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Merged nuttx/nuttx into neilh20/aNuttx:master

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neil H 2016-09-08 15:09:39 -07:00
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1232 changed files with 47869 additions and 4605 deletions
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ChangeLog
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@ -10536,8 +10536,7 @@
nuttx/libc/mqueue to nuttx/sched/mqueue. Also add syscall support
for mq_setattr() and mq_getattr(). This is necessary in protected and
kernel builds because in those cases the message queue structure is
protected and cannot be accessed directly from user mode code. Noted
by Jouko Holopainen (2015-06-03).
protected and cannot be accessed directly from user mode code (2015-06-03).
* drivers/net/tun.c: TUN driver bug fix. From Max Neklyudov (2015-06-03.
* drivers/net/Kconfig, include/nuttx/net/mii.h, and
arch/arm/src/lpc17xx/lpc17_ethernet.c: Add support for the Micrel
@ -12392,5 +12391,284 @@
banks. This fixes a race condition where the HW fills a FIFO bank
while the SW is busy, resulting in out of sequence USB packets
(2016-07-23).
* Freedom-K64F: Add PWM support. From Jordan MacIntyre (2016-07-25).
7.18 2016-xx-xx Gregory Nutt <gnutt@nuttx.org>
* drivers/serial/pty.c, serial.c, usbdev/cdcacm.c, include/nuttx/fs/ioctl.h:
Fix FIONWRITE and add FIONSPACE. All implementations of FIONWRITE
were wrong. FIONWRITE should return the number of bytes waiting in
the outgoing send queue, not the free space. Rather, FIONSPACE should
return the free space in the send queue (2016-07-25).
* lib_dumpbuffer: Now prints a large on-stack buffer first to avoid
problems when the syslog output is prefixed with time. From Pierre-
noel Bouteville (2016-07-27).
* sched/clock and sched/sched: Add standard adjtime() interface and
basic timekeeping support. Normally used with an NTP client to keep
system time in synchronizationi. From Max Neklyudov (Merged on
20160-07-28).
* arch/arm/src/stm32: Add timekeeping support for the STM32 tickless
mode. From Max Neklyudov (Merged on 20160-07-28).
* Top-Level Makefiles. Fix a chicken-and-egg problem. In the menuconfig
target, the context dependency was executed before kconfig-mconf.
That was necessary because the link at apps/platform/board needed to
be set up before creating the apps/Kconfig file. Otherwise, the
platform Kconfig files would not be included. But this introduces
the chicken-and-egg problem in some configurations.
In particular: (1) An NX graphics configuration is used that requires
auto-generation of source files using cpp, (2) the configuration is
set for Linux, but (3) we are running under Cygwin with (4) a Windows
native toolchain. In this case, POSIX-style symbolic links are set
up but the Windows native toolchain cannot follow them.
The reason we are running 'make menuconfig' is to change from Linux
to Cygwin, but the target fails. During the context phase, NX runs
CPP to generate source files but that fails because the Windows native
toolchain cannot follow the links. Checkmate.
This was fixed by changing all of the make menuconfig (and related)
targets. They no longer depend on context being run. Instead, they
depend only on the dirlinks target. The dirlinks target only sets
up the directory links but does not try to run all of the context
setup; the compiler is never invoked; no code is autogeneraed; and
things work (2016-07-28).
* tools/refresh.sh: Recent complexities added to apps/ means that
configuration needs correct Make.defs file in place in order to
configure properly (2016-07-28).
* tools/kconfig2html.c: Update to handle absolute paths when sourcing
Kconfig files (2016-07-29).
* libc/math: This fixes the following libc/math issues: (1) asin[f l]()
use Newton’s method to converge on a solution. But Newton’s method
converges very slowly (> 500,000 iterations) for values of x close
to 1.0; and, in the case of asinl(), sometimes fails to converge
(loops forever). The attached patch uses an trig identity for
values of x > sqrt(2). The resultant functions converge in no more
than 5 iterations, 6 for asinl(). (2) The NuttX erf[f l]() functions
are based on Chebyshev fitting to a good guess. The problem there’s a
bug in the implementation that causes the functions to blow up with x
near -3.0. This patch fixes that problem. It should be noted that
this method returns the error function erf(x) with fractional error
less than 1.2E-07 and that’s fine for the float version erff(), but
the same method is used for double and long double version which
will yield only slightly better precision. This patch doesn't address
the issue of lower precision for erf() and erfl(). (3) a faster
version of copysignf() for floats is included. From David S. Alessio
(2016-07-30).
* I/O Expander: Remove hard-coded PCA9555 fields from ioexpander.h
definitons. Add support for an attach() method that may be used when
any subset of pin interrupts occur (2016-07-31).
* PCA9555 Driver: Replace the signalling logic with a simple callback
using the new definitons of ioexpander.h. This repartitioning of
functionality is necessary because (1) the I/O expander driver is the
lower-lower part of any driver that uses GPIOs (include the GPIO
driver itself) and should not be interacting directly with the much
higher level application layer. And (2) in order to be compatible
with the GPIO driver (and any arbitrary upper half driver), the
PCA9555 should not directly signal, but should call back into the
upper half. The upper half driver that interacts directly with the
application is the appropriate place to be generating signal
(2016-07-31).
* drivers/ioexpander/skeleton.c: Add a skeleton I/O Expander driver
(based on the PCA9555 driver) (2016-07-31).
* I/O Expander Interface: Encode and extend I/O expander options to
include interrupt configuration (2016-07-31).
* drivers/ioexpander: Add an (untested) TCA64XX I/O Expander driver
leveraged from Project Ara (2016-07-31).
* I/O Expander Interface: Add argument to interrupt callback. Add a
method to detach the interrupt (2016-08-01).
* drivers/ioexpander: Add a GPIO lower-half driver that can be used to
register a GPIO character driver for accessing pins on an I/O expander
(2016-08-01).
* drivers/ioexpander: Add PCF8574 I/O Expander driver. Some cleanup
also of other expander drivers (2016-08-01).
* drivers/ioexpander: GPIO driver: Add IOCTLs to get the pin type and
to unregister a signal handler (2016-08-01).
* configs/sim: Add simulator-based test support for apps/examples/gpio
2016-08-01).
* drivers/sensors: Add KXJT9 Accelerometer driver from the Motorola
Moto Z MDK (2016-08-02).
* arch/arm/sim: Add a simulated I/O Expander driver (2016-08-03).
* configs/sim: Add logic to set the simulated I/O expander for testing
with apps/examples/gpio (2016-08-03).
* fs/fat: FAT performance improvement. In large files, seeking to a
position from the beginning of the file can be very time consuming.
ftell does lssek(fd, 0, SET_CURR). In that case, that is wasted time
since we are going to seek to the same position. This fix short-
circutes fat_seek() in all cases where we attempt to seek to current
position. Suggested by Nate Weibley (2016-08-03).
* tools/sethost.sh: Add sethost.sh. This is a script that you can use
to quickly change the host platform from Linux to Windows/Cygwin.
Might save you a lot of headaches (2016-08-03).
* arch/arm/src/tiva: Add tiva PWM lower-half driver implementation.
From Young (2016-08-05).
* drivers/spi/spi_transfer.c: Add a helper function that encapsulates
and manages a sequence of SPI transfers (2016-08-05).
* drivers/spi: Add an SPI character driver that will permit access to
the SPI bus for testing purposes. This driver is a simple wrapper
around spi_transfer() (2016-08-05).
* drivers/wireless: Add MFRC522 RFID ISO14443 and Mifare transceiver
driver. From Alan Carvalho de Assis (2016-08-06).
* configs/stm32f103-minimum: Add board support to MFRC522 driver. From
Alan Carvalho de Assis (2016-08-06).
* arch/renesas: Rename arch/sh to arch/renesas (2016-08-06).
* arch/arm/src/efm32, stm32, stm32l4: STM32 and EFM32 SPI drivers
adopted an incompatible conventions somewhere along the line. The
set the number of bits to negative when calling SPI_SETBITS which had
the magical side-effect of setting LSB first order of bit
transmission. This is not only a hokey way to pass control
information but is supported by no other SPI drivers. This change
three things: (1) It adds HWFEAT_LSBFIRST as a new H/W feature.
(2) It changes the implementations of SPI_SETBITS in the STM32 and
EFM32 derivers so that negated bit numbers are simply errors and it
adds the SPI_HWFEATURES method that can set the LSB bit order, and
(3) It changes all calls with negative number of bits from all
drivers: The number of bits is now always positive and SPI_HWFEATURES
is called with HWFEAT_LSBFIRST to set the bit order (2016-08-08).
* arch/arm/src/stm32: Add missing SPI2 and SPI3 support for STM32F3F3.
Add STM32F37XX DMA channel configuration. For STM32F37XX,
SYSCFG_EXTICR_PORTE defined twice. From Alan Carvalho de Assis
(2016-08-08).
* arch/arm/src/stm32: Make stm32_pwr_enablebkp thread safe. From
Max Neklyudov (2016-08-09).
* arch/arm/src/stm32: SAM3/4 GPIO: Enable peripheral clock for GPIO port
when GPIO is configured as input. The value of a GPIO input is only
sampled when the peripheral clock for the port controller the GPIO
resides in is enabled. Therefore we need to enable the clock even when
polling a GPIO. From Wolfgang Reissnegger (2016-08-09).
* arch/arm/src/tiva: Fix two bugs of tiva pwm lower-half driver
implementation. From Young (2016-08-10).
* sched/group: Explicitly initialize the group tg_exitsem with
sem_init(). The existing logic worked because the correct
initialization value is all zero, but it is better to initialize the
semaphore explicitly (2016-08-10).
* arch/arm/stm32: Fix bad pllmul values for STM32F1XX connectivity line.
STM32F1XX connectivity line supports only x4, x5, x6, x7, x8, x9 and
x6.5 values. From Michał Łyszczek (2016-08-11).
* include/nuttx/timers: Add oneshot timer lower half interface
(2016-08-11).
* arch/arm/src/stm32: Add a experimental oneshot, lower-half driver for
STM32 (2016-08-11).
* arch/arm/src/samv7: Add option to support oneshot timer without free-
running timer. Add oneshot lower half driver (2016-08-11).
* arch/arm/src/sama5: Add option to support oneshot timer without free-
running timer. Add oneshot lower half driver (2016-08-11).
* arch/arm/src/sam34: SAM4CM: Add option to support oneshot timer without
free-running timer. Add oneshot lower half driver (2016-08-11).
* arch/arm/src/stm32l4: Add oneshot lower half driver (2016-08-11).
* libc/stdlib: strtod() was not returning endptr on error conditions
(2016-08-11).
* libc/math: floor(), floorf(), and floorl(): Fix logic error. Was not
correctly handling negative integral value (2016-08-11).
* configs/sim: Add a configuration useful for testing Mini Basic
(2016-08-12).
* drivers/timers: Add an upper-half, oneshot timer character driver
(2016-08-12).
* arch/sim/src: Add a simulated oneshot lowerhalf driver (2016-08-12).
* arch/arm/src/stm32: STM32F3 SPI: Fix the number of bit setting for
the F3. That and data packing work differently on the STM32F3 than
for other STM32 parts (2016-08-12).
* arch/arm/stm32 and stm32l4: Enabling SPI DMA loses other bits in CR2
(2016-08-13).
* arch/arm/src/stm32: STM32F3 SPI: Cannot write always 16-bit value to
DR register because of how the F3 implements data packing (2016-08-13).
* Kinetis: Add support for I2C and RTC. From v01d (phreakuencies)
(2016-08-13).
* teensy 3.x i2c. From v01d (phreakuencies) (2016-08-13).
* SH1106 0.96 OLED module support (SSD1306 compatible) + I2C fixes.
From v01d (phreakuencies) (2016-08-13).
* Add support for SAMV7 DACC module. From iotr Mienkowski (2016-08-15).
* Add oneshot board initialization to stm32f103-minimum. From Alan
Carvalho de Assis (2016-08-15).
* drivers/audio/tone.c: Add Audio Tone Generator for NuttX. From Alan
Carvalho de Assis (2016-08-16).
* configs/stm32f103-minimum: Add board configuration to initialize Audio
Tone Generator. From Alan Carvalho de Assis (2016-08-16).
* STM32F411 and STM32F446 map i2c2_sda_4 to different alternate function
numbers. From Konstantin Berezenko (2016-08-17).
* STM32 DMA Fix: Change stm32 adc dma callback to send channel number
instead of index. From Konstantin Berezenko (2016-08-17).
* SAMA5: Add missing oneshot max_delay method (2016-08-18).
* configs/stm32bufferfly2: Add support for the Kamami stm32butterfly2
development board with optional ETH phy. From Michał Łyszczek
(2016-08-19).
* libc/misc: Separate XorShift128 PRNG from /dev/urandom and make it
generally available (2016-08-20).
* sched/sched_cpuload_oneshot: Use the oneshot timer with optional
entropy to measure cPU load if so configured (2016-08-20).
* drivers/usbhost/usbhost_composite.c: An an EXPERIMENTAL prototype of
how USB host support for composite devices might be implemented. This
feature is EXPERIMENTAL because (1) it is untested and (2) has some
know design issues that must be addressed before it can be of use
(2016-08-28).
* CXXFLAGS: add -fcheck-new whenever -fno-exceptions is used. From Beat
Küng (2016-08-23).
* tools/mkfsdata.pl was still generating the old-style apps/include
inclusion paths (2016-08-23).
* drivers/sensors: Add drvier for the LIS3MDL 3 axis magnetometer. From
Alexander Entinger (2016-08-23).
* drivers/sensors: Add driver for the MLX90393 3 axis magnetometer.
From Alexander Entinger (2016-08-23).
* drivers/mtd: Add Fujistu MB85RS256B ramtron support. From Beat Küng
(2016-08-23).
* drivers/sensors: Add driver for the LIS3DSH 3 axis accelerometer. From
Alexander Entinger (2016-08-24).
* drivers/sensors: Add driver for the Bosch BMG160 3 axis gyroscope.
From Alexander Entinger (2016-08-24).
* STM32: Add IAR-style STM32F1xx vectors. Tested on STM32F103RB and
STM32F107RC. From Aleksandr Vyhovanec (2016-08-24).
* libc/header files: Add POSIX type sig_atomic_t. From Sebastien
Lorquet (2016-08-24).
* libc/header files: isatty() should be prototypes in unstid.h, not
termios.h. From Sebastien Lorquet (2016-08-24).
* Documentation: Update to NuttX C coding style document with additions
discussing long comments on the right side of a statement or data
definition (2016-08-24).
* LPC43xx serial: Fix typos in LPC43 serial driver. Found by Vytautas
Lukenskas (2016-08-24).
* libc/time: This commit adds the difftime() function. The function
depends on the toolchain-dependent CONFIG_HAVE_DOUBLE so is not
available on tiny platforms. From Sebastien Lorquet (2016-08-24).
* libc/stdio: Add support for remove(). From Sebastien Lorquet
(2016-08-25).
* STM32 OTGFS device: Fix for lost first word from FIFO
1) Do not overwrite Reserved Bits in GINTSTS (per ref manual)*
2) Acknowledge all pending int on entry to ISR that are Only rc_w1*
3) Do not disable RXFVL*
4) Loop until RXFVL is cleared*
5) Only clear the NAK on the endpoint on the
OTGFS_GRXSTSD_PKTSTS_SETUPDONE to not loose the first WORD of
FIFO all the data (Bug Fix)
Changed marked *are just driver clean up and ensure ints are not lost.
The bug fix is #5
Test case open putty and observer the Set/Get LineCoding. Without this
fix #5 the Get will not match the Set, and in fact the data might be
skewed by 4 bytes, that are lost from the FIFO if the
OTGFS_DOEPCTL0_CNAK bit is set in the OTGFS_GRXSTSD_PKTSTS_SETUPRECVD
as opposed to the OTGFS_GRXSTSD_PKTSTS_SETUPDONE
Set Line Coding DATA1: 4B | 00 c2 01 00 00 00 08 | c8 1B
Get Line Coding DATA1: 4B | .. .. .. .. 00 00 08 c8 .. 00 00 07 | 7a 72
From David Sidrane (2016-08-25).
* Add system() to stdlib.h. Actual implementation is in
apps/system/system (2016-08-25).
* include/nuttx/input: Add missing prototype for btn_lower_initialize()
(2016-08-27).
* configs/stm32f103-minimum: Add board config support to SPI LCD module
JLX12864G-086. From Alan Carvalho de Assis (2016-08-28).
* net/tcp: tcp_ipvX_bind() not actually using the ported selected with
port==0. Also removes duplicate call to pkt_input(). Issues noted by
Pascal Speck (2016-08-30).
* STM32 F7: Remove duplicate call to pkt_input from Ethernet driver.
Issues noted by Pascal Speck (2016-08-30).
* STM32L4 OTGFS device: Apply stm32 fix to stm32l4. From Sebastien
Lorquet (2016-08-31).
* drivers/contactless: Remove contactless drivers from drivers/wireless
to drivers contactless. From Sebastien Lorquet (2016-08-31).
* USB host composite is at least partially functional. No longer depends
on CONFIG_EXPERIMENTAL (2016-09-02).
* MTD: Fixed cloned typos in several FLASH drivers. From Aleksandr
Vyhovanec (2016-09-02).
* MTD: SPI-based driver for Macronix MX25L3233F or MX25L6433F. From
Aleksandr Vyhovanec (2016-09-02).

4
Documentation/NuttShell.html
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@ -8,7 +8,7 @@
<tr align="center" bgcolor="#e4e4e4">
<td>
<h1><big><font color="#3c34ec"><i>NuttShell (NSH)</i></font></big></h1>
<p>Last Updated: July 20, 2016</p>
<p>Last Updated: August 4, 2016</p>
</td>
</tr>
</table>
@ -3277,7 +3277,7 @@ nsh&gt;
</tr>
<tr>
<td><b><code>mkfifo</code></b></td>
<td><code>CONFIG_NFILE_DESCRIPTORS</code> &gt; 0 &amp;&amp; <code>CONFIG_PIPES</code></td>
<td><code>CONFIG_NFILE_DESCRIPTORS</code> &gt; 0 &amp;&amp; <code>CONFIG_PIPES</code> &amp;&amp; <code>CONFIG_DEV_FIFO_SIZE</code> &gt; 0</td>
<td><code>CONFIG_NSH_DISABLE_MKFIFO</code></td>
</tr>
<tr>

42
Documentation/NuttXCCodingStandard.html
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@ -12,7 +12,7 @@
<h1><big><font color="#3c34ec">
<i>NuttX C Coding Standard</i>
</font></big></h1>
<p>Last Updated: July 28, 2015</p>
<p>Last Updated: August 24, 2016</p>
</td>
</tr>
</table>
@ -498,8 +498,8 @@
<p>
<b>Comments to the Right of Statements</b>.
Comments to the right of statements in C source files are discouraged
If such comments are used, they should at least be aligned so that the comment begins in the same comment on each line.
Comments to the right of statements in C source files are discouraged.
If such comments are used, they should be (1) very short so that they do not exceed the line width (typically 78 characters), (2) fit on one line, and (3) be aligned so that the comment begins in the same comment on each line.
</p>
<center><table width="60%" border=1>
<tr><td bgcolor="white">
@ -538,7 +538,7 @@
<p>
<b>Comments to the Right of Data Definitions</b>.
Comments to the right of a declaration with an enumeration or structure, on the other hand, are encourage.
Comments to the right of a declaration with an enumeration or structure, on the other hand, are encouraged, provided that the comments are short and do not exceed the maximum line width (usually 78 characters).
Columnar alignment of comments is very desireable (but often cannot be achieved without violating the line width).
</p>
<center><table width="60%" border=1>
@ -586,6 +586,40 @@ struct animals_s
</td></tr>
</table></center>
<p>
<b>Long Comments on the Right</b>.
Comments on the right of statements or data definitions must be short and fit on the same line without exceeding the maximum line length.
If a longer comment is needed, then it should appear above the statement of definition rather than to the right of the definition.
</p>
<center><table width="60%" border=1>
<tr><td bgcolor="white">
<p><font color="red"><b>Incorrect</b></p>
<ul><pre>
dog = cat; /* This assignment will convert what was at one time a lowly dog into a ferocious feline. */
</ul></pre></font>
</td></tr>
<tr><td bgcolor="white">
<p><font color="blue"><b>Acceptable</b></p>
<ul><pre>
dog = cat; /* This assignment will convert what was at one time a
* lowly dog into a ferocious feline. */
</ul></pre></font>
</td></tr>
<tr><td bgcolor="white">
<p><font color="green"><b>Preferred</b></p>
<ul><pre>
/* This assignment will convert what was at one time a lowly dog into a
* ferocious feline.
*/
dog = cat;
</ul></pre></font>
</td></tr>
</table></center>
<p>
<b>Note</b> that if the comment is continued on multiple lines, the comment alignment and multi-line comment rules still apply with one exception: The closing <code>*/</code> appears on the same line as the final text of the comment. This exception to the rule is enforced to keep the statements and definitions from becoming to spread out.
</p>
<p>
<b>Block comments</b>.
Block comments are only used to delimit groupings with the overall <a href="#fileorganization">file organization</a> and should not be used unless the usage is consistent with delimiting logical groupings in the program.

111
Documentation/NuttxPortingGuide.html
View File

@ -12,7 +12,7 @@
<h1><big><font color="#3c34ec">
<i>NuttX RTOS Porting Guide</i>
</font></big></h1>
<p>Last Updated: June 22, 2016</p>
<p>Last Updated: August 31, 2016</p>
</td>
</tr>
</table>
@ -948,22 +948,46 @@ drivers/
| |-- Kconfig
| |-- Make.defs
| `-- <i>(Common ADC and DAC driver source files)</i>
|-- audio/
| |-- Kconfig
| |-- Make.defs
| `-- <i>(Common audio device source files)</i>
|-- bch/
| |-- Kconfig
| |-- Make.defs
| `-- <i>(bch driver source files)</i>
|-- contactless/
| |-- Kconfig
| |-- Make.defs
| `-- <i>(Common contactless device driver source files)</i>
|-- input/
| |-- Kconfig
| |-- Make.defs
| `-- <i>(Common touchscreen and keypad driver source files)</i>
|-- ioexpander/
| |-- Kconfig
| |-- Make.defs
| `-- <i>(Common I/O expander and GPIO-related driver source files)</i>
|-- lcd/
| |-- Kconfig
| |-- Make.defs
| `-- <i>(Common LCD driver source files)</i>
|-- leds/
| |-- Kconfig
| |-- Make.defs
| `-- <i>(Common LED device driver source files)</i>
|-- loop/
| |-- Kconfig
| |-- Make.defs
| `-- <i>(Common loop device driver source files)</i>
|-- mmcsd/
| |-- Kconfig
| |-- Make.defs
| `-- <i>(Common MMC/SD card driver source files)</i>
|-- modem/
| |-- Kconfig
| |-- Make.defs
| `-- <i>(Common modem driver source files)</i>
|-- mtd/
| |-- Kconfig
| |-- Make.defs
@ -972,11 +996,19 @@ drivers/
| |-- Kconfig
| |-- Make.defs
| `-- <i>(Common network driver source files)</i>
|-- pipes/
| |-- Kconfig
| |-- Make.defs
| `-- <i>(Common pipe and FIFO driver source files)</i>
|-- power/
| |-- Kconfig
| |-- Make.defs
| `-- <i>(Common power-related driver source files)</i>
|-- sensors/
| |-- Kconfig
| |-- Make.defs
| `-- <i>(Common sensor driver source files)</i>
|-- serial/
|-- sercomm/
| |-- Kconfig
| |-- Make.defs
| `-- <i>(Files for the Calypso SERCOMM driver)</i>
@ -984,6 +1016,18 @@ drivers/
| |-- Kconfig
| |-- Make.defs
| `-- <i>(Common front-end character drivers for chip-specific UARTs)</i>
|-- spi/
| |-- Kconfig
| |-- Make.defs
| `-- <i>(Common SPI-related drivers and helper fuctions)</i>
|-- syslog/
| |-- Kconfig
| |-- Make.defs
| `-- <i>(System logging device support)</i>
|-- timers/
| |-- Kconfig
| |-- Make.defs
| `-- <i>(Timer-based device driver support)</i>
|-- usbdev/
| |-- Kconfig
| |-- Make.defs
@ -992,6 +1036,10 @@ drivers/
| |-- Kconfig
| |-- Make.defs
| `-- <i>(Common USB host driver source files)</i>
|-- usbmonitor/
| |-- Kconfig
| |-- Make.defs
| `-- <i>(USB monitor source files)</i>
|-- wireless/
| |-- Kconfig
| |-- Make.defs
@ -1088,16 +1136,32 @@ include/
| | `-- <i>(Audio driver header files)</i>
| |-binfmt/
| | `-- <i>(Binary format header files)</i>
| |-contactless/
| | `-- <i>(Contactless driver header files)</i>
| |-crypto/
| | `-- <i>(Cryptographic support header files)</i>
| |-drivers/
| | `-- <i>(Miscellaneous driver header files)</i>
| |-eeprom/
| | `-- <i>(EEPROM driver header files)</i>
| |-fs/
| | `-- <i>(File System header files)</i>
| |-input/
| | `-- <i>(Input device driver header files)</i>
| |-ioexpander/
| | `-- <i>(I/O exander and GPIO drvier header files)</i>
| |-lcd/
| | `-- <i>(LCD driver header files)</i>
| |-leds/
| | `-- <i>(LED driver header files)</i>
| |-lib/
| | `-- <i>(Non-standard C library driver header files)</i>
| |-mm/
| | `-- <i>(Memory management header files)</i>
| |-modem/
| | `-- <i>(Modem driver header files)</i>
| |-mtd/
| | `-- <i>(Memory technology device header files)</i>
| |-serial/
| | `-- <i>(Serial driver header files)</i>
| |-net/
| | `-- <i>(Networking header files)</i>
| |-nx/
@ -1114,8 +1178,12 @@ include/
| | `-- <i>(SPI driver header files)</i>
| |-syslog/
| | `-- <i>(SYSLOG header files)</i>
| |-timers/
| | `-- <i>(Timer-related driver header files)</i>
| |-usb/
| | `-- <i>(USB driver header files)</i>
| |-video/
| | `-- <i>(Video-related driver header files)</i>
| `-wireless/
| `-- <i>(Wireless device driver header files)</i>
`- sys/
@ -1148,16 +1216,28 @@ include/
</p>
<ul><pre>
libc/
|-- aio/
| `-- <i>(Implementation of functions from aio.h)</i>
|-- audio/
| `-- <i>(Implementation of audio-related functions)</i>
|-- dirent/
| `-- <i>(Implementation of functions from dirent.h)</i>
|-- fixedmath/
| `-- <i>(Implementation of functions from fixedmath.h)</i>
|-- hex2bin/
| `-- <i>(Implementation of functions from hex2bin.h)</i>
|-- libgen/
| `-- <i>(Implementation of functions from libgen.h)</i>
|-- math/
| `-- <i>(Implementation of functions from fixedmath.h)</i>
|-- misc/
| `-- <i>(Implementation of miscellaneous library functions)</i>
|-- mqueue/
| `-- <i>(Implementation of some functions from mqueue.h)</i>
|-- net/
| `-- <i>(Implementation of network-related library functions)</i>
|-- netdb/
| `-- <i>(Implementation of functions from netdb.h)</i>
|-- pthread/
| `-- <i>(Implementation of functions from pthread.h)</i>
|-- queue/
| `-- <i>(Implementation of functions from queue.h)</i>
|-- sched/
@ -1166,16 +1246,31 @@ libc/
| `-- <i>(Implementation of some functions from semaphore.h)</i>
|-- signal/
| `-- <i>(Implementation of some functions from signal.h)</i>
|-- spawn/
| `-- <i>(Implementation of some functions from spawn.h)</i>
|-- stdio/
| `-- <i>(Implementation of functions from stdio.h)</i>
|-- stdlib/
| `-- <i>(Implementation of functions from stdlib.h)</i>
|-- string/
| `-- <i>(Implementation of functions from string.h)</i>
|-- symtab/
| `-- <i>(Implementation of symbol-table library functions)</i>
|-- syslog/
| `-- <i>(Implementation of functions from syslog.h)</i>
|-- termios/
| `-- <i>(Implementation of functions from termios.h)</i>
|-- time/
| `-- <i>(Implementation of some functions from time.h)</i>
`-- unistd/
`-- <i>(Implementation of some functions from unistd.h)</i>
|-- tls/
| `-- <i>(Implementation of some functions from tls.h)</i>
|-- wqueue/
| `-- <i>(Implementation of some functions from wqueue.h)</i>
|-- unistd/
| `-- <i>(Implementation of some functions from unistd.h)</i>
`-- zoneinfo/
`-- <i>(Implementation of timezone database)</i>
</pre></ul>
<h2>2.13 <a name="DirStructLibXX">nuttx/libxx</a></h2>

6
Documentation/README.html
View File

@ -31,11 +31,11 @@ nuttx/
| |- arm/
| | `- src
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/arch/arm/src/lpc214x/README.txt" target="_blank">lpc214x/README.txt</a>
| |- sh/
| |- renesas/
| | |- include/
| | | `-<a href="https://bitbucket.org/nuttx/nuttx/src/master/arch/sh/include/README.txt" target="_blank">README.txt</a>
| | | `-<a href="https://bitbucket.org/nuttx/nuttx/src/master/arch/renesas/include/README.txt" target="_blank">README.txt</a>
| | |- src/
| | | `-<a href="https://bitbucket.org/nuttx/nuttx/src/master/arch/sh/src/README.txt" target="_blank">README.txt</a>
| | | `-<a href="https://bitbucket.org/nuttx/nuttx/src/master/arch/renesas/src/README.txt" target="_blank">README.txt</a>
| |- x86/
| | |- include/
| | | `-<a href="https://bitbucket.org/nuttx/nuttx/src/master/arch/x86/include/README.txt" target="_blank">README.txt</a>

1
Kconfig
View File

@ -1367,7 +1367,6 @@ endif # DEBUG_SPI
config DEBUG_TIMER
bool "Timer Debug Features"
default n
depends on TIMER
---help---
Enable timer debug features.

16
Makefile.unix
View File

@ -181,7 +181,7 @@ endif
BIN = nuttx$(EXEEXT)
all: $(BIN)
.PHONY: context clean_context check_context export subdir_clean clean subdir_distclean distclean apps_clean apps_distclean
.PHONY: dirlinks context clean_context check_context export subdir_clean clean subdir_distclean distclean apps_clean apps_distclean
# Target used to copy include/nuttx/lib/math.h. If CONFIG_ARCH_MATH_H is
# defined, then there is an architecture specific math.h header file
@ -315,6 +315,8 @@ ifneq ($(CONFIG_ARCH_CHIP),)
endif
dirlinks: include/arch include/arch/board include/arch/chip $(ARCH_SRC)/board $(ARCH_SRC)/chip
$(Q) $(MAKE) -C configs dirlinks TOPDIR="$(TOPDIR)"
$(Q) $(MAKE) -C $(CONFIG_APPS_DIR) dirlinks TOPDIR="$(TOPDIR)"
# context
#
@ -470,32 +472,32 @@ pass2dep: context tools/mkdeps$(HOSTEXEEXT) tools/cnvwindeps$(HOSTEXEEXT)
# location: http://ymorin.is-a-geek.org/projects/kconfig-frontends. See
# README.txt file in the NuttX tools GIT repository for additional information.
do_config: context apps_preconfig
do_config: dirlinks apps_preconfig
$(Q) APPSDIR=${CONFIG_APPS_DIR} kconfig-conf Kconfig
config: do_config clean_context
do_oldconfig: context apps_preconfig
do_oldconfig: dirlinks apps_preconfig
$(Q) APPSDIR=${CONFIG_APPS_DIR} kconfig-conf --oldconfig Kconfig
oldconfig: do_oldconfig clean_context
do_olddefconfig: context apps_preconfig
do_olddefconfig: dirlinks apps_preconfig
$(Q) APPSDIR=${CONFIG_APPS_DIR} kconfig-conf --olddefconfig Kconfig
olddefconfig: do_olddefconfig clean_context
do_menuconfig: context apps_preconfig
do_menuconfig: dirlinks apps_preconfig
$(Q) APPSDIR=${CONFIG_APPS_DIR} kconfig-mconf Kconfig
menuconfig: do_menuconfig clean_context
do_qconfig: context apps_preconfig
do_qconfig: dirlinks apps_preconfig
$(Q) APPSDIR=${CONFIG_APPS_DIR} kconfig-qconf Kconfig
qconfig: do_qconfig clean_context
gconfig: context apps_preconfig
gconfig: dirlinks apps_preconfig
$(Q) APPSDIR=${CONFIG_APPS_DIR} kconfig-gconf Kconfig
gconfig: do_gconfig clean_context

12
Makefile.win
View File

@ -174,7 +174,7 @@ endif
BIN = nuttx$(EXEEXT)
all: $(BIN)
.PHONY: context clean_context check_context configenv config oldconfig menuconfig export subdir_clean clean subdir_distclean distclean apps_clean apps_distclean
.PHONY: dirlinks context clean_context check_context configenv config oldconfig menuconfig export subdir_clean clean subdir_distclean distclean apps_clean apps_distclean
# Target used to copy include\nuttx\math.h. If CONFIG_ARCH_MATH_H is
# defined, then there is an architecture specific math.h header file
@ -335,6 +335,8 @@ endif
endif
dirlinks: include\arch include\arch\board include\arch\chip $(ARCH_SRC)\board $(ARCH_SRC)\chip
$(Q) $(MAKE) -C configs dirlinks TOPDIR="$(TOPDIR)"
$(Q) $(MAKE) -C $(CONFIG_APPS_DIR) dirlinks TOPDIR="$(TOPDIR)"
# context
#
@ -466,22 +468,22 @@ pass2dep: context tools\mkdeps$(HOSTEXEEXT)
# location: http://ymorin.is-a-geek.org/projects/kconfig-frontends. See
# misc\tools\README.txt for additional information.
do_config: context apps_preconfig
do_config: dirlinks apps_preconfig
$(Q) set APPSDIR=$(patsubst "%",%,${CONFIG_APPS_DIR})& kconfig-conf Kconfig
config: do_config clean_context
do_oldconfig: context apps_preconfig
do_oldconfig: dirlinks apps_preconfig
$(Q) set APPSDIR=$(patsubst "%",%,${CONFIG_APPS_DIR})& kconfig-conf --oldconfig Kconfig
oldconfig: do_oldconfig clean_context
do_olddefconfig: context apps_preconfig
do_olddefconfig: dirlinks apps_preconfig
$(Q) set APPSDIR=$(patsubst "%",%,${CONFIG_APPS_DIR})& kconfig-conf --olddefconfig Kconfig
olddefconfig: do_olddefconfig clean_context
do_menuconfig: context configenv apps_preconfig
do_menuconfig: dirlinks configenv apps_preconfig
$(Q) set APPSDIR=$(patsubst "%",%,${CONFIG_APPS_DIR})& kconfig-mconf Kconfig
menuconfig: do_menuconfig clean_context

43
README.txt
View File

@ -15,6 +15,7 @@ README
- NuttX Configuration Tool
- Finding Selections in the Configuration Menus
- Reveal Hidden Configuration Options
- Make Sure that You on on the Right Platform
- Comparing Two Configurations
- Incompatibilities with Older Configurations
- NuttX Configuration Tool under DOS
@ -576,6 +577,38 @@ Reveal Hidden Configuration Options
cannot be selected and has no value). About all you do is to select
the <Help> option to see what the dependencies are.
Make Sure that You on on the Right Platform
-------------------------------------------
Saved configurations may run on Linux, Cygwin (32- or 64-bit), or other
platforms. The platform characteristics can be changed use 'make
menuconfig'. Sometimes this can be confusing due to the differences
between the platforms. Enter sethost.sh
sethost.sh is a simple script that changes a configuration to your
host platform. This can greatly simplify life if you use many different
configurations. For example, if you are running on Linux and you
configure like this:
$ cd tools
$ ./configure.sh board/configuration
$ cd ..
The you can use the following command to both (1) make sure that the
configuration is up to date, AND (2) the configuration is set up
correctly for Linux:
$ tools/sethost.sh -l
Or, if you are on a Windows/Cygwin 64-bit platform:
$ tools/sethost.sh -w
Other options are available from the help option built into the
script. You can see all options with:
$ tools/sethost.sh -h
Comparing Two Configurations
----------------------------
@ -948,8 +981,12 @@ Native Windows Build
--------------------
The beginnings of a Windows native build are in place but still not often
used as of this writing. The windows native build logic initiated
if CONFIG_WINDOWS_NATIVE=y is defined in the NuttX configuration file:
used as of this writing. The build was functional but because of lack of
use may find some issues to be resolved with this build configuration.
The windows native build logic initiated if CONFIG_WINDOWS_NATIVE=y is
defined in the NuttX configuration file:
This build:
@ -1213,7 +1250,7 @@ nuttx/
| |- arm/
| | `- src
| | `- lpc214x/README.txt
| |- sh/
| |- renesas/
| | |- include/
| | | `-README.txt
| | |- src/

2
ReleaseNotes
View File

@ -9063,7 +9063,7 @@ detailed bugfix information):
for mq_setattr() and mq_getattr(). This is necessary in protected
and kernel builds because in those cases the message queue
structure is protected and cannot be accessed directly from user
mode code. Noted by Jouko Holopainen.
mode code.
* File Systems/Block Drivers/MTD:

11
TODO
View File

@ -219,7 +219,7 @@ o Task/Scheduler (sched/)
Description: Task control information is retained in simple lists. This
is completely appropriate for small embedded systems where
the number of tasks, N, is relatively small. Most list
operations are O(N). This could become as issue if N gets
operations are O(N). This could become an issue if N gets
very large.
In that case, these simple lists should be replaced with
@ -819,7 +819,7 @@ o Binary loaders (binfmt/)
"Read-Only Data in RAM" at
http://nuttx.org/Documentation/NuttXNxFlat.html#limitations).
The newer 4.6.3compiler generated PC relative relocations to the strings:
The newer 4.6.3 compiler generated PC relative relocations to the strings:
.L2:
.word .LC0-(.LPIC0+4)
@ -927,8 +927,7 @@ o Network (net/, drivers/net)
CONFIG_NET_NOINTS). This is really a very bad use of CPU
resources; All of the network stack processing should be
modified to use a work queue (and, all use of CONFIG_NET_NOINTS=n
should be eliminated). This applies to almost all Ethernet
drivers:
should be eliminated). This applies to many Ethernet drivers:
ARCHITECTURE CONFIG_NET_NOINTS? ADDRESS FILTER SUPPORT?
C5471 NO NO
@ -1340,6 +1339,8 @@ o Libraries (libc/)
UPDATE: 2015-09-01: A fix for the noted problems with asin()
has been applied.
2016-07-30: Numerous fixes and performance improvements from
David Alessio.
Status: Open
Priority: Low for casual users but clearly high if you need care about
@ -1735,7 +1736,7 @@ o ARM (arch/arm/)
upon return. This could be improved as well: If there is no
context switch, then the static registers need not be restored
because they will not be modified by the called C code.
(see arch/sh/src/sh1/sh1_vector.S for example)
(see arch/renesas/src/sh1/sh1_vector.S for example)
Status: Open
Priority: Low

24
arch/Kconfig
View File

@ -45,7 +45,7 @@ config ARCH_RGMP
RTOS and GPOS on Multi-Processor (RGMP) architecture. See
http://rgmp.sourceforge.net/wiki/index.php/Main_Page.
config ARCH_SH
config ARCH_RENESAS
bool "Renesas"
select ARCH_NOINTC
select ARCH_HAVE_INTERRUPTSTACK
@ -83,23 +83,23 @@ endchoice
config ARCH
string
default "arm" if ARCH_ARM
default "avr" if ARCH_AVR
default "hc" if ARCH_HC
default "mips" if ARCH_MIPS
default "rgmp" if ARCH_RGMP
default "sh" if ARCH_SH
default "sim" if ARCH_SIM
default "x86" if ARCH_X86
default "z16" if ARCH_Z16
default "z80" if ARCH_Z80
default "arm" if ARCH_ARM
default "avr" if ARCH_AVR
default "hc" if ARCH_HC
default "mips" if ARCH_MIPS
default "rgmp" if ARCH_RGMP
default "renesas" if ARCH_RENESAS
default "sim" if ARCH_SIM
default "x86" if ARCH_X86
default "z16" if ARCH_Z16
default "z80" if ARCH_Z80
source arch/arm/Kconfig
source arch/avr/Kconfig
source arch/hc/Kconfig
source arch/mips/Kconfig
source arch/rgmp/Kconfig
source arch/sh/Kconfig
source arch/renesas/Kconfig
source arch/sim/Kconfig
source arch/x86/Kconfig
source arch/z16/Kconfig

23
arch/README.txt
View File

@ -150,11 +150,13 @@ arch/arm - ARM-based micro-controllers
Architecture Support
arch/arm/include and arch/arm/src/common
arch/arm/src/arm and arch/arm/include/arm
arch/arm/src/armv7-a and arch/arm/include/armv6-m
arch/arm/src/armv7-a and arch/arm/include/armv7-a
arch/arm/src/armv7-m and arch/arm/include/armv7-m
arch/arm/src/armv7-r and arch/arm/include/armv7-4
arch/arm/src/armv7-r and arch/arm/include/armv7-r
MCU support
arch/arm/include/a1x and arch/arm/src/a1x
arch/arm/include/c5471 and arch/arm/src/c5471
arch/arm/include/calypso and arch/arm/src/calypso
arch/arm/include/dm320 and arch/arm/src/dm320
@ -210,6 +212,16 @@ arch/mips
arch/mips/include/pic32mx and arch/mips/src/pic32mx
arch/mips/include/pic32mz and arch/mips/src/pic32mz
arch/renesas - Support for Renesas and legacy Hitachi microcontrollers.
This include SuperH and M16C.
Architecture Support
arch/renesas/include and arch/renesas/src/common
MCU support
arch/renesas/include/m16c and arch/renesas/src/m16c
arch/renesas/include/sh1 and arch/renesas/src/sh1
arch/rgmp
RGMP stands for RTOS and GPOS on Multi-Processor. RGMP is a project
@ -221,15 +233,6 @@ arch/rgmp
See http://rgmp.sourceforge.net/wiki/index.php/Main_Page for further
information about RGMP.
arch/sh - SuperH and related Hitachi/Renesas microcontrollers
Architecture Support
arch/sh/include and arch/sh/src/common
MCU support
arch/sh/include/m16c and arch/sh/src/m16c
arch/sh/include/sh1 and arch/sh/src/sh1
arch/x86 - Intel x86 architectures
This directory holds related, 32- and 64-bit architectures from Intel.
At present, this includes the following subdirectories:

22
arch/arm/Kconfig
View File

@ -51,6 +51,7 @@ config ARCH_CHIP_DM320
config ARCH_CHIP_EFM32
bool "Energy Micro"
select ARCH_HAVE_CMNVECTOR
select ARCH_HAVE_SPI_BITORDER
select ARMV7M_CMNVECTOR
---help---
Energy Micro EFM32 microcontrollers (ARM Cortex-M).
@ -206,14 +207,15 @@ config ARCH_CHIP_SAM34
config ARCH_CHIP_SAMV7
bool "Atmel SAMV7"
select ARCH_HAVE_CMNVECTOR
select ARMV7M_CMNVECTOR
select ARCH_CORTEXM7
select ARCH_HAVE_MPU
select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_RAMFUNCS
select ARCH_HAVE_TICKLESS
select ARMV7M_HAVE_STACKCHECK
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_SPI_CS_CONTROL
select ARM_HAVE_MPU_UNIFIED
select ARMV7M_CMNVECTOR
select ARMV7M_HAVE_STACKCHECK
---help---
Atmel SAMV7 (ARM Cortex-M7) architectures
@ -221,10 +223,12 @@ config ARCH_CHIP_STM32
bool "STMicro STM32 F1/F2/F3/F4"
select ARCH_HAVE_CMNVECTOR
select ARCH_HAVE_MPU
select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_HEAPCHECK
select ARCH_HAVE_TICKLESS
select ARCH_HAVE_TIMEKEEPING
select ARCH_HAVE_SPI_BITORDER
select ARM_HAVE_MPU_UNIFIED
select ARMV7M_HAVE_STACKCHECK
---help---
STMicro STM32 architectures (ARM Cortex-M3/4).
@ -232,12 +236,13 @@ config ARCH_CHIP_STM32
config ARCH_CHIP_STM32F7
bool "STMicro STM32 F7"
select ARCH_HAVE_CMNVECTOR
select ARMV7M_CMNVECTOR
select ARCH_CORTEXM7
select ARCH_HAVE_MPU
select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_HEAPCHECK
select ARCH_HAVE_SPI_BITORDER
select ARM_HAVE_MPU_UNIFIED
select ARMV7M_CMNVECTOR
select ARMV7M_HAVE_STACKCHECK
---help---
STMicro STM32 architectures (ARM Cortex-M7).
@ -245,13 +250,14 @@ config ARCH_CHIP_STM32F7
config ARCH_CHIP_STM32L4
bool "STMicro STM32 L4"
select ARCH_HAVE_CMNVECTOR
select ARMV7M_CMNVECTOR
select ARCH_CORTEXM4
select ARCH_HAVE_MPU
select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_HEAPCHECK
select ARCH_HAVE_TICKLESS
select ARCH_HAVE_SPI_BITORDER
select ARM_HAVE_MPU_UNIFIED
select ARMV7M_CMNVECTOR
select ARMV7M_HAVE_STACKCHECK
---help---
STMicro STM32 architectures (ARM Cortex-M4).

6
arch/arm/include/calypso/clock.h
View File

@ -1,5 +1,5 @@
#ifndef _CALYPSO_CLK_H
#define _CALYPSO_CLK_H
#ifndef __ARCH_ARM_INCLUDE_CALYPSO_CLOCK_H
#define __ARCH_ARM_INCLUDE_CALYPSO_CLOCK_H
#include <stdint.h>
@ -64,4 +64,4 @@ void calypso_debugunit(int enable);
void calypso_rhea_cfg(uint8_t fac0, uint8_t fac1, uint8_t timeout,
uint8_t ws_h, uint8_t ws_l, uint8_t w_en0, uint8_t w_en1);
#endif /* _CALYPSO_CLK_H */
#endif /* __ARCH_ARM_INCLUDE_CALYPSO_CLOCK_H */

6
arch/arm/include/calypso/debug.h
View File

@ -1,5 +1,5 @@
#ifndef _DEBUG_H
#define _DEBUG_H
#ifndef __ARCH_ARM_INCLUDE_CALYPSO_DEBUG_H
#define __ARCH_ARM_INCLUDE_CALYPSO_DEBUG_H
#ifndef ARRAY_SIZE
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
@ -28,4 +28,4 @@
#define printd(x, args ...)
#endif
#endif /* _DEBUG_H */
#endif /* __ARCH_ARM_INCLUDE_CALYPSO_DEBUG_H */

7
arch/arm/include/calypso/defines.h
View File

@ -1,6 +1,5 @@
#ifndef _DEFINES_H
#define _DEFINES_H
#ifndef __ARCH_ARM_INCLUDE_CALYPSO_DEFINES_H
#define __ARCH_ARM_INCLUDE_CALYPSO_DEFINES_H
#define __attribute_const__ __attribute__((__const__))
@ -15,4 +14,4 @@
/* force placement in zero-waitstate memory */
#define __ramtext __section(".ramtext")
#endif /* !_DEFINES_H */
#endif /* !__ARCH_ARM_INCLUDE_CALYPSO_DEFINES_H */

6
arch/arm/include/calypso/irq.h
View File

@ -41,8 +41,8 @@
#error "This file should never be included directly! Use <nuttx/irq.h>"
#endif
#ifndef _CALYPSO_IRQ_H
#define _CALYPSO_IRQ_H
#ifndef __ARCH_ARM_INCLUDE_CALYPSO_IRQ_H
#define __ARCH_ARM_INCLUDE_CALYPSO_IRQ_H
#ifndef __ASSEMBLY__
@ -78,4 +78,4 @@ enum irq_nr {
#define IRQ_SYSTIMER IRQ_TIMER2
#endif /* _CALYPSO_IRQ_H */
#endif /* __ARCH_ARM_INCLUDE_CALYPSO_IRQ_H */

6
arch/arm/include/calypso/memory.h
View File

@ -1,5 +1,5 @@
#ifndef _MEMORY_H
#define _MEMORY_H
#ifndef __ARCH_ARM_INCLUDE_CALYPSO_MEMORY_H
#define __ARCH_ARM_INCLUDE_CALYPSO_MEMORY_H
#define __arch_getb(a) (*(volatile unsigned char *)(a))
#define __arch_getw(a) (*(volatile unsigned short *)(a))
@ -25,4 +25,4 @@
#define readw(a) __arch_getw(a)
#define readl(a) __arch_getl(a)
#endif /* _MEMORY_H */
#endif /* __ARCH_ARM_INCLUDE_CALYPSO_MEMORY_H */

6
arch/arm/include/calypso/timer.h
View File

@ -1,5 +1,5 @@
#ifndef _CAL_TIMER_H
#define _CAL_TIMER_H
#ifndef __ARCH_ARM_INCLUDE_CALYPSO_TIMER_H
#define __ARCH_ARM_INCLUDE_CALYPSO_TIMER_H
/* Enable or Disable a timer */
void hwtimer_enable(int num, int on);
@ -22,4 +22,4 @@ void wdog_reset(void);
/* power up the timers */
void hwtimer_init(void);
#endif /* _CAL_TIMER_H */
#endif /* __ARCH_ARM_INCLUDE_CALYPSO_TIMER_H */

4
arch/arm/include/calypso/uwire.h
View File

@ -1,5 +1,5 @@
#ifndef _CALYPSO_UWIRE_H
#define _CALYPSO_UWIRE_H
#ifndef __ARCH_ARM_INCLUDE_CALYPSO_UWIRE_H
#define __ARCH_ARM_INCLUDE_CALYPSO_UWIRE_H
void uwire_init(void);
int uwire_xfer(int cs, int bitlen, const void *dout, void *din);
#endif

6
arch/arm/include/lpc214x/irq.h
View File

@ -37,8 +37,8 @@
* only indirectly through nuttx/irq.h
*/
#ifndef __ARCH_LPC214X_IRQ_H
#define __ARCH_LPC214X_IRQ_H
#ifndef __ARCH_ARM_INCLUDE_LPC214X_IRQ_H
#define __ARCH_ARM_INCLUDE_LPC214X_IRQ_H
/****************************************************************************
* Included Files
@ -127,5 +127,5 @@ void up_detach_vector(int vector);
#endif
#endif
#endif /* __ARCH_LPC214X_IRQ_H */
#endif /* __ARCH_ARM_INCLUDE_LPC214X_IRQ_H */

6
arch/arm/include/lpc2378/irq.h
View File

@ -43,8 +43,8 @@
* only indirectly through nuttx/irq.h
*/
#ifndef __ARCH_LPC2378_IRQ_H
#define __ARCH_LPC2378_IRQ_H
#ifndef __ARCH_ARM_INCLUDE_LPC2378_IRQ_H
#define __ARCH_ARM_INCLUDE_LPC2378_IRQ_H
/****************************************************************************
* Included Files
@ -149,4 +149,4 @@ void up_detach_vector(int vector);
#endif
#endif
#endif /* __ARCH_LPC2378_IRQ_H */
#endif /* __ARCH_ARM_INCLUDE_LPC2378_IRQ_H */

8
arch/arm/src/c5471/chip.h
View File

@ -1,5 +1,5 @@
/****************************************************************************
* c5471/chip.h
* arch/arm/src/c5471/chip.h
*
* Copyright (C) 2007 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -33,8 +33,8 @@
*
****************************************************************************/
#ifndef __C5471_CHIP_H
#define __C5471_CHIP_H
#ifndef __ARCH_ARM_SRC_C5471_CHIP_H
#define __ARCH_ARM_SRC_C5471_CHIP_H
/****************************************************************************
* Included Files
@ -368,4 +368,4 @@
* Public Function Prototypes
****************************************************************************/
#endif /* __C5471_CHIP_H */
#endif /* __ARCH_ARM_SRC_C5471_CHIP_H */

6
arch/arm/src/calypso/chip.h
View File

@ -37,8 +37,8 @@
*
****************************************************************************/
#ifndef __CALYPSO_CHIP_H
#define __CALYPSO_CHIP_H
#ifndef __ARCH_ARM_SRC_CALYPSO_CHIP_H
#define __ARCH_ARM_SRC_CALYPSO_CHIP_H
/****************************************************************************
* Included Files
@ -208,4 +208,4 @@
* Public Function Prototypes
****************************************************************************/
#endif /* __CALYPSO_CHIP_H */
#endif /* __ARCH_ARM_SRC_CALYPSO_CHIP_H */

6
arch/arm/src/dm320/chip.h
View File

@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __DM320_CHIP_H
#define __DM320_CHIP_H
#ifndef __ARCH_ARM_SRC_DM320_CHIP_H
#define __ARCH_ARM_SRC_DM320_CHIP_H
/************************************************************************************
* Included Files
@ -58,4 +58,4 @@
* Inline Functions
************************************************************************************/
#endif /* __DM320_CHIP_H */
#endif /* __ARCH_ARM_SRC_DM320_CHIP_H */

6
arch/arm/src/dm320/dm320_emif.h
View File

@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __DM320_DM320_EMIF_H
#define __DM320_DM320_EMIF_H
#ifndef __ARCH_ARM_SRC_DM320_DM320_EMIF_H
#define __ARCH_ARM_SRC_DM320_DM320_EMIF_H
/************************************************************************************
* Included Files
@ -105,4 +105,4 @@
#endif
#endif /* __DM320_DM320_EMIF_H */
#endif /* __ARCH_ARM_SRC_DM320_DM320_EMIF_H */

4
arch/arm/src/dm320/dm320_gio.h
View File

@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __DM320_DM320GIO_H
#define __DM320_DM320GIO_H
#ifndef __ARCH_ARM_SRC_DM320_DM320_GIO_H
#define __ARCH_ARM_SRC_DM320_DM320_GIO_H
/************************************************************************************
* Included Files

6
arch/arm/src/dm320/dm320_intc.h
View File

@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __DM320_DM320_INTC_H
#define __DM320_DM320_INTC_H
#ifndef __ARCH_ARM_SRC_DM320_DM320_INTC_H
#define __ARCH_ARM_SRC_DM320_DM320_INTC_H
/************************************************************************************
* Included Files
@ -98,4 +98,4 @@
#endif
#endif /* __DM320_DM320_INTC_H */
#endif /* __ARCH_ARM_SRC_DM320_DM320_INTC_H */

6
arch/arm/src/dm320/dm320_memorymap.h
View File

@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __DM320_MEMORYMAP_H
#define __DM320_MEMORYMAP_H
#ifndef __ARCH_ARM_SRC_DM320_DM320_MEMORYMAP_H
#define __ARCH_ARM_SRC_DM320_DM320_MEMORYMAP_H
/************************************************************************************
* Included Files
@ -261,4 +261,4 @@
#endif
#endif /* __DM320_MEMORYMAP_H */
#endif /* __ARCH_ARM_SRC_DM320_DM320_MEMORYMAP_H */

6
arch/arm/src/dm320/dm320_timer.h
View File

@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __DM320_TIMER_H
#define __DM320_TIMER_H
#ifndef __ARCH_ARM_SRC_DM320_DM320_TIMER_H
#define __ARCH_ARM_SRC_DM320_DM320_TIMER_H
/************************************************************************************
* Included Files
@ -105,4 +105,4 @@
#endif
#endif /* __DM320_TIMER_H */
#endif /* __ARCH_ARM_SRC_DM320_DM320_TIMER_H */

6
arch/arm/src/dm320/dm320_uart.h
View File

@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __DM320_UART_H
#define __DM320_UART_H
#ifndef __ARCH_ARM_SRC_DM320_DM320_UART_H
#define __ARCH_ARM_SRC_DM320_DM320_UART_H
/************************************************************************************
* Included Files
@ -173,4 +173,4 @@
* Inline Functions
************************************************************************************/
#endif /* __DM320_UART_H */
#endif /* __ARCH_ARM_SRC_DM320_DM320_UART_H */

112
arch/arm/src/efm32/efm32_spi.c
View File

@ -185,6 +185,10 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev,
uint32_t frequency);
static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode);
static void spi_setbits(struct spi_dev_s *dev, int nbits);
#ifdef CONFIG_SPI_HWFEATURES
static int spi_hwfeatures(FAR struct spi_dev_s *dev,
spi_hwfeatures_t features);
#endif
static uint8_t spi_status(struct spi_dev_s *dev, enum spi_dev_e devid);
#ifdef CONFIG_SPI_CMDDATA
static int spi_cmddata(struct spi_dev_s *dev, enum spi_dev_e devid,
@ -218,7 +222,7 @@ static const struct spi_ops_s g_spiops =
.setmode = spi_setmode,
.setbits = spi_setbits,
#ifdef CONFIG_SPI_HWFEATURES
.hwfeatures = 0,
.hwfeatures = spi_hwfeatures,
#endif
.status = spi_status,
#ifdef CONFIG_SPI_CMDDATA
@ -976,47 +980,16 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits)
const struct efm32_spiconfig_s *config;
uint32_t regval;
uint32_t setting;
bool lsbfirst;
spiinfo("nbits=%d\n", nbits);
DEBUGASSERT(priv && priv->config);
config = priv->config;
/* Bit order is encoded by the sign of nbits */
/* Has the number of bits changed? */
if (nbits < 0)
if (nbits != priv->nbits)
{
/* LSB first */
lsbfirst = true;
nbits = -nbits;
}
else
{
/* MSH first */
lsbfirst = false;
}
/* Has the number of bits or the bit order changed? */
if (nbits != priv->nbits || lsbfirst != priv->lsbfirst)
{
/* Set the new bit order */
regval = spi_getreg(config, EFM32_USART_CTRL_OFFSET);
if (lsbfirst)
{
regval &= ~USART_CTRL_MSBF;
}
else
{
regval |= USART_CTRL_MSBF;
}
spi_putreg(config, EFM32_USART_CTRL_OFFSET, regval);
/* Select the new number of bits */
switch (nbits)
@ -1086,11 +1059,78 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits)
* faster
*/
priv->nbits = nbits;
priv->lsbfirst = lsbfirst;
priv->nbits = nbits;
}
}
/****************************************************************************
* Name: spi_hwfeatures
*
* Description:
* Set hardware-specific feature flags.
*
* Input Parameters:
* dev - Device-specific state data
* features - H/W feature flags
*
* Returned Value:
* Zero (OK) if the selected H/W features are enabled; A negated errno
* value if any H/W feature is not supportable.
*
****************************************************************************/
#ifdef CONFIG_SPI_HWFEATURES
static int spi_hwfeatures(FAR struct spi_dev_s *dev, spi_hwfeatures_t features)
{
#ifdef CONFIG_SPI_BITORDER
struct efm32_spidev_s *priv = (struct efm32_spidev_s *)dev;
const struct efm32_spiconfig_s *config;
uint32_t regval;
bool lsbfirst;
spiinfo("features=%08x\n", features);
DEBUGASSERT(priv && priv->config);
config = priv->config;
/* Bit order is encoded by the sign of nbits */
lsbfirst = ((features & HWFEAT_LSBFIRST) != 0);
/* Has the number of bits or the bit order changed? */
if (lsbfirst != priv->lsbfirst)
{
/* Set the new bit order */
regval = spi_getreg(config, EFM32_USART_CTRL_OFFSET);
if (lsbfirst)
{
regval &= ~USART_CTRL_MSBF;
}
else
{
regval |= USART_CTRL_MSBF;
}
spi_putreg(config, EFM32_USART_CTRL_OFFSET, regval);
/* Save the selection so the subsequence re-configurations will be
* faster
*/
priv->lsbfirst = lsbfirst;
}
/* Other H/W features are not supported */
return ((features & ~HWFEAT_LSBFIRST) == 0) ? OK : -ENOSYS;
#else
return -ENOSYS;
#endif
}
#endif
/****************************************************************************
* Name: spi_status
*

60
arch/arm/src/kinetis/Kconfig
View File

@ -37,94 +37,130 @@ config ARCH_CHIP_MK20DX128VLH5
config ARCH_CHIP_MK20DX64VLH7
bool "MK20DX64VLH7"
select ARCH_FAMILY_K20
select KINETIS_HAVE_I2C1
config ARCH_CHIP_MK20DX128VLH7
bool "MK20DX128VLH7"
select ARCH_FAMILY_K20
select KINETIS_HAVE_I2C1
config ARCH_CHIP_MK20DX256VLH7
bool "MK20DX256VLH7"
select ARCH_FAMILY_K20
select KINETIS_HAVE_I2C1
config ARCH_CHIP_MK40N512VLQ100
bool "MK40N512VLQ100"
select ARCH_FAMILY_K40
select KINETIS_HAVE_I2C1
config ARCH_CHIP_MK40N512VMD100
bool "MK40N512VMD100"
select ARCH_FAMILY_K40
select KINETIS_HAVE_I2C1
config ARCH_CHIP_MK40X128VLQ100
bool "MK40X128VLQ100"
select ARCH_FAMILY_K40
select KINETIS_HAVE_I2C1
config ARCH_CHIP_MK40X128VMD100
bool "MK40X128VMD100"
select ARCH_FAMILY_K40
select KINETIS_HAVE_I2C1
config ARCH_CHIP_MK40X256VLQ100
bool "MK40X256VLQ100"
select ARCH_FAMILY_K40
select KINETIS_HAVE_I2C1
config ARCH_CHIP_MK40X256VMD100
bool "MK40X256VMD100"
select ARCH_FAMILY_K40
select KINETIS_HAVE_I2C1
config ARCH_CHIP_MK60N256VLQ100
bool "MK60N256VLQ100"
select ARCH_FAMILY_K60
select KINETIS_HAVE_I2C1
config ARCH_CHIP_MK60N256VMD100
bool "MK60N256VMD100"
select ARCH_FAMILY_K60
select KINETIS_HAVE_I2C1
select KINETIS_HAVE_I2C2
config ARCH_CHIP_MK60N512VLL100
bool "MK60N512VLL100"
select ARCH_FAMILY_K60
select KINETIS_HAVE_I2C1
select KINETIS_HAVE_I2C2
config ARCH_CHIP_MK60N512VLQ100
bool "MK60N512VLQ100"
select ARCH_FAMILY_K60
select KINETIS_HAVE_I2C1
select KINETIS_HAVE_I2C2
config ARCH_CHIP_MK60N512VMD100
bool "MK60N512VMD100"
select ARCH_FAMILY_K60
select KINETIS_HAVE_I2C1
select KINETIS_HAVE_I2C2
config ARCH_CHIP_MK60X256VLQ100
bool "MK60X256VLQ100"
select ARCH_FAMILY_K60
select KINETIS_HAVE_I2C1
select KINETIS_HAVE_I2C2
config ARCH_CHIP_MK60X256VMD100
bool "MK60X256VMD100"
select ARCH_FAMILY_K60
select KINETIS_HAVE_I2C1
select KINETIS_HAVE_I2C2
config ARCH_CHIP_MK64FN1M0VLL12
bool "MK64FN1M0VLL12"
select ARCH_FAMILY_K64
select KINETIS_HAVE_I2C1
select KINETIS_HAVE_I2C2
config ARCH_CHIP_MK64FX512VLL12
bool "MK64FX512VLL12"
select ARCH_FAMILY_K64
select KINETIS_HAVE_I2C1
select KINETIS_HAVE_I2C2
config ARCH_CHIP_MK64FX512VDC12
bool "MK64FX512VDC12"
select ARCH_FAMILY_K64
select KINETIS_HAVE_I2C1
select KINETIS_HAVE_I2C2
config ARCH_CHIP_MK64FN1M0VDC12
bool "MK64FN1M0VDC12"
select ARCH_FAMILY_K64
select KINETIS_HAVE_I2C1
select KINETIS_HAVE_I2C2
config ARCH_CHIP_MK64FX512VLQ12
bool "MK64FX512VLQ12"
select ARCH_FAMILY_K64
select KINETIS_HAVE_I2C1
select KINETIS_HAVE_I2C2
config ARCH_CHIP_MK64FX512VMD12
bool "MK64FX512VMD12"
select ARCH_FAMILY_K64
select KINETIS_HAVE_I2C1
select KINETIS_HAVE_I2C2
config ARCH_CHIP_MK64FN1M0VMD12
bool "MK64FN1M0VMD12"
select ARCH_FAMILY_K64
select KINETIS_HAVE_I2C1
select KINETIS_HAVE_I2C2
endchoice
@ -148,6 +184,14 @@ config ARCH_FAMILY_K64
menu "Kinetis Peripheral Support"
config KINETIS_HAVE_I2C1
bool
default n
config KINETIS_HAVE_I2C2
bool
default n
config KINETIS_TRACE
bool "Trace"
default n
@ -255,12 +299,23 @@ config KINETIS_SPI2
config KINETIS_I2C0
bool "I2C0"
default n
select I2C
---help---
Support I2C0
config KINETIS_I2C1
bool "I2C1"
default n
select I2C
depends on KINETIS_HAVE_I2C1
---help---
Support I2C1
config KINETIS_I2C2
bool "I2C2"
default n
select I2C
depends on KINETIS_HAVE_I2C2
---help---
Support I2C1
@ -418,6 +473,9 @@ config KINETIS_PIT
endmenu
menu "Kinetis FTM PWM Configuration"
depends on KINETIS_FTM0 || KINETIS_FTM1 || KINETIS_FTM2
config KINETIS_FTM0_PWM
bool "FTM0 PWM"
default n
@ -481,6 +539,8 @@ config KINETIS_FTM2_CHANNEL
If FTM2 is enabled for PWM usage, you also need specifies the timer output
channel {0,..,1}
endmenu # Kinetis FTM PWM Configuration
menu "Kinetis GPIO Interrupt Configuration"
config KINETIS_GPIOIRQ

10
arch/arm/src/kinetis/Make.defs
View File

@ -1,7 +1,7 @@
############################################################################
# arch/arm/src/kinetis/Make.defs
#
# Copyright (C) 2011, 2013-2015 Gregory Nutt. All rights reserved.
# Copyright (C) 2011, 2013-2016 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <gnutt@nuttx.org>
#
# Redistribution and use in source and binary forms, with or without
@ -131,6 +131,14 @@ ifeq ($(CONFIG_PWM),y)
CHIP_CSRCS += kinetis_pwm.c
endif
ifeq ($(CONFIG_I2C),y)
CHIP_CSRCS += kinetis_i2c.c
endif
ifeq ($(CONFIG_RTC),y)
CHIP_CSRCS += kinetis_rtc.c
endif
ifeq ($(CONFIG_NET),y)
ifeq ($(CONFIG_KINETIS_ENET),y)
CHIP_CSRCS += kinetis_enet.c

149
arch/arm/src/kinetis/chip/kinetis_i2c.h
View File

@ -78,31 +78,35 @@
#define KINETIS_I2C0_SLTH (KINETIS_I2C0_BASE+KINETIS_I2C_SLTH_OFFSET)
#define KINETIS_I2C0_SLTL (KINETIS_I2C0_BASE+KINETIS_I2C_SLTL_OFFSET)
#define KINETIS_I2C1_A1 (KINETIS_I2C1_BASE+KINETIS_I2C_A1_OFFSET)
#define KINETIS_I2C1_F (KINETIS_I2C1_BASE+KINETIS_I2C_F_OFFSET)
#define KINETIS_I2C1_C1 (KINETIS_I2C1_BASE+KINETIS_I2C_C1_OFFSET)
#define KINETIS_I2C1_S (KINETIS_I2C1_BASE+KINETIS_I2C_S_OFFSET)
#define KINETIS_I2C1_D (KINETIS_I2C1_BASE+KINETIS_I2C_D_OFFSET)
#define KINETIS_I2C1_C2 (KINETIS_I2C1_BASE+KINETIS_I2C_C2_OFFSET)
#define KINETIS_I2C1_FLT (KINETIS_I2C1_BASE+KINETIS_I2C_FLT_OFFSET)
#define KINETIS_I2C1_RA (KINETIS_I2C1_BASE+KINETIS_I2C_RA_OFFSET)
#define KINETIS_I2C1_SMB (KINETIS_I2C1_BASE+KINETIS_I2C_SMB_OFFSET)
#define KINETIS_I2C1_A2 (KINETIS_I2C1_BASE+KINETIS_I2C_A2_OFFSET)
#define KINETIS_I2C1_SLTH (KINETIS_I2C1_BASE+KINETIS_I2C_SLTH_OFFSET)
#define KINETIS_I2C1_SLTL (KINETIS_I2C1_BASE+KINETIS_I2C_SLTL_OFFSET)
#ifdef CONFIG_KINETIS_HAVE_I2C1
# define KINETIS_I2C1_A1 (KINETIS_I2C1_BASE+KINETIS_I2C_A1_OFFSET)
# define KINETIS_I2C1_F (KINETIS_I2C1_BASE+KINETIS_I2C_F_OFFSET)
# define KINETIS_I2C1_C1 (KINETIS_I2C1_BASE+KINETIS_I2C_C1_OFFSET)
# define KINETIS_I2C1_S (KINETIS_I2C1_BASE+KINETIS_I2C_S_OFFSET)
# define KINETIS_I2C1_D (KINETIS_I2C1_BASE+KINETIS_I2C_D_OFFSET)
# define KINETIS_I2C1_C2 (KINETIS_I2C1_BASE+KINETIS_I2C_C2_OFFSET)
# define KINETIS_I2C1_FLT (KINETIS_I2C1_BASE+KINETIS_I2C_FLT_OFFSET)
# define KINETIS_I2C1_RA (KINETIS_I2C1_BASE+KINETIS_I2C_RA_OFFSET)
# define KINETIS_I2C1_SMB (KINETIS_I2C1_BASE+KINETIS_I2C_SMB_OFFSET)
# define KINETIS_I2C1_A2 (KINETIS_I2C1_BASE+KINETIS_I2C_A2_OFFSET)
# define KINETIS_I2C1_SLTH (KINETIS_I2C1_BASE+KINETIS_I2C_SLTH_OFFSET)
# define KINETIS_I2C1_SLTL (KINETIS_I2C1_BASE+KINETIS_I2C_SLTL_OFFSET)
#endif
#define KINETIS_I2C2_A1 (KINETIS_I2C2_BASE+KINETIS_I2C_A1_OFFSET)
#define KINETIS_I2C2_F (KINETIS_I2C2_BASE+KINETIS_I2C_F_OFFSET)
#define KINETIS_I2C2_C1 (KINETIS_I2C2_BASE+KINETIS_I2C_C1_OFFSET)
#define KINETIS_I2C2_S (KINETIS_I2C2_BASE+KINETIS_I2C_S_OFFSET)
#define KINETIS_I2C2_D (KINETIS_I2C2_BASE+KINETIS_I2C_D_OFFSET)
#define KINETIS_I2C2_C2 (KINETIS_I2C2_BASE+KINETIS_I2C_C2_OFFSET)
#define KINETIS_I2C2_FLT (KINETIS_I2C2_BASE+KINETIS_I2C_FLT_OFFSET)
#define KINETIS_I2C2_RA (KINETIS_I2C2_BASE+KINETIS_I2C_RA_OFFSET)
#define KINETIS_I2C2_SMB (KINETIS_I2C2_BASE+KINETIS_I2C_SMB_OFFSET)
#define KINETIS_I2C2_A2 (KINETIS_I2C2_BASE+KINETIS_I2C_A2_OFFSET)
#define KINETIS_I2C2_SLTH (KINETIS_I2C2_BASE+KINETIS_I2C_SLTH_OFFSET)
#define KINETIS_I2C2_SLTL (KINETIS_I2C2_BASE+KINETIS_I2C_SLTL_OFFSET)
#ifdef CONFIG_KINETIS_HAVE_I2C2
# define KINETIS_I2C2_A1 (KINETIS_I2C2_BASE+KINETIS_I2C_A1_OFFSET)
# define KINETIS_I2C2_F (KINETIS_I2C2_BASE+KINETIS_I2C_F_OFFSET)
# define KINETIS_I2C2_C1 (KINETIS_I2C2_BASE+KINETIS_I2C_C1_OFFSET)
# define KINETIS_I2C2_S (KINETIS_I2C2_BASE+KINETIS_I2C_S_OFFSET)
# define KINETIS_I2C2_D (KINETIS_I2C2_BASE+KINETIS_I2C_D_OFFSET)
# define KINETIS_I2C2_C2 (KINETIS_I2C2_BASE+KINETIS_I2C_C2_OFFSET)
# define KINETIS_I2C2_FLT (KINETIS_I2C2_BASE+KINETIS_I2C_FLT_OFFSET)
# define KINETIS_I2C2_RA (KINETIS_I2C2_BASE+KINETIS_I2C_RA_OFFSET)
# define KINETIS_I2C2_SMB (KINETIS_I2C2_BASE+KINETIS_I2C_SMB_OFFSET)
# define KINETIS_I2C2_A2 (KINETIS_I2C2_BASE+KINETIS_I2C_A2_OFFSET)
# define KINETIS_I2C2_SLTH (KINETIS_I2C2_BASE+KINETIS_I2C_SLTH_OFFSET)
# define KINETIS_I2C2_SLTL (KINETIS_I2C2_BASE+KINETIS_I2C_SLTL_OFFSET)
#endif
/* Register Bit Definitions *****************************************************************/
@ -115,12 +119,90 @@
#define I2C_F_ICR_SHIFT (0) /* Bits 0-5: Clock rate */
#define I2C_F_ICR_MASK (0x3f << I2C_F_ICR_SHIFT)
# define I2C_F_ICR(n) ((uint8_t)(n) << I2C_F_ICR_SHIFT)
#define I2C_F_MULT_SHIFT (6) /* Bits 6-7: Multiplier factor */
#define I2C_F_MULT_MASK (3 << I2C_F_MULT_SHIFT)
# define I2C_F_MULT_1 (0 << I2C_F_MULT_SHIFT)
# define I2C_F_MULT_2 (1 << I2C_F_MULT_SHIFT)
# define I2C_F_MULT_4 (2 << I2C_F_MULT_SHIFT)
/* From Table 51-54. I2C divider and hold values. Duplicate divider values differ in hold
* times. Refer to the Table 51-54. in the K64 Sub-Family Reference Manual.
*/
#define I2C_F_DIV20 ((uint8_t)0x00)
#define I2C_F_DIV22 ((uint8_t)0x01)
#define I2C_F_DIV24 ((uint8_t)0x02)
#define I2C_F_DIV26 ((uint8_t)0x03)
#define I2C_F_DIV28 ((uint8_t)0x04)
#define I2C_F_DIV30 ((uint8_t)0x05)
#define I2C_F_DIV34 ((uint8_t)0x06)
#define I2C_F_DIV36 ((uint8_t)0x0a)
#define I2C_F_DIV40_1 ((uint8_t)0x07)
#define I2C_F_DIV41 ((uint8_t)0x08)
#define I2C_F_DIV32 ((uint8_t)0x09)
#define I2C_F_DIV36 ((uint8_t)0x0a)
#define I2C_F_DIV40_2 ((uint8_t)0x0b)
#define I2C_F_DIV44 ((uint8_t)0x0c)
#define I2C_F_DIV48_1 ((uint8_t)0x0d)
#define I2C_F_DIV56_1 ((uint8_t)0x0e)
#define I2C_F_DIV68 ((uint8_t)0x0f)
#define I2C_F_DIV48_2 ((uint8_t)0x10)
#define I2C_F_DIV56_2 ((uint8_t)0x11)
#define I2C_F_DIV64 ((uint8_t)0x12)
#define I2C_F_DIV72 ((uint8_t)0x13)
#define I2C_F_DIV80_1 ((uint8_t)0x14)
#define I2C_F_DIV88 ((uint8_t)0x15)
#define I2C_F_DIV104 ((uint8_t)0x16)
#define I2C_F_DIV128_1 ((uint8_t)0x17)
#define I2C_F_DIV80_2 ((uint8_t)0x18)
#define I2C_F_DIV96 ((uint8_t)0x19)
#define I2C_F_DIV112 ((uint8_t)0x1a)
#define I2C_F_DIV128_2 ((uint8_t)0x1b)
#define I2C_F_DIV144 ((uint8_t)0x1c)
#define I2C_F_DIV160_1 ((uint8_t)0x1d)
#define I2C_F_DIV192_1 ((uint8_t)0x1e)
#define I2C_F_DIV240 ((uint8_t)0x1f)
#define I2C_F_DIV160_2 ((uint8_t)0x20)
#define I2C_F_DIV192_2 ((uint8_t)0x1e)
#define I2C_F_DIV224 ((uint8_t)0x22)
#define I2C_F_DIV256 ((uint8_t)0x23)
#define I2C_F_DIV288 ((uint8_t)0x24)
#define I2C_F_DIV320_1 ((uint8_t)0x25)
#define I2C_F_DIV384_1 ((uint8_t)0x26)
#define I2C_F_DIV480 ((uint8_t)0x27)
#define I2C_F_DIV320_2 ((uint8_t)0x28)
#define I2C_F_DIV384_2 ((uint8_t)0x29)
#define I2C_F_DIV448 ((uint8_t)0x2a)
#define I2C_F_DIV512 ((uint8_t)0x2b)
#define I2C_F_DIV576 ((uint8_t)0x2c)
#define I2C_F_DIV640_1 ((uint8_t)0x2d)
#define I2C_F_DIV768_1 ((uint8_t)0x2e)
#define I2C_F_DIV960 ((uint8_t)0x2f)
#define I2C_F_DIV640_2 ((uint8_t)0x30)
#define I2C_F_DIV768_3 ((uint8_t)0x31)
#define I2C_F_DIV896 ((uint8_t)0x32)
#define I2C_F_DIV1024 ((uint8_t)0x33)
#define I2C_F_DIV1152 ((uint8_t)0x34)
#define I2C_F_DIV1280_1 ((uint8_t)0x35)
#define I2C_F_DIV1536_1 ((uint8_t)0x36)
#define I2C_F_DIV1920 ((uint8_t)0x37)
#define I2C_F_DIV1280_2 ((uint8_t)0x38)
#define I2C_F_DIV1536_2 ((uint8_t)0x39)
#define I2C_F_DIV1792 ((uint8_t)0x3a)
#define I2C_F_DIV2048 ((uint8_t)0x3b)
#define I2C_F_DIV2304 ((uint8_t)0x3c)
#define I2C_F_DIV2560 ((uint8_t)0x3d)
#define I2C_F_DIV3072 ((uint8_t)0x3e)
#define I2C_F_DIV3840 ((uint8_t)0x3f)
/* I2C Control Register 1 (8-bit) */
#define I2C_C1_DMAEN (1 << 0) /* Bit 0: DMA enable */
@ -149,6 +231,7 @@
#define I2C_C2_AD_SHIFT (0) /* Bits 0-2: Slave address */
#define I2C_C2_AD_MASK (7 << I2C_C2_AD_SHIFT)
# define I2C_C2_AD(n) ((uint8_t)(n) << I2C_C2_AD_SHIFT)
#define I2C_C2_RMEN (1 << 3) /* Bit 3: Range address matching enable */
#define I2C_C2_SBRC (1 << 4) /* Bit 4: Slave baud rate control */
#define I2C_C2_HDRS (1 << 5) /* Bit 5: High drive select */
@ -156,9 +239,23 @@
#define I2C_C2_GCAEN (1 << 7) /* Bit 7: General call address enable */
/* I2C Programmable Input Glitch Filter register (8-bit) */
#if defined(KINETIS_K20) || defined(KINETIS_K40) || defined(KINETIS_K60)
# define I2C_FLT_SHIFT (0) /* Bits 0-4: I2C programmable filter factor */
# define I2C_FLT_MASK (31 << I2C_FLT_SHIFT)
# define I2C_FLT(n) ((uint8_t)(n) << I2C_FLT_SHIFT)
/* Bits 5-7: Reserved */
#define I2C_FLT_SHIFT (0) /* Bits 0-4: I2C programmable filter factor */
#define I2C_FLT_MASK (31 << I2C_FLT_SHIFT)
#endif
#ifdef KINETIS_K64
# define I2C_FLT_SHIFT (0) /* Bits 0-3: I2C programmable filter factor */
# define I2C_FLT_MASK (15 << I2C_FLT_SHIFT)
# define I2C_FLT(n) ((uint8_t)(n) << I2C_FLT_SHIFT)
# define I2C_FLT_STARTF (1 << 4) /* I2C bus start detect flag */
# define I2C_FLT_SSIE (1 << 5) /* I2C bus stop or start interrupt enable */
# define I2C_FLT_STOPF (1 << 6) /* I2C bus stop detect flag */
# define I2C_FLT_SHEN (1 << 7) /* Stop hold enable */
#endif
/* I2C Range Address register (8-bit) */
/* Bit 0: Reserved */

8
arch/arm/src/kinetis/chip/kinetis_rtc.h
View File

@ -59,7 +59,7 @@
#define KINETIS_RTC_CR_OFFSET 0x0010 /* RTC Control Register */
#define KINETIS_RTC_SR_OFFSET 0x0014 /* RTC Status Register */
#define KINETIS_RTC_LR_OFFSET 0x0018 /* RTC Lock Register */
#if defined(KINETIS_K40) || defined(KINETIS_K64)
#if defined(KINETIS_K20) || defined(KINETIS_K40) || defined(KINETIS_K64)
# define KINETIS_RTC_IER_OFFSET 0x001c /* RTC Interrupt Enable Register (K40) */
#endif
#ifdef KINETIS_K60
@ -77,7 +77,7 @@
#define KINETIS_RTC_CR (KINETIS_RTC_BASE+KINETIS_RTC_CR_OFFSET)
#define KINETIS_RTC_SR (KINETIS_RTC_BASE+KINETIS_RTC_SR_OFFSET)
#define KINETIS_RTC_LR (KINETIS_RTC_BASE+KINETIS_RTC_LR_OFFSET)
#if defined(KINETIS_K40) || defined(KINETIS_K64)
#if defined(KINETIS_K20) || defined(KINETIS_K40) || defined(KINETIS_K64)
# define KINETIS_RTC_IER (KINETIS_RTC_BASE+KINETIS_RTC_IER_OFFSET)
#endif
#ifdef KINETIS_K60
@ -135,13 +135,13 @@
#define RTC_LR_TCL (1 << 3) /* Bit 3: Time Compensation Lock */
#define RTC_LR_CRL (1 << 4) /* Bit 4: Control Register Lock */
#define RTC_LR_SRL (1 << 5) /* Bit 5: Status Register Lock */
#ifdef KINETIS_K40
#if defined(KINETIS_K20) || defined(KINETIS_K40)
# define RTC_LR_LRL (1 << 6) /* Bit 6: Lock Register Lock (K40) */
#endif
/* Bits 7-31: Reserved */
/* RTC Interrupt Enable Register (32-bits, K40) */
#if defined(KINETIS_K40) || defined(KINETIS_K64)
#if defined(KINETIS_K20) || defined(KINETIS_K40) || defined(KINETIS_K64)
# define RTC_IER_TIIE (1 << 0) /* Bit 0: Time Invalid Interrupt Enable */
# define RTC_IER_TOIE (1 << 1) /* Bit 1: Time Overflow Interrupt Enable */
# define RTC_IER_TAIE (1 << 2) /* Bit 2: Time Alarm Interrupt Enable */

113
arch/arm/src/kinetis/kinetis_alarm.h Normal file
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@ -0,0 +1,113 @@
/****************************************************************************
* arch/arm/src/kinetis/kinetis_alarm.h
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Matias v01d <phreakuencies@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_ALARM_H
#define __ARCH_ARM_SRC_KINETIS_ALARM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#ifdef CONFIG_RTC_ALARM
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/* The form of an alarm callback */
typedef CODE void (*alarmcb_t)(void);
/****************************************************************************
* Public Functions
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Name: kinetis_rtc_setalarm
*
* Description:
* Set up an alarm.
*
* Input Parameters:
* tp - the time to set the alarm
* callback - the function to call when the alarm expires.
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
struct timespec;
int kinetis_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback);
/****************************************************************************
* Name: kinetis_rtc_cancelalarm
*
* Description:
* Cancel a pending alarm alarm
*
* Input Parameters:
* none
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
int kinetis_rtc_cancelalarm(void);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_RTC_ALARM */
#endif /* __ARCH_ARM_SRC_KINETIS_ALARM_H */

1151
arch/arm/src/kinetis/kinetis_i2c.c Normal file
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File diff suppressed because it is too large Load Diff

87
arch/arm/src/kinetis/kinetis_i2c.h Normal file
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@ -0,0 +1,87 @@
/****************************************************************************
* arch/arm/src/kinetis/kinetis_i2c.h
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Matias v01d <phreakuencies@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_I2C_H
#define __ARCH_ARM_SRC_KINETIS_KINETIS_I2C_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/i2c/i2c_master.h>
#include "chip/kinetis_i2c.h"
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: kinetis_i2cbus_initialize
*
* Description:
* Initialize the selected I2C port. And return a unique instance of struct
* struct i2c_master_s. This function may be called to obtain multiple
* instances of the interface, each of which may be set up with a
* different frequency and slave address.
*
* Input Parameter:
* Port number (for hardware that has multiple I2C interfaces)
*
* Returned Value:
* Valid I2C device structure reference on succcess; a NULL on failure
*
****************************************************************************/
FAR struct i2c_master_s *kinetis_i2cbus_initialize(int port);
/****************************************************************************
* Name: kinetis_i2cbus_uninitialize
*
* Description:
* De-initialize the selected I2C port, and power down the device.
*
* Input Parameter:
* Device structure as returned by the lpc43_i2cbus_initialize()
*
* Returned Value:
* OK on success, ERROR when internal reference count mismatch or dev
* points to invalid hardware device.
*
****************************************************************************/
int kinetis_i2cbus_uninitialize(FAR struct i2c_master_s *dev);
#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_I2C_H */

2
arch/arm/src/kinetis/kinetis_pwm.c
View File

@ -58,7 +58,7 @@
#include "chip.h"
#include "kinetis.h"
#include "chip/kinetis_pwm.h"
#include "kinetis_pwm.h"
#include "chip/kinetis_gpio.h"
#include "chip/kinetis_ftm.h"
#include "chip/kinetis_sim.h"

373
arch/arm/src/kinetis/kinetis_rtc.c Normal file
View File

@ -0,0 +1,373 @@
/****************************************************************************
* arch/arm/src/kinetis/kinetis_rtc.c
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Matias v01d <phreakuencies@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include <nuttx/timers/rtc.h>
#include <arch/board/board.h>
#include <stdlib.h>
#include <stdint.h>
#include <stdbool.h>
#include <stdio.h>
#include <errno.h>
#include "up_arch.h"
#include "kinetis_config.h"
#include "chip.h"
#include "chip/kinetis_rtc.h"
#include "chip/kinetis_sim.h"
#include "kinetis.h"
#include "kinetis_alarm.h"
#if defined(CONFIG_RTC)
/****************************************************************************
* Private Data
****************************************************************************/
#ifdef CONFIG_RTC_ALARM
static alarmcb_t g_alarmcb;
#endif
/****************************************************************************
* Public Data
****************************************************************************/
volatile bool g_rtc_enabled = false;
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: kinetis_rtc_interrupt
*
* Description:
* RTC interrupt service routine
*
* Input Parameters:
* irq - The IRQ number that generated the interrupt
* context - Architecture specific register save information.
*
* Returned Value:
* Zero (OK) on success; A negated errno value on failure.
*
****************************************************************************/
#if defined(CONFIG_RTC_ALARM)
static int kinetis_rtc_interrupt(int irq, void *context)
{
if (g_alarmcb != NULL)
{
/* Alarm callback */
g_alarmcb();
g_alarmcb = NULL;
}
/* Clear pending flags, disable alarm */
putreg32(0, KINETIS_RTC_TAR); /* unset alarm (resets flags) */
putreg32(0, KINETIS_RTC_IER); /* disable alarm interrupt */
return 0;
}
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_rtc_initialize
*
* Description:
* Initialize the hardware RTC per the selected configuration. This
* function is called once during the OS initialization sequence
*
* Input Parameters:
* None
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
int up_rtc_initialize(void)
{
int regval;
/* Enable RTC module */
regval = getreg32(KINETIS_SIM_SCGC6);
regval |= SIM_SCGC6_RTC;
putreg32(regval, KINETIS_SIM_SCGC6);
/* Disable counters (just in case) */
putreg32(0, KINETIS_RTC_SR);
/* Enable oscilator */
/* capacitance values from teensyduino */
putreg32(RTC_CR_SC16P | RTC_CR_SC4P | RTC_CR_OSCE, KINETIS_RTC_CR);
/* TODO: delay some time (1024 cycles? would be 30ms) */
/* Disable interrupts */
putreg32(0, KINETIS_RTC_IER);
/* Reset flags requires writing the seconds register, the following line
* avoids altering any stored time value.
*/
putreg32(getreg32(KINETIS_RTC_TSR), KINETIS_RTC_TSR);
#if defined(CONFIG_RTC_ALARM)
/* Enable alarm interrupts. REVISIT: This will not work. up_rtc_initialize()
* is called very early in initialization BEFORE the interrupt system will be
* enabled. All interrupts will disabled later when the interrupt system is
* disabled. This must be done later when the alarm is first set.
*/
irq_attach(KINETIS_IRQ_RTC, kinetis_rtc_interrupt);
up_enable_irq(KINETIS_IRQ_RTC);
#endif
/* Enable counters */
putreg32(RTC_SR_TCE, KINETIS_RTC_SR);
/* Mark RTC enabled */
g_rtc_enabled = true;
return OK;
}
/****************************************************************************
* Name: up_rtc_time
*
* Description:
* Get the current time in seconds. This is similar to the standard
* time() function. This interface is only required if the low-resolution
* RTC/counter hardware implementation selected. It is only used by the
* RTOS during initialization to set up the system time when CONFIG_RTC is
* set but neither CONFIG_RTC_HIRES nor CONFIG_RTC_DATETIME are set.
*
* Input Parameters:
* None
*
* Returned Value:
* The current time in seconds
*
****************************************************************************/
#ifndef CONFIG_RTC_HIRES
time_t up_rtc_time(void)
{
return getreg32(KINETIS_RTC_TSR);
}
#endif
/****************************************************************************
* Name: up_rtc_gettime
*
* Description:
* Get the current time from the high resolution RTC clock/counter. This
* interface is only supported by the high-resolution RTC/counter hardware
* implementation. It is used to replace the system timer.
*
* Input Parameters:
* tp - The location to return the high resolution time value.
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
#ifdef CONFIG_RTC_HIRES
int up_rtc_gettime(FAR struct timespec *tp)
{
irqstate_t flags;
uint32_t seconds, prescaler, prescaler2;
/* Get prescaler and seconds register. this is in a loop which ensures that
* registers will be re-read if during the reads the prescaler has
* wrapped-around.
*/
flags = enter_critical_section();
do
{
prescaler = getreg32(KINETIS_RTC_TPR);
seconds = getreg32(KINETIS_RTC_TSR);
prescaler2 = getreg32(KINETIS_RTC_TPR);
}
while (prescaler > prescaler2);
leave_critical_section(flags);
/* Build seconds + nanoseconds from seconds and prescaler register */
tp->tv_sec = seconds;
tp->tv_nsec = prescaler * (1000000000 / CONFIG_RTC_FREQUENCY);
return OK;
}
#endif
/****************************************************************************
* Name: up_rtc_settime
*
* Description:
* Set the RTC to the provided time. All RTC implementations must be able
* to set their time based on a standard timespec.
*
* Input Parameters:
* tp - the time to use
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
int up_rtc_settime(FAR const struct timespec *tp)
{
irqstate_t flags;
uint32_t seconds, prescaler;
seconds = tp->tv_sec;
prescaler = tp->tv_nsec * (CONFIG_RTC_FREQUENCY / 1000000000);
flags = enter_critical_section();
putreg32(0, KINETIS_RTC_SR); /* Disable counter */
putreg32(prescaler, KINETIS_RTC_TPR); /* Always write prescaler first */
putreg32(seconds, KINETIS_RTC_TSR);
putreg32(RTC_SR_TCE, KINETIS_RTC_SR); /* Re-enable counter */
leave_critical_section(flags);
return OK;
}
/****************************************************************************
* Name: kinetis_rtc_setalarm
*
* Description:
* Set up an alarm.
*
* Input Parameters:
* tp - the time to set the alarm
* callback - the function to call when the alarm expires.
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
#ifdef CONFIG_RTC_ALARM
int kinetis_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback)
{
/* Is there already something waiting on the ALARM? */
if (g_alarmcb == NULL)
{
/* No.. Save the callback function pointer */
g_alarmcb = callback;
/* Enable and set RTC alarm */
putreg32(tp->tv_sec, KINETIS_RTC_TAR); /* Set alarm (also resets
* flags) */
putreg32(RTC_IER_TAIE, KINETIS_RTC_IER); /* Enable alarm interrupt */
return OK;
}
else
{
return -EBUSY;
}
}
#endif
/****************************************************************************
* Name: kinetis_rtc_cancelalarm
*
* Description:
* Cancel a pending alarm alarm
*
* Input Parameters:
* none
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
#ifdef CONFIG_RTC_ALARM
int kinetis_rtc_cancelalarm(void)
{
if (g_alarmcb != NULL)
{
/* Cancel the global callback function */
g_alarmcb = NULL;
/* Unset the alarm */
putreg32(0, KINETIS_RTC_IER); /* disable alarm interrupt */
return OK;
}
else
{
return -ENODATA;
}
}
#endif
#endif /* KINETIS_RTC */

8
arch/arm/src/kl/kl_pwm.h
View File

@ -90,13 +90,13 @@
# elif CONFIG_KL_TPM0_CHANNEL == 1
# define PWM_TPM0_PINCFG GPIO_TPM0_CH1OUT
# elif CONFIG_KL_TPM0_CHANNEL == 2
# define PWM_TPM0_PINCFG GPIO_TPM1_CH2OUT
# define PWM_TPM0_PINCFG GPIO_TPM0_CH2OUT
# elif CONFIG_KL_TPM0_CHANNEL == 3
# define PWM_TPM0_PINCFG GPIO_TPM1_CH3OUT
# define PWM_TPM0_PINCFG GPIO_TPM0_CH3OUT
# elif CONFIG_KL_TPM0_CHANNEL == 4
# define PWM_TPM0_PINCFG GPIO_TPM1_CH4OUT
# define PWM_TPM0_PINCFG GPIO_TPM0_CH4OUT
# elif CONFIG_KL_TPM0_CHANNEL == 5
# define PWM_TPM0_PINCFG GPIO_TPM1_CH5OUT
# define PWM_TPM0_PINCFG GPIO_TPM0_CH5OUT
# else
# error "Unsupported value of CONFIG_KL_TPM1_CHANNEL"
# endif

6
arch/arm/src/lpc214x/chip.h
View File

@ -33,8 +33,8 @@
*
****************************************************************************************************/
#ifndef __LPC214X_CHIP_H
#define __LPC214X_CHIP_H
#ifndef __ARCH_ARM_SRC_LPC214X_CHIP_H
#define __ARCH_ARM_SRC_LPC214X_CHIP_H
/****************************************************************************************************
* Included Files
@ -346,4 +346,4 @@
* Public Function Prototypes
****************************************************************************************************/
#endif /* __LPC214X_CHIP_H */
#endif /* __ARCH_ARM_SRC_LPC214X_CHIP_H */

6
arch/arm/src/lpc214x/lpc214x_apb.h
View File

@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef _ARCH_ARM_SRC_LPC214X_APB_H
#define _ARCH_ARM_SRC_LPC214X_APB_H
#ifndef __ARCH_ARM_SRC_LPC214X_LPC214X_APB_H
#define __ARCH_ARM_SRC_LPC214X_LPC214X_APB_H
/************************************************************************************
* Included Files
@ -69,4 +69,4 @@
* Public Function Prototypes
************************************************************************************/
#endif /* _ARCH_ARM_SRC_LPC214X_APB_H */
#endif /* __ARCH_ARM_SRC_LPC214X_LPC214X_APB_H */

6
arch/arm/src/lpc214x/lpc214x_i2c.h
View File

@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef _ARCH_ARM_SRC_LPC214X_I2C_H
#define _ARCH_ARM_SRC_LPC214X_I2C_H
#ifndef __ARCH_ARM_SRC_LPC214X_LPC214X_I2C_H
#define __ARCH_ARM_SRC_LPC214X_LPC214X_I2C_H
/************************************************************************************
* Included Files
@ -138,4 +138,4 @@
* Public Function Prototypes
************************************************************************************/
#endif /* _ARCH_ARM_SRC_LPC214X_I2C_H */
#endif /* __ARCH_ARM_SRC_LPC214X_LPC214X_I2C_H */

6
arch/arm/src/lpc214x/lpc214x_pinsel.h
View File

@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef _ARCH_ARM_SRC_LPC214X_PINSEL_H
#define _ARCH_ARM_SRC_LPC214X_PINSEL_H
#ifndef __ARCH_ARM_SRC_LPC214X_LPC214X_PINSEL_H
#define __ARCH_ARM_SRC_LPC214X_LPC214X_PINSEL_H
/************************************************************************************
* Included Files
@ -256,4 +256,4 @@
* Public Function Prototypes
************************************************************************************/
#endif /* _ARCH_ARM_SRC_LPC214X_PINSEL_H */
#endif /* __ARCH_ARM_SRC_LPC214X_LPC214X_PINSEL_H */

6
arch/arm/src/lpc214x/lpc214x_pll.h
View File

@ -33,8 +33,8 @@
*
****************************************************************************************************/
#ifndef _ARCH_ARM_SRC_LPC214X_PLL_H
#define _ARCH_ARM_SRC_LPC214X_PLL_H
#ifndef __ARCH_ARM_SRC_LPC214X_LPC214X_PLL_H
#define __ARCH_ARM_SRC_LPC214X_LPC214X_PLL_H
/****************************************************************************************************
* Included Files
@ -102,4 +102,4 @@
* Public Function Prototypes
****************************************************************************************************/
#endif /* _ARCH_ARM_SRC_LPC214X_PLL_H */
#endif /* __ARCH_ARM_SRC_LPC214X_LPC214X_PLL_H */

6
arch/arm/src/lpc214x/lpc214x_power.h
View File

@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef _ARCH_ARM_SRC_LPC214X_POWER_H
#define _ARCH_ARM_SRC_LPC214X_POWER_H
#ifndef __ARCH_ARM_SRC_LPC214X_LPC214X_POWER_H
#define __ARCH_ARM_SRC_LPC214X_LPC214X_POWER_H
/************************************************************************************
* Included Files
@ -87,4 +87,4 @@
* Public Function Prototypes
************************************************************************************/
#endif /* _ARCH_ARM_SRC_LPC214X_POWER_H */
#endif /* __ARCH_ARM_SRC_LPC214X_LPC214X_POWER_H */

6
arch/arm/src/lpc214x/lpc214x_spi.h
View File

@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef _ARCH_ARM_SRC_LPC214X_SPI_H
#define _ARCH_ARM_SRC_LPC214X_SPI_H
#ifndef __ARCH_ARM_SRC_LPC214X_LPC214X_SPI_H
#define __ARCH_ARM_SRC_LPC214X_LPC214X_SPI_H
/************************************************************************************
* Included Files
@ -181,4 +181,4 @@ struct spi_dev_s; /* Forward reference */
FAR struct spi_dev_s *lpc214x_spibus_initialize(int port);
#endif /* _ARCH_ARM_SRC_LPC214X_SPI_H */
#endif /* __ARCH_ARM_SRC_LPC214X_LPC214X_SPI_H */

6
arch/arm/src/lpc214x/lpc214x_timer.h
View File

@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __LPC214X_TIMER_H
#define __LPC214X_TIMER_H
#ifndef __ARCH_ARM_SRC_LPC214X_LPC214X_TIMER_H
#define __ARCH_ARM_SRC_LPC214X_LPC214X_TIMER_H
/************************************************************************************
* Included Files
@ -149,4 +149,4 @@
* Public Function Prototypes
************************************************************************************/
#endif /* __LPC214X_TIMER_H */
#endif /* __ARCH_ARM_SRC_LPC214X_LPC214X_TIMER_H */

6
arch/arm/src/lpc214x/lpc214x_uart.h
View File

@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __LPC214X_UART_H
#define __LPC214X_UART_H
#ifndef __ARCH_ARM_SRC_LPC214X_LPC214X_UART_H
#define __ARCH_ARM_SRC_LPC214X_LPC214X_UART_H
/************************************************************************************
* Included Files
@ -139,4 +139,4 @@
* Public Function Prototypes
************************************************************************************/
#endif /* __LPC214X_UART_H */
#endif /* __ARCH_ARM_SRC_LPC214X_LPC214X_UART_H */

6
arch/arm/src/lpc214x/lpc214x_vic.h
View File

@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __LPC214X_VIC_H
#define __LPC214X_VIC_H
#ifndef __ARCH_ARM_SRC_LPC214X_LPC214X_VIC_H
#define __ARCH_ARM_SRC_LPC214X_LPC214X_VIC_H
/************************************************************************************
* Included Files
@ -67,4 +67,4 @@
* Public Function Prototypes
************************************************************************************/
#endif /* __LPC214X_VIC_H */
#endif /* __ARCH_ARM_SRC_LPC214X_LPC214X_VIC_H */

6
arch/arm/src/lpc2378/chip.h
View File

@ -38,8 +38,8 @@
*
****************************************************************************************************/
#ifndef _ARCH_ARM_SRC_LPC2378_CHIP_H
#define _ARCH_ARM_SRC_LPC2378_CHIP_H
#ifndef __ARCH_ARM_SRC_LPC2378_CHIP_H
#define __ARCH_ARM_SRC_LPC2378_CHIP_H
/****************************************************************************************************
* Included Files
@ -1003,4 +1003,4 @@ are for LPC24xx only. */
* Public Function Prototypes
****************************************************************************************************/
#endif /* _ARCH_ARM_SRC_LPC2378_CHIP_H */
#endif /* __ARCH_ARM_SRC_LPC2378_CHIP_H */

6
arch/arm/src/lpc2378/lpc2378.h
View File

@ -38,8 +38,8 @@
*
****************************************************************************************************/
#ifndef _ARCH_ARM_SRC_LPC2378_INTERNAL_H
#define _ARCH_ARM_SRC_LPC2378_INTERNAL_H
#ifndef __ARCH_ARM_SRC_LPC2378_LPC23XX_H
#define __ARCH_ARM_SRC_LPC2378_LPC23XX_H
/****************************************************************************************************
* Included Files
@ -67,4 +67,4 @@ void lpc2378_statledon(void);
#endif
#endif /* _ARCH_ARM_SRC_LPC2378_INTERNAL_H */
#endif /* __ARCH_ARM_SRC_LPC2378_LPC23XX_H */

6
arch/arm/src/lpc2378/lpc23xx_gpio.h
View File

@ -38,8 +38,8 @@
*
************************************************************************************/
#ifndef _ARCH_ARM_SRC_LPC2378_LPC23XX_GPIO_H
#define _ARCH_ARM_SRC_LPC2378_LPC23XX_GPIO_H
#ifndef __ARCH_ARM_SRC_LPC2378_LPC23XX_GPIO_H
#define __ARCH_ARM_SRC_LPC2378_LPC23XX_GPIO_H
/************************************************************************************
* Included Files
@ -68,4 +68,4 @@
* Public Function Prototypes
************************************************************************************/
#endif /* _ARCH_ARM_SRC_LPC2378_LPC23XX_GPIO_H */
#endif /* __ARCH_ARM_SRC_LPC2378_LPC23XX_GPIO_H */

6
arch/arm/src/lpc2378/lpc23xx_pinsel.h
View File

@ -38,8 +38,8 @@
*
************************************************************************************/
#ifndef _ARCH_ARM_SRC_LPC23XX_PINSEL_H
#define _ARCH_ARM_SRC_LPC23XX_PINSEL_H
#ifndef __ARCH_ARM_SRC_LPC2378_LPC23XX_PINSEL_H
#define __ARCH_ARM_SRC_LPC2378_LPC23XX_PINSEL_H
/************************************************************************************
* Included Files
@ -789,4 +789,4 @@
* Public Function Prototypes
************************************************************************************/
#endif /* _ARCH_ARM_SRC_LPC23XX_PINSEL_H */
#endif /* __ARCH_ARM_SRC_LPC2378_LPC23XX_PINSEL_H */

7
arch/arm/src/lpc43xx/lpc43_adc.c
View File

@ -59,7 +59,6 @@
#include <assert.h>
#include <debug.h>
#include <arch/board/board.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <nuttx/analog/adc.h>
@ -80,6 +79,12 @@
#include "lpc43_pinconfig.h"
/* board.h should be included last because it depends on the previous
* inclusions and may need to modify other definitions.
*/
#include <arch/board/board.h>
#if defined(CONFIG_LPC43_ADC0) /* TODO ADC1 */
/****************************************************************************

8
arch/arm/src/lpc43xx/lpc43_serial.c
View File

@ -170,7 +170,7 @@ static struct up_dev_s g_uart0priv =
.bits = CONFIG_USART0_BITS,
.stopbits2 = CONFIG_USART0_2STOP,
#if defined(CONFIG_USART0_RS485MODE) && defined(CONFIG_USART0_RS485_DTRDIR)
.dtrdir = true;
.dtrdir = true,
#endif
};
@ -205,7 +205,7 @@ static struct up_dev_s g_uart1priv =
.bits = CONFIG_UART1_BITS,
.stopbits2 = CONFIG_UART1_2STOP,
#if defined(CONFIG_UART1_RS485MODE) && defined(CONFIG_UART1_RS485_DTRDIR)
.dtrdir = true;
.dtrdir = true,
#endif
};
@ -240,7 +240,7 @@ static struct up_dev_s g_uart2priv =
.bits = CONFIG_USART2_BITS,
.stopbits2 = CONFIG_USART2_2STOP,
#if defined(CONFIG_USART2_RS485MODE) && defined(CONFIG_USART2_RS485_DTRDIR)
.dtrdir = true;
.dtrdir = true,
#endif
};
@ -275,7 +275,7 @@ static struct up_dev_s g_uart3priv =
.bits = CONFIG_USART3_BITS,
.stopbits2 = CONFIG_USART3_2STOP,
#if defined(CONFIG_USART3_RS485MODE) && defined(CONFIG_USART3_RS485_DTRDIR)
.dtrdir = true;
.dtrdir = true,
#endif
};

1
arch/arm/src/sam34/Kconfig
View File

@ -1060,7 +1060,6 @@ config SAM34_TC5_TIOB
config SAM34_ONESHOT
bool "TC one-shot wrapper"
depends on SAM34_FREERUN
default n if !SCHED_TICKLESS
default y if SCHED_TICKLESS
---help---

2
arch/arm/src/sam34/Make.defs
View File

@ -199,7 +199,7 @@ ifeq ($(CONFIG_ARCH_CHIP_SAM4CM),y)
ifeq ($(CONFIG_SAM34_TC),y)
CHIP_CSRCS += sam4cm_tc.c
ifeq ($(CONFIG_SAM34_ONESHOT),y)
CHIP_CSRCS += sam4cm_oneshot.c
CHIP_CSRCS += sam4cm_oneshot.c sam4cm_oneshot_lowerhalf.c
endif
ifeq ($(CONFIG_SAM34_FREERUN),y)
CHIP_CSRCS += sam4cm_freerun.c

4
arch/arm/src/sam34/sam4cm_freerun.c
View File

@ -59,7 +59,7 @@
#include "sam4cm_freerun.h"
#ifdef CONFIG_SAM34_ONESHOT
#ifdef CONFIG_SAM34_FREERUN
/****************************************************************************
* Private Functions
@ -316,4 +316,4 @@ int sam_freerun_uninitialize(struct sam_freerun_s *freerun)
return OK;
}
#endif /* CONFIG_SAM34_ONESHOT */
#endif /* CONFIG_SAM34_FREERUN */

27
arch/arm/src/sam34/sam4cm_oneshot.c
View File

@ -111,7 +111,9 @@ static void sam_oneshot_handler(TC_HANDLE tch, void *arg, uint32_t sr)
oneshot->handler = NULL;
oneshot_arg = (void *)oneshot->arg;
oneshot->arg = NULL;
#ifdef CONFIG_SAM34_FREERUN
oneshot->start_count = 0;
#endif
oneshot_handler(oneshot_arg);
}
@ -212,7 +214,10 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
oneshot->running = false;
oneshot->handler = NULL;
oneshot->arg = NULL;
#ifdef CONFIG_SAM34_FREERUN
oneshot->start_count = 0;
#endif
return OK;
}
@ -251,8 +256,10 @@ int sam_oneshot_max_delay(struct sam_oneshot_s *oneshot, uint64_t *usec)
*
****************************************************************************/
int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freerun,
oneshot_handler_t handler, void *arg, const struct timespec *ts)
int sam_oneshot_start(struct sam_oneshot_s *oneshot,
struct sam_freerun_s *freerun,
oneshot_handler_t handler, void *arg,
const struct timespec *ts)
{
uint64_t usec;
uint64_t regval;
@ -309,6 +316,7 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
sam_tc_start(oneshot->tch);
#ifdef CONFIG_SAM34_FREERUN
/* The function sam_tc_start() starts the timer/counter by setting the
* bits TC_CCR_CLKEN and TC_CCR_SWTRG in the channel control register.
* The first one enables the timer/counter the latter performs an
@ -327,7 +335,11 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
* vanishes at least if compiled with no optimisation.
*/
oneshot->start_count = sam_tc_getcounter(freerun->tch);
if (freerun != NULL)
{
oneshot->start_count = sam_tc_getcounter(freerun->tch);
}
#endif
/* Enable interrupts. We should get the callback when the interrupt
* occurs.
@ -363,8 +375,8 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
*
****************************************************************************/
int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freerun,
struct timespec *ts)
int sam_oneshot_cancel(struct sam_oneshot_s *oneshot,
struct sam_freerun_s *freerun, struct timespec *ts)
{
irqstate_t flags;
uint64_t usec;
@ -405,16 +417,19 @@ int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *free
count = sam_tc_getcounter(oneshot->tch);
rc = sam_tc_getregister(oneshot->tch, TC_REGC);
#ifdef CONFIG_SAM34_FREERUN
/* In the case the timer/counter was canceled very short after its start,
* the counter register can hold the wrong value (the value of the last
* run). To prevent this the counter value is set to zero if not at
* least on tick passed since the start of the timer/counter.
*/
if (count > 0 && sam_tc_getcounter(freerun->tch) == oneshot->start_count)
if (count > 0 && freerun != NULL &&
sam_tc_getcounter(freerun->tch) == oneshot->start_count)
{
count = 0;
}
#endif
/* Now we can disable the interrupt and stop the timer. */

29
arch/arm/src/sam34/sam4cm_oneshot.h
View File

@ -46,7 +46,6 @@
#include <time.h>
#include "sam4cm_tc.h"
#include "sam4cm_freerun.h"
#ifdef CONFIG_SAM34_ONESHOT
@ -83,11 +82,13 @@ struct sam_oneshot_s
volatile oneshot_handler_t handler; /* Oneshot expiration callback */
volatile void *arg; /* The argument that will accompany
* the callback */
#ifdef CONFIG_SAM34_FREERUN
volatile uint32_t start_count; /* Stores the value of the freerun counter,
* at each start of the onshot timer. Is neccesary
* to find out if the onshot counter was updated
* correctly at the time of the call to
* sam_oneshot_cancel or not. */
#endif
};
/****************************************************************************
@ -130,6 +131,14 @@ extern "C"
int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
uint16_t resolution);
/****************************************************************************
* Name: sam_oneshot_max_delay
*
* Description:
* Determine the maximum delay of the one-shot timer (in microseconds)
*
****************************************************************************/
int sam_oneshot_max_delay(struct sam_oneshot_s *oneshot, uint64_t *usec);
/****************************************************************************
@ -144,7 +153,8 @@ int sam_oneshot_max_delay(struct sam_oneshot_s *oneshot, uint64_t *usec);
* sam_oneshot_initialize();
* freerun Caller allocated instance of the freerun state structure. This
* structure must have been previously initialized via a call to
* sam_freerun_initialize();
* sam_freerun_initialize(). May be NULL if there is no matching
* free-running timer.
* handler The function to call when when the oneshot timer expires.
* arg An opaque argument that will accompany the callback.
* ts Provides the duration of the one shot timer.
@ -155,8 +165,11 @@ int sam_oneshot_max_delay(struct sam_oneshot_s *oneshot, uint64_t *usec);
*
****************************************************************************/
int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freerun,
oneshot_handler_t handler, void *arg, const struct timespec *ts);
struct sam_freerun_s;
int sam_oneshot_start(struct sam_oneshot_s *oneshot,
struct sam_freerun_s *freerun,
oneshot_handler_t handler, void *arg,
const struct timespec *ts);
/****************************************************************************
* Name: sam_oneshot_cancel
@ -173,7 +186,8 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
* sam_oneshot_initialize();
* freerun Caller allocated instance of the freerun state structure. This
* structure must have been previously initialized via a call to
* sam_freerun_initialize();
* sam_freerun_initialize(). May be NULL if there is no matching
* free-running timer.
* ts The location in which to return the time remaining on the
* oneshot timer. A time of zero is returned if the timer is
* not running.
@ -185,8 +199,9 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
*
****************************************************************************/
int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freerun,
struct timespec *ts);
struct sam_freerun_s;
int sam_oneshot_cancel(struct sam_oneshot_s *oneshot,
struct sam_freerun_s *freerun, struct timespec *ts);
#undef EXTERN
#ifdef __cplusplus

345
arch/arm/src/sam34/sam4cm_oneshot_lowerhalf.c Normal file
View File

@ -0,0 +1,345 @@
/****************************************************************************
* arch/arm/src/sam/sam_oneshot_lowerhalf.c
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <time.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/kmalloc.h>
#include <nuttx/timers/oneshot.h>
#include "sam_oneshot.h"
/****************************************************************************
* Private Types
****************************************************************************/
/* This structure describes the state of the oneshot timer lower-half driver */
struct sam_oneshot_lowerhalf_s
{
/* This is the part of the lower half driver that is visible to the upper-
* half client of the driver. This must be the first thing in this
* structure so that pointers to struct oneshot_lowerhalf_s are cast
* compatible to struct sam_oneshot_lowerhalf_s and vice versa.
*/
struct oneshot_lowerhalf_s lh; /* Common lower-half driver fields */
/* Private lower half data follows */
struct sam_oneshot_s oneshot; /* SAM-specific oneshot state */
oneshot_callback_t callback; /* internal handler that receives callback */
FAR void *arg; /* Argument that is passed to the handler */
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
static void sam_oneshot_handler(void *arg);
static int sam_max_delay(FAR struct oneshot_lowerhalf_s *lower,
FAR struct timespec *ts);
static int sam_start(FAR struct oneshot_lowerhalf_s *lower,
oneshot_callback_t callback, FAR void *arg,
FAR const struct timespec *ts);
static int sam_cancel(FAR struct oneshot_lowerhalf_s *lower,
FAR struct timespec *ts);
/****************************************************************************
* Private Data
****************************************************************************/
/* Lower half operations */
static const struct oneshot_operations_s g_oneshot_ops =
{
.max_delay = sam_max_delay,
.start = sam_start,
.cancel = sam_cancel,
};
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: sam_oneshot_handler
*
* Description:
* Timer expiration handler
*
* Input Parameters:
* arg - Should be the same argument provided when sam_oneshot_start()
* was called.
*
* Returned Value:
* None
*
****************************************************************************/
static void sam_oneshot_handler(void *arg)
{
FAR struct sam_oneshot_lowerhalf_s *priv =
(FAR struct sam_oneshot_lowerhalf_s *)arg;
oneshot_callback_t callback;
FAR void *cbarg;
DEBUGASSERT(priv != NULL);
/* Perhaps the callback was nullified in a race condition with
* sam_cancel?
*/
if (priv->callback)
{
/* Sample and nullify BEFORE executing callback (in case the callback
* restarts the oneshot).
*/
callback = priv->callback;
cbarg = priv->arg;
priv->callback = NULL;
priv->arg = NULL;
/* Then perform the callback */
callback(&priv->lh, cbarg);
}
}
/****************************************************************************
* Name: sam_max_delay
*
* Description:
* Determine the maximum delay of the one-shot timer (in microseconds)
*
* Input Parameters:
* lower An instance of the lower-half oneshot state structure. This
* structure must have been previously initialized via a call to
* oneshot_initialize();
* ts The location in which to return the maxumum delay.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on failure.
*
****************************************************************************/
static int sam_max_delay(FAR struct oneshot_lowerhalf_s *lower,
FAR struct timespec *ts)
{
FAR struct sam_oneshot_lowerhalf_s *priv =
(FAR struct sam_oneshot_lowerhalf_s *)lower;
uint64_t usecs;
int ret;
DEBUGASSERT(priv != NULL && ts != NULL);
ret = sam_oneshot_max_delay(&priv->oneshot, &usecs);
if (ret >= 0)
{
uint64_t sec = usecs / 1000000;
usecs -= 1000000 * sec;
ts->tv_sec = (time_t)sec;
ts->tv_nsec = (long)(usecs * 1000);
}
return ret;
}
/****************************************************************************
* Name: sam_start
*
* Description:
* Start the oneshot timer
*
* Input Parameters:
* lower An instance of the lower-half oneshot state structure. This
* structure must have been previously initialized via a call to
* oneshot_initialize();
* handler The function to call when when the oneshot timer expires.
* arg An opaque argument that will accompany the callback.
* ts Provides the duration of the one shot timer.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on failure.
*
****************************************************************************/
static int sam_start(FAR struct oneshot_lowerhalf_s *lower,
oneshot_callback_t callback, FAR void *arg,
FAR const struct timespec *ts)
{
FAR struct sam_oneshot_lowerhalf_s *priv =
(FAR struct sam_oneshot_lowerhalf_s *)lower;
irqstate_t flags;
int ret;
DEBUGASSERT(priv != NULL && callback != NULL && ts != NULL);
/* Save the callback information and start the timer */
flags = enter_critical_section();
priv->callback = callback;
priv->arg = arg;
ret = sam_oneshot_start(&priv->oneshot, NULL,
sam_oneshot_handler, priv, ts);
leave_critical_section(flags);
if (ret < 0)
{
tmrerr("ERROR: sam_oneshot_start failed: %d\n", flags);
}
return ret;
}
/****************************************************************************
* Name: sam_cancel
*
* Description:
* Cancel the oneshot timer and return the time remaining on the timer.
*
* NOTE: This function may execute at a high rate with no timer running (as
* when pre-emption is enabled and disabled).
*
* Input Parameters:
* lower Caller allocated instance of the oneshot state structure. This
* structure must have been previously initialized via a call to
* oneshot_initialize();
* ts The location in which to return the time remaining on the
* oneshot timer. A time of zero is returned if the timer is
* not running.
*
* Returned Value:
* Zero (OK) is returned on success. A call to up_timer_cancel() when
* the timer is not active should also return success; a negated errno
* value is returned on any failure.
*
****************************************************************************/
static int sam_cancel(FAR struct oneshot_lowerhalf_s *lower,
FAR struct timespec *ts)
{
FAR struct sam_oneshot_lowerhalf_s *priv =
(FAR struct sam_oneshot_lowerhalf_s *)lower;
irqstate_t flags;
int ret;
DEBUGASSERT(priv != NULL);
/* Cancel the timer */
flags = enter_critical_section();
ret = sam_oneshot_cancel(&priv->oneshot, NULL, ts);
priv->callback = NULL;
priv->arg = NULL;
leave_critical_section(flags);
if (ret < 0)
{
tmrerr("ERROR: sam_oneshot_cancel failed: %d\n", flags);
}
return ret;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: oneshot_initialize
*
* Description:
* Initialize the oneshot timer and return a oneshot lower half driver
* instance.
*
* Input Parameters:
* chan Timer counter channel to be used.
* resolution The required resolution of the timer in units of
* microseconds. NOTE that the range is restricted to the
* range of uint16_t (excluding zero).
*
* Returned Value:
* On success, a non-NULL instance of the oneshot lower-half driver is
* returned. NULL is return on any failure.
*
****************************************************************************/
FAR struct oneshot_lowerhalf_s *oneshot_initialize(int chan,
uint16_t resolution)
{
FAR struct sam_oneshot_lowerhalf_s *priv;
int ret;
/* Allocate an instance of the lower half driver */
priv = (FAR struct sam_oneshot_lowerhalf_s *)
kmm_zalloc(sizeof(struct sam_oneshot_lowerhalf_s));
if (priv == NULL)
{
tmrerr("ERROR: Failed to initialized state structure\n");
return NULL;
}
/* Initialize the lower-half driver structure */
priv->lh.ops = &g_oneshot_ops;
/* Initialize the contained SAM oneshot timer */
ret = sam_oneshot_initialize(&priv->oneshot, chan, resolution);
if (ret < 0)
{
tmrerr("ERROR: sam_oneshot_initialize failed: %d\n", ret);
kmm_free(priv);
return NULL;
}
return &priv->lh;
}

72
arch/arm/src/sam34/sam_gpio.c
View File

@ -54,6 +54,7 @@
#include "chip.h"
#include "sam_gpio.h"
#include "sam_periphclks.h"
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
@ -96,7 +97,7 @@ static inline uintptr_t sam_gpiobase(gpio_pinset_t cfgset)
* Name: sam_gpiopin
*
* Description:
* Returun the base address of the GPIO register set
* Return the base address of the GPIO register set
*
****************************************************************************/
@ -105,6 +106,67 @@ static inline int sam_gpiopin(gpio_pinset_t cfgset)
return 1 << ((cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT);
}
/****************************************************************************
* Name: sam_gpio_enableclk
*
* Description:
* Enable clocking on the PIO port. Port clocking is required in the
* following cases:
*
* - In order to read values in input pins from the port
* - If the port supports interrupting pins
* - If glitch filtering is enabled
* - If necessary to read the input value on an open drain output (this
* may be done in TWI logic to detect hangs on the I2C bus).
* - If necessary to read the input value on peripheral pins.
*
****************************************************************************/
static inline int sam_gpio_enableclk(gpio_pinset_t cfgset)
{
/* Enable the peripheral clock for the GPIO's port controller. */
switch (cfgset & GPIO_PORT_MASK)
{
case GPIO_PORT_PIOA:
sam_pioa_enableclk();
break;
case GPIO_PORT_PIOB:
sam_piob_enableclk();
break;
#ifdef GPIO_PORT_PIOC
case GPIO_PORT_PIOC:
sam_pioc_enableclk();
break;
#endif
#ifdef GPIO_PORT_PIOD
case GPIO_PORT_PIOD:
sam_piod_enableclk();
break;
#endif
#ifdef GPIO_PORT_PIOE
case GPIO_PORT_PIOE:
sam_pioe_enableclk();
break;
#endif
#ifdef GPIO_PORT_PIOF
case GPIO_PORT_PIOF:
sam_piof_enableclk();
break;
#endif
default:
return -EINVAL;
}
return OK;
}
/****************************************************************************
* Name: sam_configinput
*
@ -171,6 +233,7 @@ static inline int sam_configinput(uintptr_t base, uint32_t pin,
{
regval &= ~pin;
}
putreg32(regval, base + SAM_PIO_SCHMITT_OFFSET);
#endif
@ -184,7 +247,12 @@ static inline int sam_configinput(uintptr_t base, uint32_t pin,
* another, new API... perhaps sam_configfilter()
*/
return OK;
/* Enable the peripheral clock for the GPIO's port controller.
* A GPIO input value is only sampled if the peripheral clock for its
* controller is enabled.
*/
return sam_gpio_enableclk(cfgset);
}
/****************************************************************************

4
arch/arm/src/sam34/sam_wdt.c
View File

@ -554,7 +554,7 @@ static xcpt_t sam34_capture(FAR struct watchdog_lowerhalf_s *lower,
regval |= WWDG_CFR_EWI;
sam34_putreg(regval, SAM_WDT_CFR);
up_enable_irq(STM32_IRQ_WWDG);
up_enable_irq(SAM_IRQ_WWDG);
}
else
{
@ -563,7 +563,7 @@ static xcpt_t sam34_capture(FAR struct watchdog_lowerhalf_s *lower,
regval &= ~WWDG_CFR_EWI;
sam34_putreg(regval, SAM_WDT_CFR);
up_disable_irq(STM32_IRQ_WWDG);
up_disable_irq(SAM_IRQ_WWDG);
}
leave_critical_section(flags);

2
arch/arm/src/sam34/sam_wdt.h
View File

@ -95,4 +95,4 @@ void sam_wdtinitialize(FAR const char *devpath);
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_WATCHDOG */
#endif /* __ARCH_ARM_SRC_STM32_STM32_WDG_H */
#endif /* __ARCH_ARM_SRC_SAM34_WDT_H */

1
arch/arm/src/sama5/Kconfig
View File

@ -3866,7 +3866,6 @@ endif # SAMA5_TC2
config SAMA5_ONESHOT
bool "TC one-shot wrapper"
depends on SAMA5_FREERUN
default n if !SCHED_TICKLESS
default y if SCHED_TICKLESS
---help---

4
arch/arm/src/sama5/Make.defs
View File

@ -1,7 +1,7 @@
############################################################################
# arch/arm/sama5/Make.defs
#
# Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
# Copyright (C) 2013-2014, 2016 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <gnutt@nuttx.org>
#
# Redistribution and use in source and binary forms, with or without
@ -292,7 +292,7 @@ endif
ifeq ($(CONFIG_SAMA5_HAVE_TC),y)
CHIP_CSRCS += sam_tc.c
ifeq ($(CONFIG_SAMA5_ONESHOT),y)
CHIP_CSRCS += sam_oneshot.c
CHIP_CSRCS += sam_oneshot.c sam_oneshot_lowerhalf.c
endif
ifeq ($(CONFIG_SAMA5_FREERUN),y)
CHIP_CSRCS += sam_freerun.c

21
arch/arm/src/sama5/sam_freerun.c
View File

@ -60,27 +60,12 @@
#include "sam_freerun.h"
#ifdef CONFIG_SAMA5_ONESHOT
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
#ifdef CONFIG_SAMA5_FREERUN
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: sam_freerun_handler
*
@ -333,4 +318,4 @@ int sam_freerun_uninitialize(struct sam_freerun_s *freerun)
return OK;
}
#endif /* CONFIG_SAMA5_ONESHOT */
#endif /* CONFIG_SAMA5_FREERUN */

69
arch/arm/src/sama5/sam_oneshot.c
View File

@ -63,22 +63,6 @@
#ifdef CONFIG_SAMA5_ONESHOT
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
@ -128,7 +112,9 @@ static void sam_oneshot_handler(TC_HANDLE tch, void *arg, uint32_t sr)
oneshot->handler = NULL;
oneshot_arg = (void *)oneshot->arg;
oneshot->arg = NULL;
#ifdef CONFIG_SAMA5_FREERUN
oneshot->start_count = 0;
#endif
oneshot_handler(oneshot_arg);
}
@ -229,7 +215,36 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
oneshot->running = false;
oneshot->handler = NULL;
oneshot->arg = NULL;
#ifdef CONFIG_SAMA5_FREERUN
oneshot->start_count = 0;
#endif
return OK;
}
/****************************************************************************
* Name: sam_oneshot_max_delay
*
* Description:
* Return the maximum delay supported by the one shot timer (in
* microseconds).
*
* Input Parameters:
* oneshot Caller allocated instance of the oneshot state structure. This
* structure must have been previously initialized via a call to
* sam_oneshot_initialize();
* usec The location in which to return the maximum delay.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on failure.
*
****************************************************************************/
int sam_oneshot_max_delay(struct sam_oneshot_s *oneshot, uint64_t *usec)
{
DEBUGASSERT(oneshot != NULL && usec != NULL);
*usec = (0xffffull * USEC_PER_SEC) / (uint64_t)sam_tc_divfreq(oneshot->tch);
return OK;
}
@ -253,8 +268,10 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
*
****************************************************************************/
int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freerun,
oneshot_handler_t handler, void *arg, const struct timespec *ts)
int sam_oneshot_start(struct sam_oneshot_s *oneshot,
struct sam_freerun_s *freerun,
oneshot_handler_t handler, void *arg,
const struct timespec *ts)
{
uint64_t usec;
uint64_t regval;
@ -311,6 +328,7 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
sam_tc_start(oneshot->tch);
#ifdef CONFIG_SAMA5_FREERUN
/* The function sam_tc_start() starts the timer/counter by setting the
* bits TC_CCR_CLKEN and TC_CCR_SWTRG in the channel control register.
* The first one enables the timer/counter the latter performs an
@ -329,7 +347,11 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
* vanishes at least if compiled with no optimisation.
*/
oneshot->start_count = sam_tc_getcounter(freerun->tch);
if (freerun != NULL)
{
oneshot->start_count = sam_tc_getcounter(freerun->tch);
}
#endif
/* Enable interrupts. We should get the callback when the interrupt
* occurs.
@ -365,8 +387,8 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
*
****************************************************************************/
int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freerun,
struct timespec *ts)
int sam_oneshot_cancel(struct sam_oneshot_s *oneshot,
struct sam_freerun_s *freerun, struct timespec *ts)
{
irqstate_t flags;
uint64_t usec;
@ -407,16 +429,19 @@ int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *free
count = sam_tc_getcounter(oneshot->tch);
rc = sam_tc_getregister(oneshot->tch, TC_REGC);
#ifdef CONFIG_SAMA5_FREERUN
/* In the case the timer/counter was canceled very short after its start,
* the counter register can hold the wrong value (the value of the last
* run). To prevent this the counter value is set to zero if not at
* least on tick passed since the start of the timer/counter.
*/
if (count > 0 && sam_tc_getcounter(freerun->tch) == oneshot->start_count)
if (count > 0 && freerun != NULL &&
sam_tc_getcounter(freerun->tch) == oneshot->start_count)
{
count = 0;
}
#endif
/* Now we can disable the interrupt and stop the timer. */

42
arch/arm/src/sama5/sam_oneshot.h
View File

@ -46,7 +46,6 @@
#include <time.h>
#include "sam_tc.h"
#include "sam_freerun.h"
#ifdef CONFIG_SAMA5_ONESHOT
@ -83,11 +82,13 @@ struct sam_oneshot_s
volatile oneshot_handler_t handler; /* Oneshot expiration callback */
volatile void *arg; /* The argument that will accompany
* the callback */
#ifdef CONFIG_SAMA5_FREERUN
volatile uint32_t start_count; /* Stores the value of the freerun counter,
* at each start of the onshot timer. Is neccesary
* to find out if the onshot counter was updated
* correctly at the time of the call to
* sam_oneshot_cancel or not. */
#endif
};
/****************************************************************************
@ -130,6 +131,27 @@ extern "C"
int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
uint16_t resolution);
/****************************************************************************
* Name: sam_oneshot_max_delay
*
* Description:
* Return the maximum delay supported by the one shot timer (in
* microseconds).
*
* Input Parameters:
* oneshot Caller allocated instance of the oneshot state structure. This
* structure must have been previously initialized via a call to
* sam_oneshot_initialize();
* usec The location in which to return the maximum delay.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on failure.
*
****************************************************************************/
int sam_oneshot_max_delay(struct sam_oneshot_s *oneshot, uint64_t *usec);
/****************************************************************************
* Name: sam_oneshot_start
*
@ -142,7 +164,8 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
* sam_oneshot_initialize();
* freerun Caller allocated instance of the freerun state structure. This
* structure must have been previously initialized via a call to
* sam_freerun_initialize();
* sam_freerun_initialize(). May be NULL if there is no matching
* free-running timer.
* handler The function to call when when the oneshot timer expires.
* arg An opaque argument that will accompany the callback.
* ts Provides the duration of the one shot timer.
@ -153,8 +176,11 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
*
****************************************************************************/
int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freerun,
oneshot_handler_t handler, void *arg, const struct timespec *ts);
struct sam_freerun_s;
int sam_oneshot_start(struct sam_oneshot_s *oneshot,
struct sam_freerun_s *freerun,
oneshot_handler_t handler, void *arg,
const struct timespec *ts);
/****************************************************************************
* Name: sam_oneshot_cancel
@ -171,7 +197,8 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
* sam_oneshot_initialize();
* freerun Caller allocated instance of the freerun state structure. This
* structure must have been previously initialized via a call to
* sam_freerun_initialize();
* sam_freerun_initialize(). May be NULL if there is no matching
* free-running timer.
* ts The location in which to return the time remaining on the
* oneshot timer. A time of zero is returned if the timer is
* not running.
@ -183,8 +210,9 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
*
****************************************************************************/
int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freerun,
struct timespec *ts);
struct sam_freerun_s;
int sam_oneshot_cancel(struct sam_oneshot_s *oneshot,
struct sam_freerun_s *freerun, struct timespec *ts);
#undef EXTERN
#ifdef __cplusplus

347
arch/arm/src/sama5/sam_oneshot_lowerhalf.c Normal file
View File

@ -0,0 +1,347 @@
/****************************************************************************
* arch/arm/src/sam/sam_oneshot_lowerhalf.c
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <time.h>
#include <limits.h>
#include <assert.h>
#include <errno.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/kmalloc.h>
#include <nuttx/timers/oneshot.h>
#include "sam_oneshot.h"
/****************************************************************************
* Private Types
****************************************************************************/
/* This structure describes the state of the oneshot timer lower-half driver */
struct sam_oneshot_lowerhalf_s
{
/* This is the part of the lower half driver that is visible to the upper-
* half client of the driver. This must be the first thing in this
* structure so that pointers to struct oneshot_lowerhalf_s are cast
* compatible to struct sam_oneshot_lowerhalf_s and vice versa.
*/
struct oneshot_lowerhalf_s lh; /* Common lower-half driver fields */
/* Private lower half data follows */
struct sam_oneshot_s oneshot; /* SAM-specific oneshot state */
oneshot_callback_t callback; /* internal handler that receives callback */
FAR void *arg; /* Argument that is passed to the handler */
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
static void sam_oneshot_handler(void *arg);
static int sam_max_delay(FAR struct oneshot_lowerhalf_s *lower,
FAR struct timespec *ts);
static int sam_start(FAR struct oneshot_lowerhalf_s *lower,
oneshot_callback_t callback, FAR void *arg,
FAR const struct timespec *ts);
static int sam_cancel(FAR struct oneshot_lowerhalf_s *lower,
FAR struct timespec *ts);
/****************************************************************************
* Private Data
****************************************************************************/
/* Lower half operations */
static const struct oneshot_operations_s g_oneshot_ops =
{
.max_delay = sam_max_delay,
.start = sam_start,
.cancel = sam_cancel,
};
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: sam_oneshot_handler
*
* Description:
* Timer expiration handler
*
* Input Parameters:
* arg - Should be the same argument provided when sam_oneshot_start()
* was called.
*
* Returned Value:
* None
*
****************************************************************************/
static void sam_oneshot_handler(void *arg)
{
FAR struct sam_oneshot_lowerhalf_s *priv =
(FAR struct sam_oneshot_lowerhalf_s *)arg;
oneshot_callback_t callback;
FAR void *cbarg;
DEBUGASSERT(priv != NULL);
/* Perhaps the callback was nullified in a race condition with
* sam_cancel?
*/
if (priv->callback)
{
/* Sample and nullify BEFORE executing callback (in case the callback
* restarts the oneshot).
*/
callback = priv->callback;
cbarg = priv->arg;
priv->callback = NULL;
priv->arg = NULL;
/* Then perform the callback */
callback(&priv->lh, cbarg);
}
}
/****************************************************************************
* Name: sam_max_delay
*
* Description:
* Determine the maximum delay of the one-shot timer (in microseconds)
*
* Input Parameters:
* lower An instance of the lower-half oneshot state structure. This
* structure must have been previously initialized via a call to
* oneshot_initialize();
* ts The location in which to return the maxumum delay.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on failure.
*
****************************************************************************/
static int sam_max_delay(FAR struct oneshot_lowerhalf_s *lower,
FAR struct timespec *ts)
{
FAR struct sam_oneshot_lowerhalf_s *priv =
(FAR struct sam_oneshot_lowerhalf_s *)lower;
uint64_t usecs;
int ret;
DEBUGASSERT(priv != NULL && ts != NULL);
ret = sam_oneshot_max_delay(&priv->oneshot, &usecs);
if (ret >= 0)
{
uint64_t sec = usecs / 1000000;
usecs -= 1000000 * sec;
ts->tv_sec = (time_t)sec;
ts->tv_nsec = (long)(usecs * 1000);
}
return ret;
}
/****************************************************************************
* Name: sam_start
*
* Description:
* Start the oneshot timer
*
* Input Parameters:
* lower An instance of the lower-half oneshot state structure. This
* structure must have been previously initialized via a call to
* oneshot_initialize();
* handler The function to call when when the oneshot timer expires.
* arg An opaque argument that will accompany the callback.
* ts Provides the duration of the one shot timer.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on failure.
*
****************************************************************************/
static int sam_start(FAR struct oneshot_lowerhalf_s *lower,
oneshot_callback_t callback, FAR void *arg,
FAR const struct timespec *ts)
{
FAR struct sam_oneshot_lowerhalf_s *priv =
(FAR struct sam_oneshot_lowerhalf_s *)lower;
irqstate_t flags;
int ret;
DEBUGASSERT(priv != NULL && callback != NULL && ts != NULL);
/* Save the callback information and start the timer */
flags = enter_critical_section();
priv->callback = callback;
priv->arg = arg;
ret = sam_oneshot_start(&priv->oneshot, NULL,
sam_oneshot_handler, priv, ts);
leave_critical_section(flags);
if (ret < 0)
{
tmrerr("ERROR: sam_oneshot_start failed: %d\n", flags);
}
return ret;
}
/****************************************************************************
* Name: sam_cancel
*
* Description:
* Cancel the oneshot timer and return the time remaining on the timer.
*
* NOTE: This function may execute at a high rate with no timer running (as
* when pre-emption is enabled and disabled).
*
* Input Parameters:
* lower Caller allocated instance of the oneshot state structure. This
* structure must have been previously initialized via a call to
* oneshot_initialize();
* ts The location in which to return the time remaining on the
* oneshot timer. A time of zero is returned if the timer is
* not running.
*
* Returned Value:
* Zero (OK) is returned on success. A call to up_timer_cancel() when
* the timer is not active should also return success; a negated errno
* value is returned on any failure.
*
****************************************************************************/
static int sam_cancel(FAR struct oneshot_lowerhalf_s *lower,
FAR struct timespec *ts)
{
FAR struct sam_oneshot_lowerhalf_s *priv =
(FAR struct sam_oneshot_lowerhalf_s *)lower;
irqstate_t flags;
int ret;
DEBUGASSERT(priv != NULL);
/* Cancel the timer */
flags = enter_critical_section();
ret = sam_oneshot_cancel(&priv->oneshot, NULL, ts);
priv->callback = NULL;
priv->arg = NULL;
leave_critical_section(flags);
if (ret < 0)
{
tmrerr("ERROR: sam_oneshot_cancel failed: %d\n", flags);
}
return ret;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: oneshot_initialize
*
* Description:
* Initialize the oneshot timer and return a oneshot lower half driver
* instance.
*
* Input Parameters:
* chan Timer counter channel to be used.
* resolution The required resolution of the timer in units of
* microseconds. NOTE that the range is restricted to the
* range of uint16_t (excluding zero).
*
* Returned Value:
* On success, a non-NULL instance of the oneshot lower-half driver is
* returned. NULL is return on any failure.
*
****************************************************************************/
FAR struct oneshot_lowerhalf_s *oneshot_initialize(int chan,
uint16_t resolution)
{
FAR struct sam_oneshot_lowerhalf_s *priv;
int ret;
/* Allocate an instance of the lower half driver */
priv = (FAR struct sam_oneshot_lowerhalf_s *)
kmm_zalloc(sizeof(struct sam_oneshot_lowerhalf_s));
if (priv == NULL)
{
tmrerr("ERROR: Failed to initialized state structure\n");
return NULL;
}
/* Initialize the lower-half driver structure */
priv->lh.ops = &g_oneshot_ops;
/* Initialize the contained SAM oneshot timer */
ret = sam_oneshot_initialize(&priv->oneshot, chan, resolution);
if (ret < 0)
{
tmrerr("ERROR: sam_oneshot_initialize failed: %d\n", ret);
kmm_free(priv);
return NULL;
}
return &priv->lh;
}

71
arch/arm/src/samv7/Kconfig
View File

@ -102,7 +102,7 @@ config ARCH_CHIP_SAME70Q
default n
select ARCH_CHIP_SAME70
select SAMV7_HAVE_MCAN1
select SAMV7_HAVE_DAC1
select SAMV7_HAVE_DAC1 if !SAMV7_EMAC0
select SAMV7_HAVE_EBI
select SAMV7_HAVE_HSMCI0
select SAMV7_HAVE_SDRAMC
@ -119,7 +119,7 @@ config ARCH_CHIP_SAME70N
default n
select ARCH_CHIP_SAME70
select SAMV7_HAVE_MCAN1
select SAMV7_HAVE_DAC1
select SAMV7_HAVE_DAC1 if !SAMV7_EMAC0
select SAMV7_HAVE_HSMCI0
select SAMV7_HAVE_SPI0
select SAMV7_HAVE_TWIHS2
@ -152,7 +152,7 @@ config ARCH_CHIP_SAMV71Q
default n
select ARCH_CHIP_SAMV71
select SAMV7_HAVE_MCAN1
select SAMV7_HAVE_DAC1
select SAMV7_HAVE_DAC1 if !SAMV7_EMAC0
select SAMV7_HAVE_EBI
select SAMV7_HAVE_HSMCI0
select SAMV7_HAVE_SDRAMC
@ -169,7 +169,7 @@ config ARCH_CHIP_SAMV71N
default n
select ARCH_CHIP_SAMV71
select SAMV7_HAVE_MCAN1
select SAMV7_HAVE_DAC1
select SAMV7_HAVE_DAC1 if !SAMV7_EMAC0
select SAMV7_HAVE_HSMCI0
select SAMV7_HAVE_SPI0
select SAMV7_HAVE_TWIHS2
@ -196,6 +196,10 @@ config SAMV7_HAVE_MCAN1
bool
default n
config SAMV7_DAC
bool
default n
config SAMV7_HAVE_DAC1
bool
default n
@ -334,10 +338,12 @@ config SAMV7_MCAN1
config SAMV7_DAC0
bool "Digital To Analog Converter 0 (DAC0)"
default n
select SAMV7_DAC
config SAMV7_DAC1
bool "Digital To Analog Converter 1 (DAC1)"
default n
select SAMV7_DAC
depends on SAMV7_HAVE_DAC1
config SAMV7_EBI
@ -1600,7 +1606,6 @@ endif # SAMV7_TC3
config SAMV7_ONESHOT
bool "TC one-shot wrapper"
depends on SAMV7_FREERUN
default n if !SCHED_TICKLESS
default y if SCHED_TICKLESS
---help---
@ -1658,6 +1663,62 @@ config SAMV7_TC_REGDEBUG
endmenu # Timer/counter Configuration
endif # SAMV7_HAVE_TC
menu "DAC device driver configuration"
depends on SAMV7_DAC
config SAMV7_DAC_PRESCAL
int "DAC MCK prescaler"
default 7
range 0 15
---help---
Define PRESCALER (Peripheral Clock to DAC Clock Ratio)
0 -> 2 periods of DAC Clock
1 -> 3 periods of DAC Clock
2 -> 4 periods of DAC Clock
3 -> 5 periods of DAC Clock
4 -> 6 periods of DAC Clock
5 -> 7 periods of DAC Clock
6 -> 8 periods of DAC Clock
7 -> 9 periods of DAC Clock
8 -> 10 periods of DAC Clock
9 -> 11 periods of DAC Clock
10 -> 12 periods of DAC Clock
11 -> 13 periods of DAC Clock
12 -> 14 periods of DAC Clock
13 -> 15 periods of DAC Clock
14 -> 16 periods of DAC Clock
15 -> 17 periods of DAC Clock
config SAMV7_DAC_TRIGGER
bool "DAC trigger mode"
default n
---help---
Enable DAC trigger mode
if SAMV7_DAC_TRIGGER
config SAMV7_DAC_TRIGGER_FREQUENCY
int "DAC trigger frequency"
default 1000
---help---
Define DAC trigger frequency
config SAMV7_DAC_TRIGGER_SELECT
int "DAC trigger source"
default 3
range 1 3
---help---
Define DAC trigger source. Snly support for TC0, TC1, TC2 output is
currently implemented:
1 -> TC0
2 -> TC1
3 -> TC2
endif # SAMV7_DAC_TRIGGER
endmenu # DAC device driver configuration
menu "HSMCI device driver options"
depends on SAMV7_HSMCI

6
arch/arm/src/samv7/Make.defs
View File

@ -181,7 +181,7 @@ endif
ifeq ($(CONFIG_SAMV7_HAVE_TC),y)
CHIP_CSRCS += sam_tc.c
ifeq ($(CONFIG_SAMV7_ONESHOT),y)
CHIP_CSRCS += sam_oneshot.c
CHIP_CSRCS += sam_oneshot.c sam_oneshot_lowerhalf.c
endif
ifeq ($(CONFIG_SAMV7_FREERUN),y)
CHIP_CSRCS += sam_freerun.c
@ -214,3 +214,7 @@ endif
ifeq ($(CONFIG_SAMV7_PROGMEM),y)
CHIP_CSRCS += sam_progmem.c
endif
ifeq ($(CONFIG_SAMV7_DAC),y)
CHIP_CSRCS += sam_dac.c
endif

226
arch/arm/src/samv7/chip/sam_dacc.h Normal file
View File

@ -0,0 +1,226 @@
/****************************************************************************************
* arch/arm/src/samv7/chip/sam_dacc.h
* Digital-to-Analog Converter Controller (DACC) for the SAMV7
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_DACC_H
#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_DACC_H
/****************************************************************************************
* Included Files
****************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "chip/sam_memorymap.h"
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* DACC register offsets *****************************************************************/
#define SAM_DACC_CR_OFFSET 0x0000 /* Control Register */
#define SAM_DACC_MR_OFFSET 0x0004 /* Mode Register */
#define SAM_DACC_TRIGR_OFFSET 0x0008 /* Trigger Register */
#define SAM_DACC_CHER_OFFSET 0x0010 /* Channel Enable Register */
#define SAM_DACC_CHDR_OFFSET 0x0014 /* Channel Disable Register */
#define SAM_DACC_CHSR_OFFSET 0x0018 /* Channel Status Register */
#define SAM_DACC_CDR0_OFFSET 0x001c /* Conversion Data Register 0 */
#define SAM_DACC_CDR1_OFFSET 0x0020 /* Conversion Data Register 1 */
#define SAM_DACC_IER_OFFSET 0x0024 /* Interrupt Enable Register */
#define SAM_DACC_IDR_OFFSET 0x0028 /* Interrupt Disable Register */
#define SAM_DACC_IMR_OFFSET 0x002c /* Interrupt Mask Register */
#define SAM_DACC_ISR_OFFSET 0x0030 /* Interrupt Status Register */
#define SAM_DACC_ACR_OFFSET 0x0094 /* Analog Current Register */
#define SAM_DACC_WPMR_OFFSET 0x00e4 /* Write Protect Mode register */
#define SAM_DACC_WPSR_OFFSET 0x00e8 /* Write Protect Status register */
/* DACC register addresses **************************************************************/
#define SAM_DACC_CR (SAM_DACC_BASE+SAM_DACC_CR_OFFSET)
#define SAM_DACC_MR (SAM_DACC_BASE+SAM_DACC_MR_OFFSET)
#define SAM_DACC_TRIGR (SAM_DACC_BASE+SAM_DACC_TRIGR_OFFSET)
#define SAM_DACC_CHER (SAM_DACC_BASE+SAM_DACC_CHER_OFFSET)
#define SAM_DACC_CHDR (SAM_DACC_BASE+SAM_DACC_CHDR_OFFSET)
#define SAM_DACC_CHSR (SAM_DACC_BASE+SAM_DACC_CHSR_OFFSET)
#define SAM_DACC_CDR0 (SAM_DACC_BASE+SAM_DACC_CDR0_OFFSET)
#define SAM_DACC_CDR1 (SAM_DACC_BASE+SAM_DACC_CDR1_OFFSET)
#define SAM_DACC_IER (SAM_DACC_BASE+SAM_DACC_IER_OFFSET)
#define SAM_DACC_IDR (SAM_DACC_BASE+SAM_DACC_IDR_OFFSET)
#define SAM_DACC_IMR (SAM_DACC_BASE+SAM_DACC_IMR_OFFSET)
#define SAM_DACC_ISR (SAM_DACC_BASE+SAM_DACC_ISR_OFFSET)
#define SAM_DACC_ACR (SAM_DACC_BASE+SAM_DACC_ACR_OFFSET)
#define SAM_DACC_WPMR (SAM_DACC_BASE+SAM_DACC_WPMR_OFFSET)
#define SAM_DACC_WPSR (SAM_DACC_BASE+SAM_DACC_WPSR_OFFSET)
/* DACC register bit definitions ********************************************************/
/* Control Register */
#define DACC_CR_SWRST (1 << 0) /* Bit 0: Software reset */
/* Mode Register */
#define DACC_MR_MAXS0 (1 << 0) /* Max Speed Mode for Channel 0 */
# define DACC_MR_MAXS0_TRIG_EVENT (0 << 0) /* External trigger mode or Free-running mode enabled */
# define DACC_MR_MAXS0_MAXIMUM (1 << 0) /* Max speed mode enabled */
#define DACC_MR_MAXS1 (1 << 1) /* Max Speed Mode for Channel 1 */
# define DACC_MR_MAXS1_TRIG_EVENT (0 << 1) /* External trigger mode or Free-running mode enabled */
# define DACC_MR_MAXS1_MAXIMUM (1 << 1) /* Max speed mode enabled */
#define DACC_MR_WORD (1 << 4) /* Word Transfer Mode */
# define DACC_MR_WORD_DISABLED (0 << 4) /* One data to convert is written to the FIFO per access to DACC */
# define DACC_MR_WORD_ENABLED (1 << 4) /* Two data to convert are written to the FIFO per access to DACC */
#define DACC_MR_ZERO (1 << 5) /* Must always be written to 0 */
#define DACC_MR_DIFF (1 << 23) /* Differential Mode */
# define DACC_MR_DIFF_DISABLED (0 << 23) /* DAC0 and DAC1 are single-ended outputs */
# define DACC_MR_DIFF_ENABLED (1 << 23) /* DACP and DACN are differential outputs. The differential level is configured by the channel 0 value. */
#define DACC_MR_PRESCALER_SHIFT (24)
#define DACC_MR_PRESCALER_MASK (0xfu << DACC_MR_PRESCALER_SHIFT) /* Peripheral Clock to DAC Clock Ratio */
#define DACC_MR_PRESCALER(value) ((DACC_MR_PRESCALER_MASK & ((value) << DACC_MR_PRESCALER_SHIFT)))
# define DACC_MR_PRESCALER_2 (0 << DACC_MR_PRESCALER_SHIFT) /* 2 periods of DAC Clock */
# define DACC_MR_PRESCALER_3 (1 << DACC_MR_PRESCALER_SHIFT) /* 3 periods of DAC Clock */
# define DACC_MR_PRESCALER_4 (2 << DACC_MR_PRESCALER_SHIFT) /* 4 periods of DAC Clock */
# define DACC_MR_PRESCALER_5 (3 << DACC_MR_PRESCALER_SHIFT) /* 5 periods of DAC Clock */
# define DACC_MR_PRESCALER_6 (4 << DACC_MR_PRESCALER_SHIFT) /* 6 periods of DAC Clock */
# define DACC_MR_PRESCALER_7 (5 << DACC_MR_PRESCALER_SHIFT) /* 7 periods of DAC Clock */
# define DACC_MR_PRESCALER_8 (6 << DACC_MR_PRESCALER_SHIFT) /* 8 periods of DAC Clock */
# define DACC_MR_PRESCALER_9 (7 << DACC_MR_PRESCALER_SHIFT) /* 9 periods of DAC Clock */
# define DACC_MR_PRESCALER_10 (8 << DACC_MR_PRESCALER_SHIFT) /* 10 periods of DAC Clock */
# define DACC_MR_PRESCALER_11 (9 << DACC_MR_PRESCALER_SHIFT) /* 11 periods of DAC Clock */
# define DACC_MR_PRESCALER_12 (10 << DACC_MR_PRESCALER_SHIFT) /* 12 periods of DAC Clock */
# define DACC_MR_PRESCALER_13 (11 << DACC_MR_PRESCALER_SHIFT) /* 13 periods of DAC Clock */
# define DACC_MR_PRESCALER_14 (12 << DACC_MR_PRESCALER_SHIFT) /* 14 periods of DAC Clock */
# define DACC_MR_PRESCALER_15 (13 << DACC_MR_PRESCALER_SHIFT) /* 15 periods of DAC Clock */
# define DACC_MR_PRESCALER_16 (14 << DACC_MR_PRESCALER_SHIFT) /* 16 periods of DAC Clock */
# define DACC_MR_PRESCALER_17 (15 << DACC_MR_PRESCALER_SHIFT) /* 17 periods of DAC Clock */
/* Trigger Register */
#define DACC_TRIGR_TRGEN0 (1 << 0) /* Trigger Enable of Channel 0 */
# define DACC_TRIGR_TRGEN0_DIS (0 << 0) /* External trigger mode disabled. DACC is in Free-running mode or Max speed mode. */
# define DACC_TRIGR_TRGEN0_EN (1 << 0) /* External trigger mode enabled. */
#define DACC_TRIGR_TRGEN1 (1 << 1) /* Trigger Enable of Channel 1 */
# define DACC_TRIGR_TRGEN1_DIS (0 << 1) /* External trigger mode disabled. DACC is in Free-running mode or Max speed mode. */
# define DACC_TRIGR_TRGEN1_EN (1 << 1) /* External trigger mode enabled. */
#define DACC_TRIGR_TRGSEL0_SHIFT (4)
#define DACC_TRIGR_TRGSEL0_MASK (0x7u << DACC_TRIGR_TRGSEL0_SHIFT) /* Trigger Selection of Channel 0 */
#define DACC_TRIGR_TRGSEL0(value) ((DACC_TRIGR_TRGSEL0_MASK & ((value) << DACC_TRIGR_TRGSEL0_SHIFT)))
# define DACC_TRIGR_TRGSEL0_DATRG (0 << 4) /* DATRG output */
# define DACC_TRIGR_TRGSEL0_TC0 (1 << 4) /* TC0 output */
# define DACC_TRIGR_TRGSEL0_TC1 (2 << 4) /* TC1 output */
# define DACC_TRIGR_TRGSEL0_TC2 (3 << 4) /* TC2 output */
# define DACC_TRIGR_TRGSEL0_PWM0EV0 (4 << 4) /* PWM0 event 0 */
# define DACC_TRIGR_TRGSEL0_PWM0EV1 (5 << 4) /* PWM0 event 1 */
# define DACC_TRIGR_TRGSEL0_PWM1EV0 (6 << 4) /* PWM1 event 0 */
# define DACC_TRIGR_TRGSEL0_PWM1EV1 (7 << 4) /* PWM1 event 1 */
#define DACC_TRIGR_TRGSEL1_SHIFT (8)
#define DACC_TRIGR_TRGSEL1_MASK (0x7u << DACC_TRIGR_TRGSEL1_SHIFT) /* Trigger Selection of Channel 1 */
#define DACC_TRIGR_TRGSEL1(value) ((DACC_TRIGR_TRGSEL1_MASK & ((value) << DACC_TRIGR_TRGSEL1_SHIFT)))
# define DACC_TRIGR_TRGSEL1_DATRG (0 << 8) /* DATRG output */
# define DACC_TRIGR_TRGSEL1_TC0 (1 << 8) /* TC0 output */
# define DACC_TRIGR_TRGSEL1_TC1 (2 << 8) /* TC1 output */
# define DACC_TRIGR_TRGSEL1_TC2 (3 << 8) /* TC2 output */
# define DACC_TRIGR_TRGSEL1_PWM0EV0 (4 << 8) /* PWM0 event 0 */
# define DACC_TRIGR_TRGSEL1_PWM0EV1 (5 << 8) /* PWM0 event 1 */
# define DACC_TRIGR_TRGSEL1_PWM1EV0 (6 << 8) /* PWM1 event 0 */
# define DACC_TRIGR_TRGSEL1_PWM1EV1 (7 << 8) /* PWM1 event 1 */
#define DACC_TRIGR_OSR0_SHIFT (16)
#define DACC_TRIGR_OSR0_MASK (0x7u << DACC_TRIGR_OSR0_SHIFT) /* Over Sampling Ratio of Channel 0 */
#define DACC_TRIGR_OSR0(value) ((DACC_TRIGR_OSR0_MASK & ((value) << DACC_TRIGR_OSR0_SHIFT)))
# define DACC_TRIGR_OSR0_OSR_1 (0 << 16) /* OSR = 1 */
# define DACC_TRIGR_OSR0_OSR_2 (1 << 16) /* OSR = 2 */
# define DACC_TRIGR_OSR0_OSR_4 (2 << 16) /* OSR = 4 */
# define DACC_TRIGR_OSR0_OSR_8 (3 << 16) /* OSR = 8 */
# define DACC_TRIGR_OSR0_OSR_16 (4 << 16) /* OSR = 16 */
# define DACC_TRIGR_OSR0_OSR_32 (5 << 16) /* OSR = 32 */
#define DACC_TRIGR_OSR1_SHIFT (20)
#define DACC_TRIGR_OSR1_MASK (0x7u << DACC_TRIGR_OSR1_SHIFT) /* Over Sampling Ratio of Channel 1 */
#define DACC_TRIGR_OSR1(value) ((DACC_TRIGR_OSR1_MASK & ((value) << DACC_TRIGR_OSR1_SHIFT)))
# define DACC_TRIGR_OSR1_OSR_1 (0 << 20) /* OSR = 1 */
# define DACC_TRIGR_OSR1_OSR_2 (1 << 20) /* OSR = 2 */
# define DACC_TRIGR_OSR1_OSR_4 (2 << 20) /* OSR = 4 */
# define DACC_TRIGR_OSR1_OSR_8 (3 << 20) /* OSR = 8 */
# define DACC_TRIGR_OSR1_OSR_16 (4 << 20) /* OSR = 16 */
# define DACC_TRIGR_OSR1_OSR_32 (5 << 20) /* OSR = 32 */
/* Channel Enable, Channel Disable, and Channel Status Registers */
#define DACC_CH0 (1 << 0) /* Channel 0 */
#define DACC_CH1 (1 << 1) /* Channel 1 */
#define DACC_CHSR_DACRDY0 (1 << 8) /* DAC Ready Flag */
#define DACC_CHSR_DACRDY1 (1 << 9) /* DAC Ready Flag */
/* Conversion Data Register -- 32-bit data */
#define DACC_CDR_DATA0_SHIFT (0)
#define DACC_CDR_DATA0_MASK (0xffffu << DACC_CDR_DATA0_SHIFT) /* Data to Convert for channel 0 */
#define DACC_CDR_DATA0(value) ((DACC_CDR_DATA0_MASK & ((value) << DACC_CDR_DATA0_SHIFT)))
#define DACC_CDR_DATA1_SHIFT (16)
#define DACC_CDR_DATA1_MASK (0xffffu << DACC_CDR_DATA1_SHIFT) /* Data to Convert for channel 1 */
#define DACC_CDR_DATA1(value) ((DACC_CDR_DATA1_MASK & ((value) << DACC_CDR_DATA1_SHIFT)))
/* Interrupt Enable, Interrupt Disable, Interrupt Mask, and Interrupt Status Register */
#define DACC_INT_TXRDY0 (1 << 0) /* Transmit Ready Interrupt of channel 0 */
#define DACC_INT_TXRDY1 (1 << 1) /* Transmit Ready Interrupt of channel 1 */
#define DACC_INT_EOC0 (1 << 4) /* End of Conversion Interrupt of channel 0 */
#define DACC_INT_EOC1 (1 << 5) /* End of Conversion Interrupt of channel 1 */
#define DACC_INT_ALL (0xffffffffu) /* All interrupts */
/* Analog Current Register */
#define DACC_ACR_IBCTLCH0_SHIFT (0)
#define DACC_ACR_IBCTLCH0_MASK (0x3u << DACC_ACR_IBCTLCH0_SHIFT) /* Analog Output Current Control */
#define DACC_ACR_IBCTLCH0(value) ((DACC_ACR_IBCTLCH0_MASK & ((value) << DACC_ACR_IBCTLCH0_SHIFT)))
#define DACC_ACR_IBCTLCH1_SHIFT (2)
#define DACC_ACR_IBCTLCH1_MASK (0x3u << DACC_ACR_IBCTLCH1_SHIFT) /* Analog Output Current Control */
#define DACC_ACR_IBCTLCH1(value) ((DACC_ACR_IBCTLCH1_MASK & ((value) << DACC_ACR_IBCTLCH1_SHIFT)))
/* Write Protect Mode register */
#define DACC_WPMR_WPEN (1 << 0) /* Write Protection Enable */
#define DACC_WPMR_WPKEY_SHIFT (8)
#define DACC_WPMR_WPKEY_MASK (0xffffffu << DACC_WPMR_WPKEY_SHIFT) /* Write Protect Key */
#define DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_MASK & ((value) << DACC_WPMR_WPKEY_SHIFT)))
# define DACC_WPMR_WPKEY_PASSWD (0x444143u << 8) /* Writing any other value in this field aborts the write operation of bit WPEN. Always reads as 0. */
/* Write Protect Status register */
#define DACC_WPSR_WPVS (1 << 0) /* Write Protection Violation Status */
#define DACC_WPSR_WPVSRC_SHIFT (8)
#define DACC_WPSR_WPVSRC_MASK (0xffu << DACC_WPSR_WPVSRC_SHIFT) /* Write Protection Violation Source */
#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_DACC_H */

658
arch/arm/src/samv7/sam_dac.c Normal file
View File

@ -0,0 +1,658 @@
/************************************************************************************
* arch/arm/src/samv7/sam_dac.c
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <semaphore.h>
#include <errno.h>
#include <debug.h>
#include <arch/board/board.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <nuttx/analog/dac.h>
#include "up_internal.h"
#include "up_arch.h"
#include "cache.h"
#include "chip/sam_dacc.h"
#include "chip/sam_pmc.h"
#include "chip/sam_pinmap.h"
#include "sam_gpio.h"
#include "sam_xdmac.h"
#include "sam_periphclks.h"
#include "sam_tc.h"
#include "sam_dac.h"
#if defined(CONFIG_SAMV7_DAC0) || defined(CONFIG_SAMV7_DAC1)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Get TC channel number from Trigger Selection value */
#define SAMV7_DAC_TC_CHANNEL (CONFIG_SAMV7_DAC_TRIGGER_SELECT - 1)
/****************************************************************************
* Private Types
****************************************************************************/
/* This structure represents the internal state of a single SAMV7 DAC module */
struct sam_dac_s
{
uint8_t initialized : 1; /* True, the DAC block has been initialized */
#ifdef CONFIG_SAMV7_DAC_TRIGGER
TC_HANDLE tc; /* Timer handle */
#endif
};
/* This structure represents the internal state of one SAMV7 DAC channel */
struct sam_chan_s
{
uint8_t inuse : 1; /* True, the driver is in use and not available */
uint8_t intf; /* DAC zero-based interface number (0 or 1) */
uint32_t dro; /* Conversion Data Register */
#ifdef CONFIG_SAMV7_DAC_TRIGGER
uint32_t reg_dacc_trigr_clear; /* channel DACC_TRIGR register clear bits */
uint32_t reg_dacc_trigr_set; /* channel DACC_TRIGR register set bits */
#endif
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/* Interrupt handler */
static int dac_interrupt(int irq, FAR void *context);
/* DAC methods */
static void dac_reset(FAR struct dac_dev_s *dev);
static int dac_setup(FAR struct dac_dev_s *dev);
static void dac_shutdown(FAR struct dac_dev_s *dev);
static void dac_txint(FAR struct dac_dev_s *dev, bool enable);
static int dac_send(FAR struct dac_dev_s *dev, FAR struct dac_msg_s *msg);
static int dac_ioctl(FAR struct dac_dev_s *dev, int cmd, unsigned long arg);
/* Initialization */
#ifdef CONFIG_SAMV7_DAC_TRIGGER
static int dac_timer_init(struct sam_dac_s *priv, uint32_t freq_required,
int channel);
static void dac_timer_free(struct sam_dac_s *priv);
#endif
static int dac_channel_init(FAR struct sam_chan_s *chan);
static int dac_module_init(void);
/****************************************************************************
* Private Data
****************************************************************************/
static const struct dac_ops_s g_dacops =
{
.ao_reset = dac_reset,
.ao_setup = dac_setup,
.ao_shutdown = dac_shutdown,
.ao_txint = dac_txint,
.ao_send = dac_send,
.ao_ioctl = dac_ioctl,
};
#ifdef CONFIG_SAMV7_DAC0
static struct sam_chan_s g_dac1priv =
{
.intf = 0,
.dro = SAM_DACC_CDR0,
#ifdef CONFIG_SAMV7_DAC_TRIGGER
.reg_dacc_trigr_clear = DACC_TRIGR_TRGSEL0_MASK,
.reg_dacc_trigr_set = DACC_TRIGR_TRGSEL0(CONFIG_SAMV7_DAC_TRIGGER_SELECT) | DACC_TRIGR_TRGEN0,
#endif
};
static struct dac_dev_s g_dac1dev =
{
.ad_ops = &g_dacops,
.ad_priv = &g_dac1priv,
};
#endif
#ifdef CONFIG_SAMV7_DAC1
static struct sam_chan_s g_dac2priv =
{
.intf = 1,
.dro = SAM_DACC_CDR1,
#ifdef CONFIG_SAMV7_DAC_TRIGGER
.reg_dacc_trigr_clear = DACC_TRIGR_TRGSEL1_MASK,
.reg_dacc_trigr_set = DACC_TRIGR_TRGSEL1(CONFIG_SAMV7_DAC_TRIGGER_SELECT) | DACC_TRIGR_TRGEN1,
#endif
};
static struct dac_dev_s g_dac2dev =
{
.ad_ops = &g_dacops,
.ad_priv = &g_dac2priv,
};
#endif
static struct sam_dac_s g_dacmodule;
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: dac_interrupt
*
* Description:
* DAC interrupt handler.
*
* Input Parameters:
*
* Returned Value:
* OK
*
****************************************************************************/
static int dac_interrupt(int irq, FAR void *context)
{
#ifdef CONFIG_SAMV7_DAC1
uint32_t status;
status = getreg32(SAM_DACC_ISR) & getreg32(SAM_DACC_IMR);
if (status & DACC_INT_TXRDY1)
{
dac_txdone(&g_dac2dev);
}
if (status & DACC_INT_TXRDY0)
#endif
{
dac_txdone(&g_dac1dev);
}
return OK;
}
/****************************************************************************
* Name: dac_reset
*
* Description:
* Reset the DAC channel. Called early to initialize the hardware. This
* is called, before dac_setup() and on error conditions.
*
* Input Parameters:
*
* Returned Value:
* None
*
****************************************************************************/
static void dac_reset(FAR struct dac_dev_s *dev)
{
irqstate_t flags;
/* Reset only the selected DAC channel; the other DAC channel must remain
* functional.
*/
flags = enter_critical_section();
#warning "Missing logic"
leave_critical_section(flags);
}
/****************************************************************************
* Name: dac_setup
*
* Description:
* Configure the DAC. This method is called the first time that the DAC
* device is opened. This will occur when the port is first opened.
* This setup includes configuring and attaching DAC interrupts. Interrupts
* are all disabled upon return.
*
* Input Parameters:
*
* Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
static int dac_setup(FAR struct dac_dev_s *dev)
{
#warning "Missing logic"
return OK;
}
/****************************************************************************
* Name: dac_shutdown
*
* Description:
* Disable the DAC. This method is called when the DAC device is closed.
* This method reverses the operation the setup method.
*
* Input Parameters:
*
* Returned Value:
* None
*
****************************************************************************/
static void dac_shutdown(FAR struct dac_dev_s *dev)
{
#warning "Missing logic"
}
/****************************************************************************
* Name: dac_txint
*
* Description:
* Call to enable or disable TX interrupts.
*
* Input Parameters:
*
* Returned Value:
* None
*
****************************************************************************/
static void dac_txint(FAR struct dac_dev_s *dev, bool enable)
{
FAR struct sam_chan_s *chan;
chan = dev->ad_priv;
if (enable)
{
putreg32(DACC_INT_TXRDY0 << chan->intf, SAM_DACC_IER);
}
else
{
putreg32(DACC_INT_TXRDY0 << chan->intf, SAM_DACC_IDR);
}
}
/****************************************************************************
* Name: dac_send
*
* Description:
* Set the DAC output.
*
* Input Parameters:
*
* Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
static int dac_send(FAR struct dac_dev_s *dev, FAR struct dac_msg_s *msg)
{
FAR struct sam_chan_s *chan = dev->ad_priv;
/* Interrupt based transfer */
putreg16(msg->am_data >> 16, chan->dro);
return OK;
}
/****************************************************************************
* Name: dac_ioctl
*
* Description:
* All ioctl calls will be routed through this method.
*
* Input Parameters:
*
* Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
static int dac_ioctl(FAR struct dac_dev_s *dev, int cmd, unsigned long arg)
{
return -ENOTTY;
}
/****************************************************************************
* Name: dac_timer_init
*
* Description:
* Configure a timer to periodically trigger conversion. Only channels TC0,
* TC1, TC2 can be used with DAC.
*
****************************************************************************/
#ifdef CONFIG_SAMV7_DAC_TRIGGER
static int dac_timer_init(struct sam_dac_s *priv, uint32_t freq_required,
int channel)
{
uint32_t mode;
uint32_t regval;
uint32_t freq_actual;
ainfo("required frequency=%ld [Hz], channel=%d\n",
(long)freq_required, channel);
DEBUGASSERT(priv && (freq_required > 0) && (channel >= 0 && channel <= 2));
/* Set the timer/counter waveform mode the the clock input. Use smallest
* MCK divisor of 8 to have highest clock resolution thus smallest frequency
* error. With 32 bit counter the lowest possible frequency of 1 Hz is easily
* supported.
*/
/* TODO Add support for TC_CMR_TCCLKS_PCK6 to reduce frequency error */
mode = (TC_CMR_TCCLKS_MCK8 | /* Use MCK/8 clock signal */
TC_CMR_WAVSEL_UPRC | /* UP mode w/ trigger on RC Compare */
TC_CMR_WAVE | /* Wave mode */
TC_CMR_ACPA_CLEAR | /* RA Compare Effect on TIOA: Clear */
TC_CMR_ACPC_SET); /* RC Compare Effect on TIOA: Set */
/* Now allocate and configure the channel */
priv->tc = sam_tc_allocate(channel, mode);
if (!priv->tc)
{
aerr("ERROR: Failed to allocate channel %d mode %08x\n", channel, mode);
return -EINVAL;
}
/* Calculate the actual counter value from this divider and the tc input
* frequency.
*/
regval = BOARD_MCK_FREQUENCY / 8 / freq_required;
DEBUGASSERT(regval > 0); /* Will check for integer underflow */
/* Set up TC_RA and TC_RC. The frequency is determined by RA and RC:
* TIOA is cleared on RA match; TIOA is set on RC match.
*/
sam_tc_setregister(priv->tc, TC_REGA, regval >> 1);
sam_tc_setregister(priv->tc, TC_REGC, regval);
freq_actual = BOARD_MCK_FREQUENCY / 8 / regval;
ainfo("configured frequency=%ld [Hz]\n", (long)freq_actual);
/* And start the timer */
sam_tc_start(priv->tc);
return OK;
}
#endif
/****************************************************************************
* Name: dac_timer_free
*
* Description:
* Free the timer resource
*
****************************************************************************/
#ifdef CONFIG_SAMV7_DAC_TRIGGER
static void dac_timer_free(struct sam_dac_s *priv)
{
/* Is a timer allocated? */
ainfo("tc=%p\n", priv->tc);
if (priv->tc)
{
/* Yes.. stop it and free it */
sam_tc_stop(priv->tc);
sam_tc_free(priv->tc);
priv->tc = NULL;
}
}
#endif
/****************************************************************************
* Name: dac_channel_init
*
* Description:
* Initialize the DAC channel.
*
* Input Parameters:
* chan - A reference to the DAC channel state data
*
* Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
static int dac_channel_init(FAR struct sam_chan_s *chan)
{
/* Is the selected channel already in-use? */
if (chan->inuse)
{
/* Yes.. then return EBUSY */
return -EBUSY;
}
#ifdef CONFIG_SAMV7_DAC_TRIGGER
/* Configure trigger mode operation */
ainfo("Enabled trigger mode for DAC%d\n", chan->intf);
modifyreg32(SAM_DACC_TRIGR,
chan->reg_dacc_trigr_clear,
chan->reg_dacc_trigr_set);
#endif
/* Enable DAC Channel */
putreg32(1 << chan->intf, SAM_DACC_CHER);
/* Mark the DAC channel "in-use" */
chan->inuse = 1;
return OK;
}
/****************************************************************************
* Name: dac_module_init
*
* Description:
* Initialize the DAC. All ioctl calls will be routed through this method.
*
* Input Parameters:
*
* Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
static int dac_module_init(void)
{
uint32_t regval;
int ret;
/* Has the DAC block already been initialized? */
if (g_dacmodule.initialized)
{
/* Yes.. then return success We only have to do this once */
return OK;
}
ainfo("Initializing...\n");
/* Disable DAC peripheral clock */
sam_dacc_disableclk();
/* Configure DAC pins */
#ifdef CONFIG_SAMV7_DAC0
sam_configgpio(GPIO_DAC0);
#endif
#ifdef CONFIG_SAMV7_DAC1
sam_configgpio(GPIO_DAC1);
#endif
/* Enable the DAC peripheral clock */
sam_dacc_enableclk();
/* Reset the DAC controller */
putreg32(DACC_CR_SWRST, SAM_DACC_CR);
/* Set the MCK clock prescaler: PRESCAL = (MCK / DACClock) - 2 */
regval = DACC_MR_PRESCALER(CONFIG_SAMV7_DAC_PRESCAL);
putreg32(regval, SAM_DACC_MR);
/* Configure trigger mode operation */
#ifdef CONFIG_SAMV7_DAC_TRIGGER
ret = dac_timer_init(&g_dacmodule,
CONFIG_SAMV7_DAC_TRIGGER_FREQUENCY,
SAMV7_DAC_TC_CHANNEL);
if (ret < 0)
{
aerr("ERROR: Failed to initialize the timer: %d\n", ret);
return ret;
}
#endif
/* Configure interrupts */
ret = irq_attach(SAM_IRQ_DACC, dac_interrupt);
if (ret < 0)
{
aerr("irq_attach failed: %d\n", ret);
return ret;
}
ainfo("Enable the DAC interrupt: irq=%d\n", SAM_IRQ_DACC);
up_enable_irq(SAM_IRQ_DACC);
/* Mark the DAC module as initialized */
g_dacmodule.initialized = 1;
return OK;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: sam_dac_initialize
*
* Description:
* Initialize the DAC.
*
* Input Parameters:
* intf - The DAC interface number.
*
* Returned Value:
* Valid DAC device structure reference on success, NULL on failure.
*
****************************************************************************/
FAR struct dac_dev_s *sam_dac_initialize(int intf)
{
FAR struct dac_dev_s *dev;
FAR struct sam_chan_s *chan;
int ret;
#ifdef CONFIG_SAMV7_DAC0
if (intf == 0)
{
ainfo("DAC1 Selected\n");
dev = &g_dac1dev;
}
else
#endif
#ifdef CONFIG_SAMV7_DAC1
if (intf == 1)
{
ainfo("DAC2 Selected\n");
dev = &g_dac2dev;
}
else
#endif
{
aerr("ERROR: No such DAC interface: %d\n", intf);
errno = ENODEV;
return NULL;
}
/* Initialize the DAC peripheral module */
ret = dac_module_init();
if (ret < 0)
{
aerr("ERROR: Failed to initialize the DAC peripheral module: %d\n", ret);
errno = -ret;
return NULL;
}
/* Configure the selected DAC channel */
chan = dev->ad_priv;
ret = dac_channel_init(chan);
if (ret < 0)
{
aerr("ERROR: Failed to initialize DAC channel %d: %d\n", intf, ret);
errno = -ret;
return NULL;
}
return dev;
}
#endif /* CONFIG_SAMV7_DAC0 || CONFIG_SAMV7_DAC1 */

129
arch/arm/src/samv7/sam_dac.h Normal file
View File

@ -0,0 +1,129 @@
/****************************************************************************
* arch/arm/src/samv7/sam_dac.h
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMV7_SAM_DAC_H
#define __ARCH_ARM_SRC_SAMV7_SAM_DAC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/analog/dac.h>
#include "chip/sam_dacc.h"
#if defined(CONFIG_SAMV7_DAC0) || defined(CONFIG_SAMV7_DAC1)
/****************************************************************************
* Pre-processor definitions
****************************************************************************/
/* Default configuration settings may be overridden in the board configuration
* file.
*/
#if !defined(CONFIG_SAMV7_DAC_DMA_BUFFER_SIZE)
# define CONFIG_SAMV7_DAC_DMA_BUFFER_SIZE 8
#elif CONFIG_SAMV7_DAC_DMA_BUFFER_SIZE > 65535
# warning "CONFIG_SAMV7_DAC_DMA_BUFFER_SIZE value does not fit into uint16_t, limiting it to 65535"
# undef CONFIG_SAMV7_DAC_DMA_BUFFER_SIZE
# define CONFIG_SAMV7_DAC_DMA_BUFFER_SIZE (65535)
#endif
#if !defined(CONFIG_SAMV7_DAC_TRIGGER_FREQUENCY)
# define CONFIG_SAMV7_DAC_TRIGGER_FREQUENCY 8000
#endif
/* PRESCAL = (MCK / DACClock) - 2
*
* Given:
* MCK = 150MHz
* DACClock = 16MHz
* Then:
* PRESCAL = 7
*/
#if !defined(CONFIG_SAMV7_DAC_PRESCAL)
#define CONFIG_SAMV7_DAC_PRESCAL (7)
#elif CONFIG_SAMV7_DAC_PRESCAL > 15
# warning "Maximum valid CONFIG_SAMV7_DAC_PRESCAL value is 15"
#endif
#if !defined(CONFIG_SAMV7_DAC_TRIGGER_SELECT)
#define CONFIG_SAMV7_DAC_TRIGGER_SELECT (3)
#elif CONFIG_SAMV7_DAC_TRIGGER_SELECT < 1 || CONFIG_SAMV7_DAC_TRIGGER_SELECT > 3
# warning "Only CONFIG_SAMV7_DAC_TRIGGER_SELECT == [1-3] is supported"
#endif
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Name: sam_dac_initialize
*
* Description:
* Initialize the DAC
*
* Input Parameters:
* intf - The DAC interface number.
*
* Returned Value:
* Valid DAC device structure reference on success; a NULL on failure
*
****************************************************************************/
struct dac_dev_s;
FAR struct dac_dev_s *sam_dac_initialize(int intf);
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* CONFIG_SAMV7_DAC0 || CONFIG_SAMV7_DAC1 */
#endif /* __ARCH_ARM_SRC_SAMV7_SAM_DAC_H */

4
arch/arm/src/samv7/sam_freerun.c
View File

@ -61,7 +61,7 @@
#include "sam_freerun.h"
#ifdef CONFIG_SAMV7_ONESHOT
#ifdef CONFIG_SAMV7_FREERUN
/****************************************************************************
* Private Functions
@ -319,4 +319,4 @@ int sam_freerun_uninitialize(struct sam_freerun_s *freerun)
return OK;
}
#endif /* CONFIG_SAMV7_ONESHOT */
#endif /* CONFIG_SAMV7_FREERUN */

110
arch/arm/src/samv7/sam_oneshot.c
View File

@ -64,22 +64,6 @@
#ifdef CONFIG_SAMV7_ONESHOT
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
@ -129,7 +113,9 @@ static void sam_oneshot_handler(TC_HANDLE tch, void *arg, uint32_t sr)
oneshot->handler = NULL;
oneshot_arg = (void *)oneshot->arg;
oneshot->arg = NULL;
#ifdef CONFIG_SAMV7_FREERUN
oneshot->start_count = 0;
#endif
oneshot_handler(oneshot_arg);
}
@ -230,7 +216,36 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
oneshot->running = false;
oneshot->handler = NULL;
oneshot->arg = NULL;
#ifdef CONFIG_SAMV7_FREERUN
oneshot->start_count = 0;
#endif
return OK;
}
/****************************************************************************
* Name: sam_oneshot_max_delay
*
* Description:
* Return the maximum delay supported by the one shot timer (in
* microseconds).
*
* Input Parameters:
* oneshot Caller allocated instance of the oneshot state structure. This
* structure must have been previously initialized via a call to
* sam_oneshot_initialize();
* usec The location in which to return the maximum delay.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on failure.
*
****************************************************************************/
int sam_oneshot_max_delay(struct sam_oneshot_s *oneshot, uint64_t *usec)
{
DEBUGASSERT(oneshot != NULL && usec != NULL);
*usec = (0xffffull * USEC_PER_SEC) / (uint64_t)sam_tc_divfreq(oneshot->tch);
return OK;
}
@ -254,8 +269,10 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
*
****************************************************************************/
int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freerun,
oneshot_handler_t handler, void *arg, const struct timespec *ts)
int sam_oneshot_start(struct sam_oneshot_s *oneshot,
struct sam_freerun_s *freerun,
oneshot_handler_t handler, void *arg,
const struct timespec *ts)
{
uint64_t usec;
uint64_t regval;
@ -285,7 +302,8 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
usec = (uint64_t)ts->tv_sec * USEC_PER_SEC + (uint64_t)(ts->tv_nsec / NSEC_PER_USEC);
/* Get the timer counter frequency and determine the number of counts need to achieve the requested delay.
/* Get the timer counter frequency and determine the number of counts
* needed to achieve the requested delay.
*
* frequency = ticks / second
* ticks = seconds * frequency
@ -312,6 +330,7 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
sam_tc_start(oneshot->tch);
#ifdef CONFIG_SAMV7_FREERUN
/* The function sam_tc_start() starts the timer/counter by setting the
* bits TC_CCR_CLKEN and TC_CCR_SWTRG in the channel control register.
* The first one enables the timer/counter the latter performs an
@ -325,12 +344,16 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
* the counter value of the freerun timer/counter is stored at each start
* of the oneshot timer/counter.
*
* The function up_timer_gettime() could also be used for this but it takes
* too long. If up_timer_gettime() is called within this function the problem
* vanishes at least if compiled with no optimisation.
* The function up_timer_gettime() could also be used for this but it
* takes too long. If up_timer_gettime() is called within this function
* the problem vanishes at least if compiled with no optimisation.
*/
oneshot->start_count = sam_tc_getcounter(freerun->tch);
if (freerun != NULL)
{
oneshot->start_count = sam_tc_getcounter(freerun->tch);
}
#endif
/* Enable interrupts. We should get the callback when the interrupt
* occurs.
@ -347,8 +370,8 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
* Description:
* Cancel the oneshot timer and return the time remaining on the timer.
*
* NOTE: This function may execute at a high rate with no timer running (as
* when pre-emption is enabled and disabled).
* NOTE: This function may execute at a high rate with no timer running
* (as when pre-emption is enabled and disabled).
*
* Input Parameters:
* oneshot Caller allocated instance of the oneshot state structure. This
@ -366,8 +389,8 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
*
****************************************************************************/
int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freerun,
struct timespec *ts)
int sam_oneshot_cancel(struct sam_oneshot_s *oneshot,
struct sam_freerun_s *freerun, struct timespec *ts)
{
irqstate_t flags;
uint64_t usec;
@ -408,16 +431,19 @@ int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *free
count = sam_tc_getcounter(oneshot->tch);
rc = sam_tc_getregister(oneshot->tch, TC_REGC);
#ifdef CONFIG_SAMV7_FREERUN
/* In the case the timer/counter was canceled very short after its start,
* the counter register can hold the wrong value (the value of the last
* run). To prevent this the counter value is set to zero if not at
* least on tick passed since the start of the timer/counter.
*/
if (count > 0 && sam_tc_getcounter(freerun->tch) == oneshot->start_count)
if (count > 0 && freerun != NULL &&
sam_tc_getcounter(freerun->tch) == oneshot->start_count)
{
count = 0;
}
#endif
/* Now we can disable the interrupt and stop the timer. */
@ -491,32 +517,4 @@ int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *free
return OK;
}
/****************************************************************************
* Name: sam_oneshot_max_delay
*
* Description:
* Return the maximum delay supported by the one shot timer (in
* microseconds).
*
* Input Parameters:
* oneshot Caller allocated instance of the oneshot state structure. This
* structure must have been previously initialized via a call to
* sam_oneshot_initialize();
* usec The location in which to return the maximum delay.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on failure.
*
****************************************************************************/
#ifdef CONFIG_SCHED_TICKLESS_LIMIT_MAX_SLEEP
int sam_oneshot_max_delay(struct sam_oneshot_s *oneshot, uint64_t *usec)
{
DEBUGASSERT(oneshot && usec);
*usec = (0xffffull * USEC_PER_SEC) / (uint64_t)sam_tc_divfreq(oneshot->tch);
return OK;
}
#endif
#endif /* CONFIG_SAMV7_ONESHOT */

23
arch/arm/src/samv7/sam_oneshot.h
View File

@ -46,7 +46,6 @@
#include <time.h>
#include "sam_tc.h"
#include "sam_freerun.h"
#ifdef CONFIG_SAMV7_ONESHOT
@ -83,11 +82,13 @@ struct sam_oneshot_s
volatile oneshot_handler_t handler; /* Oneshot expiration callback */
volatile void *arg; /* The argument that will accompany
* the callback */
#ifdef CONFIG_SAMV7_FREERUN
volatile uint32_t start_count; /* Stores the value of the freerun counter,
* at each start of the onshot timer. Is neccesary
* to find out if the onshot counter was updated
* correctly at the time of the call to
* sam_oneshot_cancel or not. */
#endif
};
/****************************************************************************
@ -149,9 +150,7 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
*
****************************************************************************/
#ifdef CONFIG_SCHED_TICKLESS_LIMIT_MAX_SLEEP
int sam_oneshot_max_delay(struct sam_oneshot_s *oneshot, uint64_t *usec);
#endif
/****************************************************************************
* Name: sam_oneshot_start
@ -165,7 +164,8 @@ int sam_oneshot_max_delay(struct sam_oneshot_s *oneshot, uint64_t *usec);
* sam_oneshot_initialize();
* freerun Caller allocated instance of the freerun state structure. This
* structure must have been previously initialized via a call to
* sam_freerun_initialize();
* sam_freerun_initialize(). May be NULL if there is no matching
* free-running timer.
* handler The function to call when when the oneshot timer expires.
* arg An opaque argument that will accompany the callback.
* ts Provides the duration of the one shot timer.
@ -176,8 +176,11 @@ int sam_oneshot_max_delay(struct sam_oneshot_s *oneshot, uint64_t *usec);
*
****************************************************************************/
int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freerun,
oneshot_handler_t handler, void *arg, const struct timespec *ts);
struct sam_freerun_s;
int sam_oneshot_start(struct sam_oneshot_s *oneshot,
struct sam_freerun_s *freerun,
oneshot_handler_t handler, void *arg,
const struct timespec *ts);
/****************************************************************************
* Name: sam_oneshot_cancel
@ -194,7 +197,8 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
* sam_oneshot_initialize();
* freerun Caller allocated instance of the freerun state structure. This
* structure must have been previously initialized via a call to
* sam_freerun_initialize();
* sam_freerun_initialize(). May be NULL if there is no matching
* free-running timer.
* ts The location in which to return the time remaining on the
* oneshot timer. A time of zero is returned if the timer is
* not running.
@ -206,8 +210,9 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
*
****************************************************************************/
int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freerun,
struct timespec *ts);
struct sam_freerun_s;
int sam_oneshot_cancel(struct sam_oneshot_s *oneshot,
struct sam_freerun_s *freerun, struct timespec *ts);
#undef EXTERN
#ifdef __cplusplus

345
arch/arm/src/samv7/sam_oneshot_lowerhalf.c Normal file
View File

@ -0,0 +1,345 @@
/****************************************************************************
* arch/arm/src/sam/sam_oneshot_lowerhalf.c
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <time.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/kmalloc.h>
#include <nuttx/timers/oneshot.h>
#include "sam_oneshot.h"
/****************************************************************************
* Private Types
****************************************************************************/
/* This structure describes the state of the oneshot timer lower-half driver */
struct sam_oneshot_lowerhalf_s
{
/* This is the part of the lower half driver that is visible to the upper-
* half client of the driver. This must be the first thing in this
* structure so that pointers to struct oneshot_lowerhalf_s are cast
* compatible to struct sam_oneshot_lowerhalf_s and vice versa.
*/
struct oneshot_lowerhalf_s lh; /* Common lower-half driver fields */
/* Private lower half data follows */
struct sam_oneshot_s oneshot; /* SAMV7-specific oneshot state */
oneshot_callback_t callback; /* internal handler that receives callback */
FAR void *arg; /* Argument that is passed to the handler */
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
static void sam_oneshot_handler(void *arg);
static int sam_max_delay(FAR struct oneshot_lowerhalf_s *lower,
FAR struct timespec *ts);
static int sam_start(FAR struct oneshot_lowerhalf_s *lower,
oneshot_callback_t callback, FAR void *arg,
FAR const struct timespec *ts);
static int sam_cancel(FAR struct oneshot_lowerhalf_s *lower,
FAR struct timespec *ts);
/****************************************************************************
* Private Data
****************************************************************************/
/* Lower half operations */
static const struct oneshot_operations_s g_oneshot_ops =
{
.max_delay = sam_max_delay,
.start = sam_start,
.cancel = sam_cancel,
};
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: sam_oneshot_handler
*
* Description:
* Timer expiration handler
*
* Input Parameters:
* arg - Should be the same argument provided when sam_oneshot_start()
* was called.
*
* Returned Value:
* None
*
****************************************************************************/
static void sam_oneshot_handler(void *arg)
{
FAR struct sam_oneshot_lowerhalf_s *priv =
(FAR struct sam_oneshot_lowerhalf_s *)arg;
oneshot_callback_t callback;
FAR void *cbarg;
DEBUGASSERT(priv != NULL);
/* Perhaps the callback was nullified in a race condition with
* sam_cancel?
*/
if (priv->callback)
{
/* Sample and nullify BEFORE executing callback (in case the callback
* restarts the oneshot).
*/
callback = priv->callback;
cbarg = priv->arg;
priv->callback = NULL;
priv->arg = NULL;
/* Then perform the callback */
callback(&priv->lh, cbarg);
}
}
/****************************************************************************
* Name: sam_max_delay
*
* Description:
* Determine the maximum delay of the one-shot timer (in microseconds)
*
* Input Parameters:
* lower An instance of the lower-half oneshot state structure. This
* structure must have been previously initialized via a call to
* oneshot_initialize();
* ts The location in which to return the maxumum delay.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on failure.
*
****************************************************************************/
static int sam_max_delay(FAR struct oneshot_lowerhalf_s *lower,
FAR struct timespec *ts)
{
FAR struct sam_oneshot_lowerhalf_s *priv =
(FAR struct sam_oneshot_lowerhalf_s *)lower;
uint64_t usecs;
int ret;
DEBUGASSERT(priv != NULL && ts != NULL);
ret = sam_oneshot_max_delay(&priv->oneshot, &usecs);
if (ret >= 0)
{
uint64_t sec = usecs / 1000000;
usecs -= 1000000 * sec;
ts->tv_sec = (time_t)sec;
ts->tv_nsec = (long)(usecs * 1000);
}
return ret;
}
/****************************************************************************
* Name: sam_start
*
* Description:
* Start the oneshot timer
*
* Input Parameters:
* lower An instance of the lower-half oneshot state structure. This
* structure must have been previously initialized via a call to
* oneshot_initialize();
* handler The function to call when when the oneshot timer expires.
* arg An opaque argument that will accompany the callback.
* ts Provides the duration of the one shot timer.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on failure.
*
****************************************************************************/
static int sam_start(FAR struct oneshot_lowerhalf_s *lower,
oneshot_callback_t callback, FAR void *arg,
FAR const struct timespec *ts)
{
FAR struct sam_oneshot_lowerhalf_s *priv =
(FAR struct sam_oneshot_lowerhalf_s *)lower;
irqstate_t flags;
int ret;
DEBUGASSERT(priv != NULL && callback != NULL && ts != NULL);
/* Save the callback information and start the timer */
flags = enter_critical_section();
priv->callback = callback;
priv->arg = arg;
ret = sam_oneshot_start(&priv->oneshot, NULL,
sam_oneshot_handler, priv, ts);
leave_critical_section(flags);
if (ret < 0)
{
tmrerr("ERROR: sam_oneshot_start failed: %d\n", flags);
}
return ret;
}
/****************************************************************************
* Name: sam_cancel
*
* Description:
* Cancel the oneshot timer and return the time remaining on the timer.
*
* NOTE: This function may execute at a high rate with no timer running (as
* when pre-emption is enabled and disabled).
*
* Input Parameters:
* lower Caller allocated instance of the oneshot state structure. This
* structure must have been previously initialized via a call to
* oneshot_initialize();
* ts The location in which to return the time remaining on the
* oneshot timer. A time of zero is returned if the timer is
* not running.
*
* Returned Value:
* Zero (OK) is returned on success. A call to up_timer_cancel() when
* the timer is not active should also return success; a negated errno
* value is returned on any failure.
*
****************************************************************************/
static int sam_cancel(FAR struct oneshot_lowerhalf_s *lower,
FAR struct timespec *ts)
{
FAR struct sam_oneshot_lowerhalf_s *priv =
(FAR struct sam_oneshot_lowerhalf_s *)lower;
irqstate_t flags;
int ret;
DEBUGASSERT(priv != NULL);
/* Cancel the timer */
flags = enter_critical_section();
ret = sam_oneshot_cancel(&priv->oneshot, NULL, ts);
priv->callback = NULL;
priv->arg = NULL;
leave_critical_section(flags);
if (ret < 0)
{
tmrerr("ERROR: sam_oneshot_cancel failed: %d\n", flags);
}
return ret;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: oneshot_initialize
*
* Description:
* Initialize the oneshot timer and return a oneshot lower half driver
* instance.
*
* Input Parameters:
* chan Timer counter channel to be used.
* resolution The required resolution of the timer in units of
* microseconds. NOTE that the range is restricted to the
* range of uint16_t (excluding zero).
*
* Returned Value:
* On success, a non-NULL instance of the oneshot lower-half driver is
* returned. NULL is return on any failure.
*
****************************************************************************/
FAR struct oneshot_lowerhalf_s *oneshot_initialize(int chan,
uint16_t resolution)
{
FAR struct sam_oneshot_lowerhalf_s *priv;
int ret;
/* Allocate an instance of the lower half driver */
priv = (FAR struct sam_oneshot_lowerhalf_s *)
kmm_zalloc(sizeof(struct sam_oneshot_lowerhalf_s));
if (priv == NULL)
{
tmrerr("ERROR: Failed to initialized state structure\n");
return NULL;
}
/* Initialize the lower-half driver structure */
priv->lh.ops = &g_oneshot_ops;
/* Initialize the contained SAM oneshot timer */
ret = sam_oneshot_initialize(&priv->oneshot, chan, resolution);
if (ret < 0)
{
tmrerr("ERROR: sam_oneshot_initialize failed: %d\n", ret);
kmm_free(priv);
return NULL;
}
return &priv->lh;
}

6
arch/arm/src/samv7/sam_spi.c
View File

@ -1221,6 +1221,7 @@ static int spi_setdelay(struct spi_dev_s *dev, uint32_t startdelay,
#ifdef CONFIG_SPI_HWFEATURES
static int spi_hwfeatures(struct spi_dev_s *dev, uint8_t features)
{
#ifdef CONFIG_SPI_CS_CONTROL
struct sam_spics_s *spics = (struct sam_spics_s *)dev;
struct sam_spidev_s *spi = spi_device(spics);
uint32_t regval;
@ -1280,7 +1281,10 @@ static int spi_hwfeatures(struct spi_dev_s *dev, uint8_t features)
spi->escape_lastxfer = false;
}
return 0;
return ((features & ~HWFEAT_FORCE_CS_CONTROL_MASK) == 0) ? OK : -ENOSYS;
#else
return -ENOSYS;
#endif
}
#endif

4
arch/arm/src/stm32/Kconfig
View File

@ -1398,6 +1398,8 @@ config STM32_STM32F37XX
select STM32_HAVE_DAC1
select STM32_HAVE_DAC2
select STM32_HAVE_I2C2
select STM32_HAVE_SPI2
select STM32_HAVE_SPI3
select STM32_HAVE_USART3
config STM32_STM32F40XX
@ -2074,7 +2076,7 @@ config STM32_SPI6
config STM32_SYSCFG
bool "SYSCFG"
default y
depends on STM32_STM32L15XX || STM32_STM32F30XX || STM32_STM32F37XX || STM32_STM32F207 || STM32_STM32F40XX
depends on STM32_STM32L15XX || STM32_STM32F30XX || STM32_STM32F37XX || STM32_STM32F207 || STM32_STM32F40XX || STM32_CONNECTIVITYLINE
config STM32_TIM1
bool "TIM1"

4
arch/arm/src/stm32/Make.defs
View File

@ -1,7 +1,7 @@
############################################################################
# arch/arm/src/stm32/Make.defs
#
# Copyright (C) 2009, 2011-2015 Gregory Nutt. All rights reserved.
# Copyright (C) 2009, 2011-2016 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <gnutt@nuttx.org>
#
# Redistribution and use in source and binary forms, with or without
@ -125,7 +125,7 @@ CHIP_CSRCS += stm32_tickless.c
endif
ifeq ($(CONFIG_STM32_ONESHOT),y)
CHIP_CSRCS += stm32_oneshot.c
CHIP_CSRCS += stm32_oneshot.c stm32_oneshot_lowerhalf.c
endif
ifeq ($(CONFIG_STM32_FREERUN),y)

2
arch/arm/src/stm32/chip/stm32_otghs.h
View File

@ -59,8 +59,6 @@
#define OTGHS_PID_MDATA (3) /* Non-control */
#define OTGHS_PID_SETUP (3) /* Control */
/* If OTGHS2 is defined (FS mode of the HS module), then remap the OTGHS base address */
/* Register Offsets *********************************************************************************/
/* Core global control and status registers */

84
arch/arm/src/stm32/chip/stm32_spi.h
View File

@ -66,7 +66,7 @@
#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32F40XX)
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX)
# define STM32_SPI_I2SCFGR_OFFSET 0x001c /* I2S configuration register */
# define STM32_SPI_I2SPR_OFFSET 0x0020 /* I2S prescaler register */
#endif
@ -92,7 +92,7 @@
# define STM32_SPI2_RXCRCR (STM32_SPI2_BASE+STM32_SPI_RXCRCR_OFFSET)
# define STM32_SPI2_TXCRCR (STM32_SPI2_BASE+STM32_SPI_TXCRCR_OFFSET)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32F40XX)
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX)
# define STM32_SPI2_I2SCFGR (STM32_SPI2_BASE+STM32_SPI_I2SCFGR_OFFSET)
# define STM32_SPI2_I2SPR (STM32_SPI2_BASE+STM32_SPI_I2SPR_OFFSET)
# endif
@ -107,7 +107,7 @@
# define STM32_SPI3_RXCRCR (STM32_SPI3_BASE+STM32_SPI_RXCRCR_OFFSET)
# define STM32_SPI3_TXCRCR (STM32_SPI3_BASE+STM32_SPI_TXCRCR_OFFSET)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32F40XX)
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX)
# define STM32_SPI3_I2SCFGR (STM32_SPI3_BASE+STM32_SPI_I2SCFGR_OFFSET)
# define STM32_SPI3_I2SPR (STM32_SPI3_BASE+STM32_SPI_I2SPR_OFFSET)
# endif
@ -135,7 +135,11 @@
#define SPI_CR1_SSI (1 << 8) /* Bit 8: Internal slave select */
#define SPI_CR1_SSM (1 << 9) /* Bit 9: Software slave management */
#define SPI_CR1_RXONLY (1 << 10) /* Bit 10: Receive only */
#define SPI_CR1_DFF (1 << 11) /* Bit 11: Data Frame Format */
#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
# define SPI_CR1_CRCL (1 << 11) /* Bit 11: CRC length */
#else
# define SPI_CR1_DFF (1 << 11) /* Bit 11: Data Frame Format */
#endif
#define SPI_CR1_CRCNEXT (1 << 12) /* Bit 12: Transmit CRC next */
#define SPI_CR1_CRCEN (1 << 13) /* Bit 13: Hardware CRC calculation enable */
#define SPI_CR1_BIDIOE (1 << 14) /* Bit 14: Output enable in bidirectional mode */
@ -148,7 +152,7 @@
#define SPI_CR2_SSOE (1 << 2) /* Bit 2: SS Output Enable */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32F40XX)
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX)
# define SPI_CR2_FRF (1 << 4) /* Bit 4: Frame format */
#endif
@ -156,22 +160,23 @@
#define SPI_CR2_RXNEIE (1 << 6) /* Bit 6: RX buffer not empty interrupt enable */
#define SPI_CR2_TXEIE (1 << 7) /* Bit 7: Tx buffer empty interrupt enable */
#ifdef CONFIG_STM32_STM32F30XX
#define SPI_CR1_DS_SHIFT (8) /* Bits 8-11: Data size */
#define SPI_CR1_DS_MASK (15 << SPI_CR1_DS_SHIFT)
# define SPI_CR1_DS_4BIT (3 << SPI_CR1_DS_SHIFT)
# define SPI_CR1_DS_5BIT (4 << SPI_CR1_DS_SHIFT)
# define SPI_CR1_DS_6BIT (5 << SPI_CR1_DS_SHIFT)
# define SPI_CR1_DS_7BIT (6 << SPI_CR1_DS_SHIFT)
# define SPI_CR1_DS_8BIT (7 << SPI_CR1_DS_SHIFT)
# define SPI_CR1_DS_9BIT (8 << SPI_CR1_DS_SHIFT)
# define SPI_CR1_DS_10BIT (9 << SPI_CR1_DS_SHIFT)
# define SPI_CR1_DS_11BIT (10 << SPI_CR1_DS_SHIFT)
# define SPI_CR1_DS_12BIT (11 << SPI_CR1_DS_SHIFT)
# define SPI_CR1_DS_13BIT (12 << SPI_CR1_DS_SHIFT)
# define SPI_CR1_DS_14BIT (13 << SPI_CR1_DS_SHIFT)
# define SPI_CR1_DS_15BIT (14 << SPI_CR1_DS_SHIFT)
# define SPI_CR1_DS_16BIT (15 << SPI_CR1_DS_SHIFT)
#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
#define SPI_CR2_DS_SHIFT (8) /* Bits 8-11: Data size */
#define SPI_CR2_DS_MASK (15 << SPI_CR2_DS_SHIFT)
# define SPI_CR2_DS(n) ((uint32_t)((n) - 1) << SPI_CR2_DS_SHIFT)
# define SPI_CR2_DS_4BIT (3 << SPI_CR2_DS_SHIFT)
# define SPI_CR2_DS_5BIT (4 << SPI_CR2_DS_SHIFT)
# define SPI_CR2_DS_6BIT (5 << SPI_CR2_DS_SHIFT)
# define SPI_CR2_DS_7BIT (6 << SPI_CR2_DS_SHIFT)
# define SPI_CR2_DS_8BIT (7 << SPI_CR2_DS_SHIFT)
# define SPI_CR2_DS_9BIT (8 << SPI_CR2_DS_SHIFT)
# define SPI_CR2_DS_10BIT (9 << SPI_CR2_DS_SHIFT)
# define SPI_CR2_DS_11BIT (10 << SPI_CR2_DS_SHIFT)
# define SPI_CR2_DS_12BIT (11 << SPI_CR2_DS_SHIFT)
# define SPI_CR2_DS_13BIT (12 << SPI_CR2_DS_SHIFT)
# define SPI_CR2_DS_14BIT (13 << SPI_CR2_DS_SHIFT)
# define SPI_CR2_DS_15BIT (14 << SPI_CR2_DS_SHIFT)
# define SPI_CR2_DS_16BIT (15 << SPI_CR2_DS_SHIFT)
#define SPI_CR2_FRXTH (1 << 12) /* Bit 12: FIFO reception threshold */
#define SPI_CR2_LDMARX (1 << 13) /* Bit 13: Last DMA transfer for receptione */
#define SPI_CR2_LDMATX (1 << 14) /* Bit 14: Last DMA transfer for transmission */
@ -183,7 +188,7 @@
#define SPI_SR_TXE (1 << 1) /* Bit 1: Transmit buffer empty */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32F40XX)
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX)
# define SPI_SR_CHSIDE (1 << 2) /* Bit 2: Channel side */
# define SPI_SR_UDR (1 << 3) /* Bit 3: Underrun flag */
#endif
@ -194,29 +199,29 @@
#define SPI_SR_BSY (1 << 7) /* Bit 7: Busy flag */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32F40XX)
# define SPI_SR_TIFRFE (1 << 8) /* Bit 8: TI frame format error */
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX)
# define SPI_SR_FRE (1 << 8) /* Bit 8: TI frame format error */
#endif
#ifdef CONFIG_STM32_STM32F30XX
#define SPI_CR1_FRLVL_SHIFT (9) /* Bits 9-10: FIFO reception level */
#define SPI_CR1_FRLVL_MASK (3 << SPI_CR1_FRLVL_SHIFT)
# define SPI_CR1_FRLVL_EMPTY (0 << SPI_CR1_FRLVL_SHIFT) /* FIFO empty */
# define SPI_CR1_FRLVL_QUARTER (1 << SPI_CR1_FRLVL_SHIFT) /* 1/4 FIFO */
# define SPI_CR1_FRLVL_HALF (2 << SPI_CR1_FRLVL_SHIFT) /* 1/2 FIFO */
# define SPI_CR1_FRLVL_FULL (3 << SPI_CR1_FRLVL_SHIFT) /* FIFO full */
#define SPI_CR1_FTLVL_SHIFT (11) /* Bits 11-12: FIFO transmission level */
#define SPI_CR1_FTLVL_MASK (3 << SPI_CR1_FTLVL_SHIFT)
# define SPI_CR1_FTLVL_EMPTY (0 << SPI_CR1_FTLVL_SHIFT) /* FIFO empty */
# define SPI_CR1_FTLVL_QUARTER (1 << SPI_CR1_FTLVL_SHIFT) /* 1/4 FIFO */
# define SPI_CR1_FTLVL_HALF (2 << SPI_CR1_FTLVL_SHIFT) /* 1/2 FIFO */
# define SPI_CR1_FTLVL_FULL (3 << SPI_CR1_FTLVL_SHIFT) /* FIFO full */
#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
#define SPI_SR_FRLVL_SHIFT (9) /* Bits 9-10: FIFO reception level */
#define SPI_SR_FRLVL_MASK (3 << SPI_SR_FRLVL_SHIFT)
# define SPI_SR_FRLVL_EMPTY (0 << SPI_SR_FRLVL_SHIFT) /* FIFO empty */
# define SPI_SR_FRLVL_QUARTER (1 << SPI_SR_FRLVL_SHIFT) /* 1/4 FIFO */
# define SPI_SR_FRLVL_HALF (2 << SPI_SR_FRLVL_SHIFT) /* 1/2 FIFO */
# define SPI_SR_FRLVL_FULL (3 << SPI_SR_FRLVL_SHIFT) /* FIFO full */
#define SPI_SR_FTLVL_SHIFT (11) /* Bits 11-12: FIFO transmission level */
#define SPI_SR_FTLVL_MASK (3 << SPI_SR_FTLVL_SHIFT)
# define SPI_SR_FTLVL_EMPTY (0 << SPI_SR_FTLVL_SHIFT) /* FIFO empty */
# define SPI_SR_FTLVL_QUARTER (1 << SPI_SR_FTLVL_SHIFT) /* 1/4 FIFO */
# define SPI_SR_FTLVL_HALF (2 << SPI_SR_FTLVL_SHIFT) /* 1/2 FIFO */
# define SPI_SR_FTLVL_FULL (3 << SPI_SR_FTLVL_SHIFT) /* FIFO full */
#endif
/* I2S configuration register */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32F40XX)
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX)
# define SPI_I2SCFGR_CHLEN (1 << 0) /* Bit 0: Channel length (number of bits per audio channel) */
# define SPI_I2SCFGR_DATLEN_SHIFT (1) /* Bit 1-2: Data length to be transferred */
# define SPI_I2SCFGR_DATLEN_MASK (3 << SPI_I2SCFGR_DATLEN_SHIFT)
@ -244,7 +249,7 @@
/* I2S prescaler register */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32F40XX)
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX)
# define SPI_I2SPR_I2SDIV_SHIFT (0) /* Bit 0-7: I2S Linear prescaler */
# define SPI_I2SPR_I2SDIV_MASK (0xff << SPI_I2SPR_I2SDIV_SHIFT)
# define SPI_I2SPR_ODD (1 << 8) /* Bit 8: Odd factor for the prescaler */
@ -252,4 +257,3 @@
#endif
#endif /* __ARCH_ARM_STC_STM32_CHIP_STM32_SPI_H */

29
arch/arm/src/stm32/chip/stm32f10xxx_rcc.h
View File

@ -148,26 +148,37 @@
#define RCC_CFGR_PLLXTPRE (1 << 17) /* Bit 17: HSE divider for PLL entry */
#define RCC_CFGR_PLLMUL_SHIFT (18) /* Bits 21-18: PLL Multiplication Factor */
#define RCC_CFGR_PLLMUL_MASK (0x0f << RCC_CFGR_PLLMUL_SHIFT)
# define RCC_CFGR_PLLMUL_CLKx2 (0 << RCC_CFGR_PLLMUL_SHIFT) /* 0000: PLL input clock x 2 */
# define RCC_CFGR_PLLMUL_CLKx3 (1 << RCC_CFGR_PLLMUL_SHIFT) /* 0001: PLL input clock x 3 */
#ifndef CONFIG_STM32_CONNECTIVITYLINE
# define RCC_CFGR_PLLMUL_CLKx2 (0 << RCC_CFGR_PLLMUL_SHIFT) /* 0000: PLL input clock x 2 */
# define RCC_CFGR_PLLMUL_CLKx3 (1 << RCC_CFGR_PLLMUL_SHIFT) /* 0001: PLL input clock x 3 */
#endif
# define RCC_CFGR_PLLMUL_CLKx4 (2 << RCC_CFGR_PLLMUL_SHIFT) /* 0010: PLL input clock x 4 */
# define RCC_CFGR_PLLMUL_CLKx5 (3 << RCC_CFGR_PLLMUL_SHIFT) /* 0011: PLL input clock x 5 */
# define RCC_CFGR_PLLMUL_CLKx6 (4 << RCC_CFGR_PLLMUL_SHIFT) /* 0100: PLL input clock x 6 */
# define RCC_CFGR_PLLMUL_CLKx7 (5 << RCC_CFGR_PLLMUL_SHIFT) /* 0101: PLL input clock x 7 */
# define RCC_CFGR_PLLMUL_CLKx8 (6 << RCC_CFGR_PLLMUL_SHIFT) /* 0110: PLL input clock x 8 */
# define RCC_CFGR_PLLMUL_CLKx9 (7 << RCC_CFGR_PLLMUL_SHIFT) /* 0111: PLL input clock x 9 */
# define RCC_CFGR_PLLMUL_CLKx10 (8 << RCC_CFGR_PLLMUL_SHIFT) /* 1000: PLL input clock x 10 */
# define RCC_CFGR_PLLMUL_CLKx11 (9 << RCC_CFGR_PLLMUL_SHIFT) /* 1001: PLL input clock x 11 */
# define RCC_CFGR_PLLMUL_CLKx12 (10 << RCC_CFGR_PLLMUL_SHIFT) /* 1010: PLL input clock x 12 */
# define RCC_CFGR_PLLMUL_CLKx13 (11 << RCC_CFGR_PLLMUL_SHIFT) /* 1011: PLL input clock x 13 */
# define RCC_CFGR_PLLMUL_CLKx14 (12 << RCC_CFGR_PLLMUL_SHIFT) /* 1100: PLL input clock x 14 */
# define RCC_CFGR_PLLMUL_CLKx15 (13 << RCC_CFGR_PLLMUL_SHIFT) /* 1101: PLL input clock x 15 */
# define RCC_CFGR_PLLMUL_CLKx16 (14 << RCC_CFGR_PLLMUL_SHIFT) /* 111x: PLL input clock x 16 */
#ifndef CONFIG_STM32_CONNECTIVITYLINE
# define RCC_CFGR_PLLMUL_CLKx10 (8 << RCC_CFGR_PLLMUL_SHIFT) /* 1000: PLL input clock x 10 */
# define RCC_CFGR_PLLMUL_CLKx11 (9 << RCC_CFGR_PLLMUL_SHIFT) /* 1001: PLL input clock x 11 */
# define RCC_CFGR_PLLMUL_CLKx12 (10 << RCC_CFGR_PLLMUL_SHIFT) /* 1010: PLL input clock x 12 */
# define RCC_CFGR_PLLMUL_CLKx13 (11 << RCC_CFGR_PLLMUL_SHIFT) /* 1011: PLL input clock x 13 */
# define RCC_CFGR_PLLMUL_CLKx14 (12 << RCC_CFGR_PLLMUL_SHIFT) /* 1100: PLL input clock x 14 */
# define RCC_CFGR_PLLMUL_CLKx15 (13 << RCC_CFGR_PLLMUL_SHIFT) /* 1101: PLL input clock x 15 */
# define RCC_CFGR_PLLMUL_CLKx16 (14 << RCC_CFGR_PLLMUL_SHIFT) /* 111x: PLL input clock x 16 */
#else
# define RCC_CFGR_PLLMUL_CLKx65 (13 << RCC_CFGR_PLLMUL_SHIFT) /* 1011: PLL input clock x 6.5 */
#endif
#ifndef CONFIG_STM32_VALUELINE
# define RCC_CFGR_USBPRE (1 << 22) /* Bit 22: USB FS prescaler */
# define RCC_CFGR_USBPREd0 (0) /* PLLCLK / 1 */
# define RCC_CFGR_USBPREd15 (1) /* PLLCLK / 1.5 */
#endif
#ifdef CONFIG_STM32_CONNECTIVITYLINE
# define RCC_CFGR_OTGFSPRE (1 << 22) /* Bit 22: OTG FS prescaler */
# define RCC_CFGR_OTGFSPREd2 (1) /* PLL_VCO (2x PLLCLK) / 2 */
# define RCC_CFGR_OTGFSPREd3 (0) /* PLL_VCO (3x PLLCLK) / 3 */
#endif
#define RCC_CFGR_MCO_SHIFT (24) /* Bits 27-24: Microcontroller Clock Output */
#define RCC_CFGR_MCO_MASK (15 << RCC_CFGR_MCO_SHIFT)

2
arch/arm/src/stm32/chip/stm32f37xxx_syscfg.h
View File

@ -113,7 +113,7 @@
#define SYSCFG_EXTICR_PORTC (2) /* 0010: PC[x] pin */
#define SYSCFG_EXTICR_PORTD (3) /* 0011: PD[x] pin */
#define SYSCFG_EXTICR_PORTE (4) /* 0100: Reserved */
#define SYSCFG_EXTICR_PORTE (5) /* 0101: PF[x] pin */
#define SYSCFG_EXTICR_PORTF (5) /* 0101: PF[x] pin */
#define SYSCFG_EXTICR_PORT_MASK (15)
#define SYSCFG_EXTICR_EXTI_SHIFT(g) (((g) & 3) << 2)

5
arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h
View File

@ -413,10 +413,11 @@
#define GPIO_I2C2_SMBA_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN12)
#define GPIO_I2C2_SMBA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN2)
#define GPIO_I2C2_SMBA_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN6)
#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F411)
# define GPIO_I2C2_SDA_4 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN3)
#if defined(CONFIG_STM32_STM32F411)
# define GPIO_I2C2_SDA_4 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN3)
#endif
#if defined(CONFIG_STM32_STM32F446)
# define GPIO_I2C2_SDA_4 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN3)
# define GPIO_I2C2_SDA_5 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN12)
#endif

71
arch/arm/src/stm32/chip/stm32fxxxxx_otgfs.h
View File

@ -1,10 +1,11 @@
/****************************************************************************************************
* arch/arm/src/stm32/chip/stm32fxxxxx_otgfs.h
*
* Copyright (C) 2012, 2014-2015 Gregory Nutt. All rights reserved.
* Copyright (C) 2012, 2014-2016 Gregory Nutt. All rights reserved.
* Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Paul Alexander Patience <paul-a.patience@polymtl.ca>
* Authors: Gregory Nutt <gnutt@nuttx.org>
* Paul Alexander Patience <paul-a.patience@polymtl.ca>
* David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -470,44 +471,38 @@
/* Core interrupt and Interrupt mask registers */
#define OTGFS_GINTSTS_CMOD (1 << 0) /* Bit 0: Current mode of operation */
#define OTGFS_GINTSTS_CMOD (1 << 0) /* Bit 0: ro Current mode of operation */
# define OTGFS_GINTSTS_DEVMODE (0)
# define OTGFS_GINTSTS_HOSTMODE (OTGFS_GINTSTS_CMOD)
#define OTGFS_GINT_MMIS (1 << 1) /* Bit 1: Mode mismatch interrupt */
#define OTGFS_GINT_OTG (1 << 2) /* Bit 2: OTG interrupt */
#define OTGFS_GINT_SOF (1 << 3) /* Bit 3: Start of frame */
#define OTGFS_GINT_RXFLVL (1 << 4) /* Bit 4: RxFIFO non-empty */
#define OTGFS_GINT_NPTXFE (1 << 5) /* Bit 5: Non-periodic TxFIFO empty */
#define OTGFS_GINT_GINAKEFF (1 << 6) /* Bit 6: Global IN non-periodic NAK effective */
#define OTGFS_GINT_MMIS (1 << 1) /* Bit 1: rc_w1 Mode mismatch interrupt */
#define OTGFS_GINT_OTG (1 << 2) /* Bit 2: ro OTG interrupt */
#define OTGFS_GINT_SOF (1 << 3) /* Bit 3: rc_w1 Start of frame */
#define OTGFS_GINT_RXFLVL (1 << 4) /* Bit 4: ro RxFIFO non-empty */
#define OTGFS_GINT_NPTXFE (1 << 5) /* Bit 5: ro Non-periodic TxFIFO empty */
#define OTGFS_GINT_GINAKEFF (1 << 6) /* Bit 6: ro Global IN non-periodic NAK effective */
#define OTGFS_GINT_GONAKEFF (1 << 7) /* Bit 7: Global OUT NAK effective */
/* Bits 8-9: Reserved, must be kept at reset value */
#define OTGFS_GINT_ESUSP (1 << 10) /* Bit 10: Early suspend */
#define OTGFS_GINT_USBSUSP (1 << 11) /* Bit 11: USB suspend */
#define OTGFS_GINT_USBRST (1 << 12) /* Bit 12: USB reset */
#define OTGFS_GINT_ENUMDNE (1 << 13) /* Bit 13: Enumeration done */
#define OTGFS_GINT_ISOODRP (1 << 14) /* Bit 14: Isochronous OUT packet dropped interrupt */
#define OTGFS_GINT_EOPF (1 << 15) /* Bit 15: End of periodic frame interrupt */
/* Bits 16 Reserved, must be kept at reset value */
#define OTGFS_GINTMSK_EPMISM (1 << 17) /* Bit 17: Endpoint mismatch interrupt mask */
#define OTGFS_GINT_IEP (1 << 18) /* Bit 18: IN endpoint interrupt */
#define OTGFS_GINT_OEP (1 << 19) /* Bit 19: OUT endpoint interrupt */
#define OTGFS_GINT_IISOIXFR (1 << 20) /* Bit 20: Incomplete isochronous IN transfer */
#define OTGFS_GINT_IISOOXFR (1 << 21) /* Bit 21: Incomplete isochronous OUT transfer (device) */
#define OTGFS_GINT_IPXFR (1 << 21) /* Bit 21: Incomplete periodic transfer (host) */
/* Bit 22: Reserved, must be kept at reset value */
#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
# define OTGFS_GINT_RSTDET (1 << 23) /* Bit 23: Reset detected interrupt */
#endif
#define OTGFS_GINT_HPRT (1 << 24) /* Bit 24: Host port interrupt */
#define OTGFS_GINT_HC (1 << 25) /* Bit 25: Host channels interrupt */
#define OTGFS_GINT_PTXFE (1 << 26) /* Bit 26: Periodic TxFIFO empty */
#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
# define OTGFS_GINT_LPMINT (1 << 27) /* Bit 27: LPM interrupt */
#endif
#define OTGFS_GINT_CIDSCHG (1 << 28) /* Bit 28: Connector ID status change */
#define OTGFS_GINT_DISC (1 << 29) /* Bit 29: Disconnect detected interrupt */
#define OTGFS_GINT_SRQ (1 << 30) /* Bit 30: Session request/new session detected interrupt */
#define OTGFS_GINT_WKUP (1 << 31) /* Bit 31: Resume/remote wakeup detected interrupt */
#define OTGFS_GINT_RES89 (3 << 8) /* Bits 8-9: Reserved, must be kept at reset value */
#define OTGFS_GINT_ESUSP (1 << 10) /* Bit 10: rc_w1 Early suspend */
#define OTGFS_GINT_USBSUSP (1 << 11) /* Bit 11: rc_w1 USB suspend */
#define OTGFS_GINT_USBRST (1 << 12) /* Bit 12: rc_w1 USB reset */
#define OTGFS_GINT_ENUMDNE (1 << 13) /* Bit 13: rc_w1 Enumeration done */
#define OTGFS_GINT_ISOODRP (1 << 14) /* Bit 14: rc_w1 Isochronous OUT packet dropped interrupt */
#define OTGFS_GINT_EOPF (1 << 15) /* Bit 15: rc_w1 End of periodic frame interrupt */
#define OTGFS_GINT_RES16 (1 << 16) /* Bits 16 Reserved, must be kept at reset value */
#define OTGFS_GINTMSK_EPMISM (1 << 17) /* Bit 17: Reserved in GINT rw Endpoint mismatch interrupt mask */
#define OTGFS_GINT_IEP (1 << 18) /* Bit 18: ro IN endpoint interrupt */
#define OTGFS_GINT_OEP (1 << 19) /* Bit 19: ro OUT endpoint interrupt */
#define OTGFS_GINT_IISOIXFR (1 << 20) /* Bit 20: rc_w1Incomplete isochronous IN transfer */
#define OTGFS_GINT_IISOOXFR (1 << 21) /* Bit 21: rc_w1 Incomplete isochronous OUT transfer */
#define OTGFS_GINT_RES2223 (3 << 22) /* Bits 22-23: Reserved, must be kept at reset value */
#define OTGFS_GINT_HPRT (1 << 24) /* Bit 24: ro Host port interrupt */
#define OTGFS_GINT_HC (1 << 25) /* Bit 25: ro Host channels interrupt */
#define OTGFS_GINT_PTXFE (1 << 26) /* Bit 26: ro Periodic TxFIFO empty */
#define OTGFS_GINT_RES27 (1 << 27) /* Bit 27 Reserved, must be kept at reset value */
#define OTGFS_GINT_CIDSCHG (1 << 28) /* Bit 28: rc_w1 Connector ID status change */
#define OTGFS_GINT_DISC (1 << 29) /* Bit 29: rc_w1 Disconnect detected interrupt */
#define OTGFS_GINT_SRQ (1 << 30) /* Bit 30: rc_w1 Session request/new session detected interrupt */
#define OTGFS_GINT_WKUP (1 << 31) /* Bit 31: rc_w1 Resume/remote wakeup detected interrupt */
/* Receive status debug read/OTG status read and pop registers (host mode) */

395
arch/arm/src/stm32/iar/stm32_vectors.S
View File

@ -176,7 +176,207 @@ __vector_table:
#if defined(CONFIG_STM32_STM32L15XX)
# include "chip/stm32l15xxx_vectors.h"
#elif defined(CONFIG_STM32_STM32F10XX)
# include "chip/stm32f10xxx_vectors.h"
# if defined(CONFIG_STM32_VALUELINE)
DCD stm32_wwdg /* Vector 16+0: Window Watchdog interrupt */
DCD stm32_pvd /* Vector 16+1: PVD through EXTI Line detection interrupt */
DCD stm32_tamper /* Vector 16+2: Tamper interrupt */
DCD stm32_rtc /* Vector 16+3: RTC Wakeup through EXTI line interrupt */
DCD stm32_flash /* Vector 16+4: Flash global interrupt */
DCD stm32_rcc /* Vector 16+5: RCC global interrupt */
DCD stm32_exti0 /* Vector 16+6: EXTI Line 0 interrupt */
DCD stm32_exti1 /* Vector 16+7: EXTI Line 1 interrupt */
DCD stm32_exti2 /* Vector 16+8: EXTI Line 2 interrupt */
DCD stm32_exti3 /* Vector 16+9: EXTI Line 3 interrupt */
DCD stm32_exti4 /* Vector 16+10: EXTI Line 4 interrupt */
DCD stm32_dma1ch1 /* Vector 16+11: DMA1 Channel 1 global interrupt */
DCD stm32_dma1ch2 /* Vector 16+12: DMA1 Channel 2 global interrupt */
DCD stm32_dma1ch3 /* Vector 16+13: DMA1 Channel 3 global interrupt */
DCD stm32_dma1ch4 /* Vector 16+14: DMA1 Channel 4 global interrupt */
DCD stm32_dma1ch5 /* Vector 16+15: DMA1 Channel 5 global interrupt */
DCD stm32_dma1ch6 /* Vector 16+16: DMA1 Channel 6 global interrupt */
DCD stm32_dma1ch7 /* Vector 16+17: DMA1 Channel 7 global interrupt */
DCD stm32_adc1 /* Vector 16+18: ADC1 global interrupt */
DCD stm32_reserved /* Vector 16+19: Reserved 0 */
DCD stm32_reserved /* Vector 16+20: Reserved 1 */
DCD stm32_reserved /* Vector 16+21: Reserved 2 */
DCD stm32_reserved /* Vector 16+22: Reserved 3 */
DCD stm32_exti95 /* Vector 16+23: EXTI Line[9:5] interrupts */
DCD stm32_tim1brk /* Vector 16+24: TIM1 Break interrupt; TIM15 global interrupt */
DCD stm32_tim1up /* Vector 16+25: TIM1 Update interrupt; TIM16 global interrupt */
DCD stm32_tim1trgcom /* Vector 16+26: TIM1 Trigger and Commutation interrupts; TIM17 global interrupt */
DCD stm32_tim1cc /* Vector 16+27: TIM1 Capture Compare interrupt */
DCD stm32_tim2 /* Vector 16+28: TIM2 global interrupt */
DCD stm32_tim3 /* Vector 16+29: TIM3 global interrupt */
DCD stm32_tim4 /* Vector 16+30: TIM4 global interrupt */
DCD stm32_i2c1ev /* Vector 16+31: I2C1 event interrupt */
DCD stm32_i2c1er /* Vector 16+32: I2C1 error interrupt */
DCD stm32_i2c2ev /* Vector 16+33: I2C2 event interrupt */
DCD stm32_i2c2er /* Vector 16+34: I2C2 error interrupt */
DCD stm32_spi1 /* Vector 16+35: SPI1 global interrupt */
DCD stm32_spi2 /* Vector 16+36: SPI2 global interrupt */
DCD stm32_usart1 /* Vector 16+37: USART1 global interrupt */
DCD stm32_usart2 /* Vector 16+38: USART2 global interrupt */
DCD stm32_usart3 /* Vector 16+39: USART3 global interrupt */
DCD stm32_exti1510 /* Vector 16+40: EXTI Line[15:10] interrupts */
DCD stm32_rtcalr /* Vector 16+41: RTC alarms (A and B) through EXTI line interrupt */
DCD stm32_cec /* Vector 16+42: CEC global interrupt */
DCD stm32_tim12 /* Vector 16+43: TIM12 global interrupt */
DCD stm32_tim13 /* Vector 16+44: TIM13 global interrupt */
DCD stm32_tim14 /* Vector 16+45: TIM14 global interrupt */
DCD stm32_reserved /* Vector 16+46: Reserved 4 */
DCD stm32_reserved /* Vector 16+47: Reserved 5 */
DCD stm32_fsmc /* Vector 16+48: FSMC global interrupt */
DCD stm32_reserved /* Vector 16+49: Reserved 6 */
DCD stm32_tim5 /* Vector 16+50: TIM5 global interrupt */
DCD stm32_spi3 /* Vector 16+51: SPI3 global interrupt */
DCD stm32_uart4 /* Vector 16+52: USART2 global interrupt */
DCD stm32_uart5 /* Vector 16+53: UART5 global interrupt */
DCD stm32_tim6 /* Vector 16+54: TIM6 global interrupt */
DCD stm32_tim7 /* Vector 16+55: TIM7 global interrupt */
DCD stm32_dma2ch1 /* Vector 16+56: DMA2 Channel 1 global interrupt */
DCD stm32_dma2ch2 /* Vector 16+57: DMA2 Channel 2 global interrupt */
DCD stm32_dma2ch3 /* Vector 16+58: DMA2 Channel 3 global interrupt */
DCD stm32_dma2ch45 /* Vector 16+59: DMA2 Channel 4 and 5 global interrupt */
DCD stm32_dma2ch5 /* Vector 16+60: DMA2 Channel 5 global interrupt */
# elif defined(CONFIG_STM32_CONNECTIVITYLINE)
DCD stm32_wwdg /* Vector 16+0: Window Watchdog interrupt */
DCD stm32_pvd /* Vector 16+1: PVD through EXTI Line detection interrupt */
DCD stm32_tamper /* Vector 16+2: Tamper interrupt */
DCD stm32_rtc /* Vector 16+3: RTC global interrupt */
DCD stm32_flash /* Vector 16+4: Flash global interrupt */
DCD stm32_rcc /* Vector 16+5: RCC global interrupt */
DCD stm32_exti0 /* Vector 16+6: EXTI Line 0 interrupt */
DCD stm32_exti1 /* Vector 16+7: EXTI Line 1 interrupt */
DCD stm32_exti2 /* Vector 16+8: EXTI Line 2 interrupt */
DCD stm32_exti3 /* Vector 16+9: EXTI Line 3 interrupt */
DCD stm32_exti4 /* Vector 16+10: EXTI Line 4 interrupt */
DCD stm32_dma1ch1 /* Vector 16+11: DMA1 Channel 1 global interrupt */
DCD stm32_dma1ch2 /* Vector 16+12: DMA1 Channel 2 global interrupt */
DCD stm32_dma1ch3 /* Vector 16+13: DMA1 Channel 3 global interrupt */
DCD stm32_dma1ch4 /* Vector 16+14: DMA1 Channel 4 global interrupt */
DCD stm32_dma1ch5 /* Vector 16+15: DMA1 Channel 5 global interrupt */
DCD stm32_dma1ch6 /* Vector 16+16: DMA1 Channel 6 global interrupt */
DCD stm32_dma1ch7 /* Vector 16+17: DMA1 Channel 7 global interrupt */
DCD stm32_adc12 /* Vector 16+18: ADC1 and ADC2 global interrupt */
DCD stm32_can1tx /* Vector 16+19: CAN1 TX interrupts */
DCD stm32_can1rx0 /* Vector 16+20: CAN1 RX0 interrupts */
DCD stm32_can1rx /* Vector 16+21: CAN1 RX1 interrupt */
DCD stm32_can1sce /* Vector 16+22: CAN1 SCE interrupt */
DCD stm32_exti95 /* Vector 16+23: EXTI Line[9:5] interrupts */
DCD stm32_tim1brk /* Vector 16+24: TIM1 Break interrupt */
DCD stm32_tim1up /* Vector 16+25: TIM1 Update interrupt */
DCD stm32_tim1trgcom /* Vector 16+26: TIM1 Trigger and Commutation interrupts */
DCD stm32_tim1cc /* Vector 16+27: TIM1 Capture Compare interrupt */
DCD stm32_tim2 /* Vector 16+28: TIM2 global interrupt */
DCD stm32_tim3 /* Vector 16+29: TIM3 global interrupt */
DCD stm32_tim4 /* Vector 16+30: TIM4 global interrupt */
DCD stm32_i2c1ev /* Vector 16+31: I2C1 event interrupt */
DCD stm32_i2c1er /* Vector 16+32: I2C1 error interrupt */
DCD stm32_i2c2ev /* Vector 16+33: I2C2 event interrupt */
DCD stm32_i2c2er /* Vector 16+34: I2C2 error interrupt */
DCD stm32_spi1 /* Vector 16+35: SPI1 global interrupt */
DCD stm32_spi2 /* Vector 16+36: SPI2 global interrupt */
DCD stm32_usart1 /* Vector 16+37: USART1 global interrupt */
DCD stm32_usart2 /* Vector 16+38: USART2 global interrupt */
DCD stm32_usart3 /* Vector 16+39: USART3 global interrupt */
DCD stm32_exti1510 /* Vector 16+40: EXTI Line[15:10] interrupts */
DCD stm32_rtcalr /* Vector 16+41: RTC alarm through EXTI line interrupt */
DCD stm32_otgfswkup /* Vector 16+42: USB On-The-Go FS Wakeup through EXTI line interrupt */
DCD stm32_reserved /* Vector 16+43: Reserved 0 */
DCD stm32_reserved /* Vector 16+44: Reserved 1 */
DCD stm32_reserved /* Vector 16+45: Reserved 2 */
DCD stm32_reserved /* Vector 16+46: Reserved 3 */
DCD stm32_reserved /* Vector 16+47: Reserved 4 */
DCD stm32_reserved /* Vector 16+48: Reserved 5 */
DCD stm32_reserved /* Vector 16+49: Reserved 6 */
DCD stm32_tim5 /* Vector 16+50: TIM5 global interrupt */
DCD stm32_spi3 /* Vector 16+51: SPI3 global interrupt */
DCD stm32_uart4 /* Vector 16+52: UART4 global interrupt */
DCD stm32_uart5 /* Vector 16+53: UART5 global interrupt */
DCD stm32_tim6 /* Vector 16+54: TIM6 global interrupt */
DCD stm32_tim7 /* Vector 16+55: TIM7 global interrupt */
DCD stm32_dma2ch1 /* Vector 16+56: DMA2 Channel 1 global interrupt */
DCD stm32_dma2ch2 /* Vector 16+57: DMA2 Channel 2 global interrupt */
DCD stm32_dma2ch3 /* Vector 16+58: DMA2 Channel 3 global interrupt */
DCD stm32_dma2ch4 /* Vector 16+59: DMA2 Channel 4 global interrupt */
DCD stm32_dma2ch5 /* Vector 16+60: DMA2 Channel 5 global interrupt */
DCD stm32_eth /* Vector 16+61: Ethernet global interrupt */
DCD stm32_ethwkup /* Vector 16+62: Ethernet Wakeup through EXTI line interrupt */
DCD stm32_can2tx /* Vector 16+63: CAN2 TX interrupts */
DCD stm32_can2rx0 /* Vector 16+64: CAN2 RX0 interrupts */
DCD stm32_can2rx1 /* Vector 16+65: CAN2 RX1 interrupt */
DCD stm32_can2sce /* Vector 16+66: CAN2 SCE interrupt */
DCD stm32_otgfs /* Vector 16+67: USB On The Go FS global interrupt */
# else /* CONFIG_STM32_CONNECTIVITYLINE */
DCD stm32_wwdg /* Vector 16+0: Window Watchdog interrupt */
DCD stm32_pvd /* Vector 16+1: PVD through EXTI Line detection interrupt */
DCD stm32_tamper /* Vector 16+2: Tamper interrupt */
DCD stm32_rtc /* Vector 16+3: RTC global interrupt */
DCD stm32_flash /* Vector 16+4: Flash global interrupt */
DCD stm32_rcc /* Vector 16+5: RCC global interrupt */
DCD stm32_exti0 /* Vector 16+6: EXTI Line 0 interrupt */
DCD stm32_exti1 /* Vector 16+7: EXTI Line 1 interrupt */
DCD stm32_exti2 /* Vector 16+8: EXTI Line 2 interrupt */
DCD stm32_exti3 /* Vector 16+9: EXTI Line 3 interrupt */
DCD stm32_exti4 /* Vector 16+10: EXTI Line 4 interrupt */
DCD stm32_dma1ch1 /* Vector 16+11: DMA1 Channel 1 global interrupt */
DCD stm32_dma1ch2 /* Vector 16+12: DMA1 Channel 2 global interrupt */
DCD stm32_dma1ch3 /* Vector 16+13: DMA1 Channel 3 global interrupt */
DCD stm32_dma1ch4 /* Vector 16+14: DMA1 Channel 4 global interrupt */
DCD stm32_dma1ch5 /* Vector 16+15: DMA1 Channel 5 global interrupt */
DCD stm32_dma1ch6 /* Vector 16+16: DMA1 Channel 6 global interrupt */
DCD stm32_dma1ch7 /* Vector 16+17: DMA1 Channel 7 global interrupt */
DCD stm32_adc12 /* Vector 16+18: ADC1 and ADC2 global interrupt */
DCD stm32_usbhpcantx /* Vector 16+19: USB High Priority or CAN TX interrupts*/
DCD stm32_usblpcanrx0 /* Vector 16+20: USB Low Priority or CAN RX0 interrupts*/
DCD stm32_can1rx1 /* Vector 16+21: CAN1 RX1 interrupt */
DCD stm32_can1sce /* Vector 16+22: CAN1 SCE interrupt */
DCD stm32_exti95 /* Vector 16+23: EXTI Line[9:5] interrupts */
DCD stm32_tim1brk /* Vector 16+24: TIM1 Break interrupt */
DCD stm32_tim1up /* Vector 16+25: TIM1 Update interrupt */
DCD stm32_tim1rtgcom /* Vector 16+26: TIM1 Trigger and Commutation interrupts */
DCD stm32_tim1cc /* Vector 16+27: TIM1 Capture Compare interrupt */
DCD stm32_tim2 /* Vector 16+28: TIM2 global interrupt */
DCD stm32_tim3 /* Vector 16+29: TIM3 global interrupt */
DCD stm32_tim4 /* Vector 16+30: TIM4 global interrupt */
DCD stm32_i2c1ev /* Vector 16+31: I2C1 event interrupt */
DCD stm32_i2c1er /* Vector 16+32: I2C1 error interrupt */
DCD stm32_i2c2ev /* Vector 16+33: I2C2 event interrupt */
DCD stm32_i2c2er /* Vector 16+34: I2C2 error interrupt */
DCD stm32_spi1 /* Vector 16+35: SPI1 global interrupt */
DCD stm32_spi2 /* Vector 16+36: SPI2 global interrupt */
DCD stm32_usart1 /* Vector 16+37: USART1 global interrupt */
DCD stm32_usart2 /* Vector 16+38: USART2 global interrupt */
DCD stm32_usart3 /* Vector 16+39: USART3 global interrupt */
DCD stm32_exti1510 /* Vector 16+40: EXTI Line[15:10] interrupts */
DCD stm32_rtcalr /* Vector 16+41: RTC alarm through EXTI line interrupt */
DCD stm32_usbwkup /* Vector 16+42: USB wakeup from suspend through EXTI line interrupt*/
DCD stm32_tim8brk /* Vector 16+43: TIM8 Break interrupt */
DCD stm32_tim8up /* Vector 16+44: TIM8 Update interrupt */
DCD stm32_tim8trgcom /* Vector 16+45: TIM8 Trigger and Commutation interrupts */
DCD stm32_tim8cc /* Vector 16+46: TIM8 Capture Compare interrupt */
DCD stm32_adc3 /* Vector 16+47: ADC3 global interrupt */
DCD stm32_fsmc /* Vector 16+48: FSMC global interrupt */
DCD stm32_sdio /* Vector 16+49: SDIO global interrupt */
DCD stm32_tim5 /* Vector 16+50: TIM5 global interrupt */
DCD stm32_spi3 /* Vector 16+51: SPI3 global interrupt */
DCD stm32_uart4 /* Vector 16+52: UART4 global interrupt */
DCD stm32_uart5 /* Vector 16+53: UART5 global interrupt */
DCD stm32_tim6 /* Vector 16+54: TIM6 global interrupt */
DCD stm32_tim7 /* Vector 16+55: TIM7 global interrupt */
DCD stm32_dma2ch1 /* Vector 16+56: DMA2 Channel 1 global interrupt */
DCD stm32_dma2ch2 /* Vector 16+57: DMA2 Channel 2 global interrupt */
DCD stm32_dma2ch3 /* Vector 16+58: DMA2 Channel 3 global interrupt */
DCD stm32_dma2ch45 /* Vector 16+59: DMA2 Channel 4&5 global interrupt */
# endif /* CONFIG_STM32_CONNECTIVITYLINE */
#elif defined(CONFIG_STM32_STM32F20XX)
DCD stm32_wwdg /* Vector 16+0: Window Watchdog interrupt */
DCD stm32_pvd /* Vector 16+1: PVD through EXTI Line detection interrupt */
@ -278,7 +478,7 @@ __vector_table:
* .text
************************************************************************************/
SECTION .text:CODE:NOROOT(2)
SECTION .text:CODE:NOROOT(8)
handlers:
HANDLER stm32_reserved, STM32_IRQ_RESERVED /* Unexpected/reserved vector */
@ -304,8 +504,196 @@ handlers:
#if defined(CONFIG_STM32_STM32L15XX)
# include "chip/stm32l15xxx_vectors.h"
#elif defined(CONFIG_STM32_STM32F10XX)
# include "chip/stm32f10xxx_vectors.h"
# if defined(CONFIG_STM32_VALUELINE)
HANDLER stm32_wwdg, STM32_IRQ_WWDG /* Vector 16+0: Window Watchdog interrupt */
HANDLER stm32_pvd, STM32_IRQ_PVD /* Vector 16+1: PVD through EXTI Line detection interrupt */
HANDLER stm32_tamper, STM32_IRQ_TAMPER /* Vector 16+2: Tamper interrupt */
HANDLER stm32_rtc, STM32_IRQ_RTC /* Vector 16+3: RTC Wakeup through EXTI line interrupt */
HANDLER stm32_flash, STM32_IRQ_FLASH /* Vector 16+4: Flash global interrupt */
HANDLER stm32_rcc, STM32_IRQ_RCC /* Vector 16+5: RCC global interrupt */
HANDLER stm32_exti0, STM32_IRQ_EXTI0 /* Vector 16+6: EXTI Line 0 interrupt */
HANDLER stm32_exti1, STM32_IRQ_EXTI1 /* Vector 16+7: EXTI Line 1 interrupt */
HANDLER stm32_exti2, STM32_IRQ_EXTI2 /* Vector 16+8: EXTI Line 2 interrupt */
HANDLER stm32_exti3, STM32_IRQ_EXTI3 /* Vector 16+9: EXTI Line 3 interrupt */
HANDLER stm32_exti4, STM32_IRQ_EXTI4 /* Vector 16+10: EXTI Line 4 interrupt */
HANDLER stm32_dma1ch1, STM32_IRQ_DMA1CH1 /* Vector 16+11: DMA1 Channel 1 global interrupt */
HANDLER stm32_dma1ch2, STM32_IRQ_DMA1CH2 /* Vector 16+12: DMA1 Channel 2 global interrupt */
HANDLER stm32_dma1ch3, STM32_IRQ_DMA1CH3 /* Vector 16+13: DMA1 Channel 3 global interrupt */
HANDLER stm32_dma1ch4, STM32_IRQ_DMA1CH4 /* Vector 16+14: DMA1 Channel 4 global interrupt */
HANDLER stm32_dma1ch5, STM32_IRQ_DMA1CH5 /* Vector 16+15: DMA1 Channel 5 global interrupt */
HANDLER stm32_dma1ch6, STM32_IRQ_DMA1CH6 /* Vector 16+16: DMA1 Channel 6 global interrupt */
HANDLER stm32_dma1ch7, STM32_IRQ_DMA1CH7 /* Vector 16+17: DMA1 Channel 7 global interrupt */
HANDLER stm32_adc1, STM32_IRQ_ADC1 /* Vector 16+18: ADC1 global interrupt */
HANDLER stm32_exti95, STM32_IRQ_EXTI95 /* Vector 16+23: EXTI Line[9:5] interrupts */
HANDLER stm32_tim1brk, STM32_IRQ_TIM1BRK /* Vector 16+24: TIM1 Break interrupt; TIM15 global interrupt */
HANDLER stm32_tim1up, STM32_IRQ_TIM1UP /* Vector 16+25: TIM1 Update interrupt; TIM16 global interrupt */
HANDLER stm32_tim1trgcom, STM32_IRQ_TIM1TRGCOM /* Vector 16+26: TIM1 Trigger and Commutation interrupts; TIM17 global interrupt */
HANDLER stm32_tim1cc, STM32_IRQ_TIM1CC /* Vector 16+27: TIM1 Capture Compare interrupt */
HANDLER stm32_tim2, STM32_IRQ_TIM2 /* Vector 16+28: TIM2 global interrupt */
HANDLER stm32_tim3, STM32_IRQ_TIM3 /* Vector 16+29: TIM3 global interrupt */
HANDLER stm32_tim4, STM32_IRQ_TIM4 /* Vector 16+30: TIM4 global interrupt */
HANDLER stm32_i2c1ev, STM32_IRQ_I2C1EV /* Vector 16+31: I2C1 event interrupt */
HANDLER stm32_i2c1er, STM32_IRQ_I2C1ER /* Vector 16+32: I2C1 error interrupt */
HANDLER stm32_i2c2ev, STM32_IRQ_I2C2EV /* Vector 16+33: I2C2 event interrupt */
HANDLER stm32_i2c2er, STM32_IRQ_I2C2ER /* Vector 16+34: I2C2 error interrupt */
HANDLER stm32_spi1, STM32_IRQ_SPI1 /* Vector 16+35: SPI1 global interrupt */
HANDLER stm32_spi2, STM32_IRQ_SPI2 /* Vector 16+36: SPI2 global interrupt */
HANDLER stm32_usart1, STM32_IRQ_USART1 /* Vector 16+37: USART1 global interrupt */
HANDLER stm32_usart2, STM32_IRQ_USART2 /* Vector 16+38: USART2 global interrupt */
HANDLER stm32_usart3, STM32_IRQ_USART3 /* Vector 16+39: USART3 global interrupt */
HANDLER stm32_exti1510, STM32_IRQ_EXTI1510 /* Vector 16+40: EXTI Line[15:10] interrupts */
HANDLER stm32_rtcalr, STM32_IRQ_RTCALR /* Vector 16+41: RTC alarms (A and B) through EXTI line interrupt */
HANDLER stm32_cec, STM32_IRQ_CEC /* Vector 16+42: CEC global interrupt */
HANDLER stm32_tim12, STM32_IRQ_TIM12 /* Vector 16+43: TIM12 global interrupt */
HANDLER stm32_tim13, STM32_IRQ_TIM13 /* Vector 16+44: TIM13 global interrupt */
HANDLER stm32_tim14, STM32_IRQ_TIM14 /* Vector 16+45: TIM14 global interrupt */
HANDLER stm32_fsmc, STM32_IRQ_FSMC /* Vector 16+48: FSMC global interrupt */
HANDLER stm32_tim5, STM32_IRQ_TIM5 /* Vector 16+50: TIM5 global interrupt */
HANDLER stm32_spi3, STM32_IRQ_SPI3 /* Vector 16+51: SPI3 global interrupt */
HANDLER stm32_uart4, STM32_IRQ_UART4 /* Vector 16+52: USART2 global interrupt */
HANDLER stm32_uart5, STM32_IRQ_UART5 /* Vector 16+53: UART5 global interrupt */
HANDLER stm32_tim6, STM32_IRQ_TIM6 /* Vector 16+54: TIM6 global interrupt */
HANDLER stm32_tim7, STM32_IRQ_TIM7 /* Vector 16+55: TIM7 global interrupt */
HANDLER stm32_dma2ch1, STM32_IRQ_DMA2CH1 /* Vector 16+56: DMA2 Channel 1 global interrupt */
HANDLER stm32_dma2ch2, STM32_IRQ_DMA2CH2 /* Vector 16+57: DMA2 Channel 2 global interrupt */
HANDLER stm32_dma2ch3, STM32_IRQ_DMA2CH3 /* Vector 16+58: DMA2 Channel 3 global interrupt */
HANDLER stm32_dma2ch45, STM32_IRQ_DMA2CH45 /* Vector 16+59: DMA2 Channel 4 and 5 global interrupt */
HANDLER stm32_dma2ch5, STM32_IRQ_DMA2CH5 /* Vector 16+60: DMA2 Channel 5 global interrupt */
# elif defined(CONFIG_STM32_CONNECTIVITYLINE)
HANDLER stm32_wwdg, STM32_IRQ_WWDG /* Vector 16+0: Window Watchdog interrupt */
HANDLER stm32_pvd, STM32_IRQ_PVD /* Vector 16+1: PVD through EXTI Line detection interrupt */
HANDLER stm32_tamper, STM32_IRQ_TAMPER /* Vector 16+2: Tamper interrupt */
HANDLER stm32_rtc, STM32_IRQ_RTC /* Vector 16+3: RTC global interrupt */
HANDLER stm32_flash, STM32_IRQ_FLASH /* Vector 16+4: Flash global interrupt */
HANDLER stm32_rcc, STM32_IRQ_RCC /* Vector 16+5: RCC global interrupt */
HANDLER stm32_exti0, STM32_IRQ_EXTI0 /* Vector 16+6: EXTI Line 0 interrupt */
HANDLER stm32_exti1, STM32_IRQ_EXTI1 /* Vector 16+7: EXTI Line 1 interrupt */
HANDLER stm32_exti2, STM32_IRQ_EXTI2 /* Vector 16+8: EXTI Line 2 interrupt */
HANDLER stm32_exti3, STM32_IRQ_EXTI3 /* Vector 16+9: EXTI Line 3 interrupt */
HANDLER stm32_exti4, STM32_IRQ_EXTI4 /* Vector 16+10: EXTI Line 4 interrupt */
HANDLER stm32_dma1ch1, STM32_IRQ_DMA1CH1 /* Vector 16+11: DMA1 Channel 1 global interrupt */
HANDLER stm32_dma1ch2, STM32_IRQ_DMA1CH2 /* Vector 16+12: DMA1 Channel 2 global interrupt */
HANDLER stm32_dma1ch3, STM32_IRQ_DMA1CH3 /* Vector 16+13: DMA1 Channel 3 global interrupt */
HANDLER stm32_dma1ch4, STM32_IRQ_DMA1CH4 /* Vector 16+14: DMA1 Channel 4 global interrupt */
HANDLER stm32_dma1ch5, STM32_IRQ_DMA1CH5 /* Vector 16+15: DMA1 Channel 5 global interrupt */
HANDLER stm32_dma1ch6, STM32_IRQ_DMA1CH6 /* Vector 16+16: DMA1 Channel 6 global interrupt */
HANDLER stm32_dma1ch7, STM32_IRQ_DMA1CH7 /* Vector 16+17: DMA1 Channel 7 global interrupt */
HANDLER stm32_adc12, STM32_IRQ_ADC12 /* Vector 16+18: ADC1 and ADC2 global interrupt */
HANDLER stm32_can1tx, STM32_IRQ_CAN1TX /* Vector 16+19: CAN1 TX interrupts */
HANDLER stm32_can1rx0, STM32_IRQ_CAN1RX0 /* Vector 16+20: CAN1 RX0 interrupts */
HANDLER stm32_can1rx, STM32_IRQ_CAN1RX1 /* Vector 16+21: CAN1 RX1 interrupt */
HANDLER stm32_can1sce, STM32_IRQ_CAN1SCE /* Vector 16+22: CAN1 SCE interrupt */
HANDLER stm32_exti95, STM32_IRQ_EXTI95 /* Vector 16+23: EXTI Line[9:5] interrupts */
HANDLER stm32_tim1brk, STM32_IRQ_TIM1BRK /* Vector 16+24: TIM1 Break interrupt */
HANDLER stm32_tim1up, STM32_IRQ_TIM1UP /* Vector 16+25: TIM1 Update interrupt */
HANDLER stm32_tim1trgcom, STM32_IRQ_TIM1TRGCOM /* Vector 16+26: TIM1 Trigger and Commutation interrupts */
HANDLER stm32_tim1cc, STM32_IRQ_TIM1CC /* Vector 16+27: TIM1 Capture Compare interrupt */
HANDLER stm32_tim2, STM32_IRQ_TIM2 /* Vector 16+28: TIM2 global interrupt */
HANDLER stm32_tim3, STM32_IRQ_TIM3 /* Vector 16+29: TIM3 global interrupt */
HANDLER stm32_tim4, STM32_IRQ_TIM4 /* Vector 16+30: TIM4 global interrupt */
HANDLER stm32_i2c1ev, STM32_IRQ_I2C1EV /* Vector 16+31: I2C1 event interrupt */
HANDLER stm32_i2c1er, STM32_IRQ_I2C1ER /* Vector 16+32: I2C1 error interrupt */
HANDLER stm32_i2c2ev, STM32_IRQ_I2C2EV /* Vector 16+33: I2C2 event interrupt */
HANDLER stm32_i2c2er, STM32_IRQ_I2C2ER /* Vector 16+34: I2C2 error interrupt */
HANDLER stm32_spi1, STM32_IRQ_SPI1 /* Vector 16+35: SPI1 global interrupt */
HANDLER stm32_spi2, STM32_IRQ_SPI2 /* Vector 16+36: SPI2 global interrupt */
HANDLER stm32_usart1, STM32_IRQ_USART1 /* Vector 16+37: USART1 global interrupt */
HANDLER stm32_usart2, STM32_IRQ_USART2 /* Vector 16+38: USART2 global interrupt */
HANDLER stm32_usart3, STM32_IRQ_USART3 /* Vector 16+39: USART3 global interrupt */
HANDLER stm32_exti1510, STM32_IRQ_EXTI1510 /* Vector 16+40: EXTI Line[15:10] interrupts */
HANDLER stm32_rtcalr, STM32_IRQ_RTCALRM /* Vector 16+41: RTC alarm through EXTI line interrupt */
HANDLER stm32_otgfswkup, STM32_IRQ_OTGFSWKUP /* Vector 16+42: USB On-The-Go FS Wakeup through EXTI line interrupt */
HANDLER stm32_tim5, STM32_IRQ_TIM5 /* Vector 16+50: TIM5 global interrupt */
HANDLER stm32_spi3, STM32_IRQ_SPI3 /* Vector 16+51: SPI3 global interrupt */
HANDLER stm32_uart4 , STM32_IRQ_UART4 /* Vector 16+52: UART4 global interrupt */
HANDLER stm32_uart5, STM32_IRQ_UART5 /* Vector 16+53: UART5 global interrupt */
HANDLER stm32_tim6, STM32_IRQ_TIM6 /* Vector 16+54: TIM6 global interrupt */
HANDLER stm32_tim7, STM32_IRQ_TIM7 /* Vector 16+55: TIM7 global interrupt */
HANDLER stm32_dma2ch1, STM32_IRQ_DMA2CH1 /* Vector 16+56: DMA2 Channel 1 global interrupt */
HANDLER stm32_dma2ch2, STM32_IRQ_DMA2CH2 /* Vector 16+57: DMA2 Channel 2 global interrupt */
HANDLER stm32_dma2ch3, STM32_IRQ_DMA2CH3 /* Vector 16+58: DMA2 Channel 3 global interrupt */
HANDLER stm32_dma2ch4, STM32_IRQ_DMA2CH4 /* Vector 16+59: DMA2 Channel 4 global interrupt */
HANDLER stm32_dma2ch5, STM32_IRQ_DMA2CH5 /* Vector 16+60: DMA2 Channel 5 global interrupt */
HANDLER stm32_eth, STM32_IRQ_ETH /* Vector 16+61: Ethernet global interrupt */
HANDLER stm32_ethwkup, STM32_IRQ_ETHWKUP /* Vector 16+62: Ethernet Wakeup through EXTI line interrupt */
HANDLER stm32_can2tx, STM32_IRQ_CAN2TX /* Vector 16+63: CAN2 TX interrupts */
HANDLER stm32_can2rx0, STM32_IRQ_CAN2RX0 /* Vector 16+64: CAN2 RX0 interrupts */
HANDLER stm32_can2rx1, STM32_IRQ_CAN2RX1 /* Vector 16+65: CAN2 RX1 interrupt */
HANDLER stm32_can2sce, STM32_IRQ_CAN2SCE /* Vector 16+66: CAN2 SCE interrupt */
HANDLER stm32_otgfs, STM32_IRQ_OTGFS /* Vector 16+67: USB On The Go FS global interrupt */
# else /* CONFIG_STM32_CONNECTIVITYLINE */
HANDLER stm32_wwdg, STM32_IRQ_WWDG /* Vector 16+0: Window Watchdog interrupt */
HANDLER stm32_pvd, STM32_IRQ_PVD /* Vector 16+1: PVD through EXTI Line detection interrupt */
HANDLER stm32_tamper, STM32_IRQ_TAMPER /* Vector 16+2: Tamper interrupt */
HANDLER stm32_rtc, STM32_IRQ_RTC /* Vector 16+3: RTC global interrupt */
HANDLER stm32_flash, STM32_IRQ_FLASH /* Vector 16+4: Flash global interrupt */
HANDLER stm32_rcc, STM32_IRQ_RCC /* Vector 16+5: RCC global interrupt */
HANDLER stm32_exti0, STM32_IRQ_EXTI0 /* Vector 16+6: EXTI Line 0 interrupt */
HANDLER stm32_exti1, STM32_IRQ_EXTI1 /* Vector 16+7: EXTI Line 1 interrupt */
HANDLER stm32_exti2, STM32_IRQ_EXTI2 /* Vector 16+8: EXTI Line 2 interrupt */
HANDLER stm32_exti3, STM32_IRQ_EXTI3 /* Vector 16+9: EXTI Line 3 interrupt */
HANDLER stm32_exti4, STM32_IRQ_EXTI4 /* Vector 16+10: EXTI Line 4 interrupt */
HANDLER stm32_dma1ch1, STM32_IRQ_DMA1CH1 /* Vector 16+11: DMA1 Channel 1 global interrupt */
HANDLER stm32_dma1ch2, STM32_IRQ_DMA1CH2 /* Vector 16+12: DMA1 Channel 2 global interrupt */
HANDLER stm32_dma1ch3, STM32_IRQ_DMA1CH3 /* Vector 16+13: DMA1 Channel 3 global interrupt */
HANDLER stm32_dma1ch4, STM32_IRQ_DMA1CH4 /* Vector 16+14: DMA1 Channel 4 global interrupt */
HANDLER stm32_dma1ch5, STM32_IRQ_DMA1CH5 /* Vector 16+15: DMA1 Channel 5 global interrupt */
HANDLER stm32_dma1ch6, STM32_IRQ_DMA1CH6 /* Vector 16+16: DMA1 Channel 6 global interrupt */
HANDLER stm32_dma1ch7, STM32_IRQ_DMA1CH7 /* Vector 16+17: DMA1 Channel 7 global interrupt */
HANDLER stm32_adc12, STM32_IRQ_ADC12 /* Vector 16+18: ADC1 and ADC2 global interrupt */
HANDLER stm32_usbhpcantx, STM32_IRQ_USBHPCANTX /* Vector 16+19: USB High Priority or CAN TX interrupts*/
HANDLER stm32_usblpcanrx0, STM32_IRQ_USBLPCANRX0 /* Vector 16+20: USB Low Priority or CAN RX0 interrupts*/
HANDLER stm32_can1rx1, STM32_IRQ_CAN1RX1 /* Vector 16+21: CAN1 RX1 interrupt */
HANDLER stm32_can1sce, STM32_IRQ_CAN1SCE /* Vector 16+22: CAN1 SCE interrupt */
HANDLER stm32_exti95, STM32_IRQ_EXTI95 /* Vector 16+23: EXTI Line[9:5] interrupts */
HANDLER stm32_tim1brk, STM32_IRQ_TIM1BRK /* Vector 16+24: TIM1 Break interrupt */
HANDLER stm32_tim1up, STM32_IRQ_TIM1UP /* Vector 16+25: TIM1 Update interrupt */
HANDLER stm32_tim1rtgcom, STM32_IRQ_TIM1TRGCOM /* Vector 16+26: TIM1 Trigger and Commutation interrupts */
HANDLER stm32_tim1cc, STM32_IRQ_TIM1CC /* Vector 16+27: TIM1 Capture Compare interrupt */
HANDLER stm32_tim2, STM32_IRQ_TIM2 /* Vector 16+28: TIM2 global interrupt */
HANDLER stm32_tim3, STM32_IRQ_TIM3 /* Vector 16+29: TIM3 global interrupt */
HANDLER stm32_tim4, STM32_IRQ_TIM4 /* Vector 16+30: TIM4 global interrupt */
HANDLER stm32_i2c1ev, STM32_IRQ_I2C1EV /* Vector 16+31: I2C1 event interrupt */
HANDLER stm32_i2c1er, STM32_IRQ_I2C1ER /* Vector 16+32: I2C1 error interrupt */
HANDLER stm32_i2c2ev, STM32_IRQ_I2C2EV /* Vector 16+33: I2C2 event interrupt */
HANDLER stm32_i2c2er, STM32_IRQ_I2C2ER /* Vector 16+34: I2C2 error interrupt */
HANDLER stm32_spi1, STM32_IRQ_SPI1 /* Vector 16+35: SPI1 global interrupt */
HANDLER stm32_spi2, STM32_IRQ_SPI2 /* Vector 16+36: SPI2 global interrupt */
HANDLER stm32_usart1, STM32_IRQ_USART1 /* Vector 16+37: USART1 global interrupt */
HANDLER stm32_usart2, STM32_IRQ_USART2 /* Vector 16+38: USART2 global interrupt */
HANDLER stm32_usart3, STM32_IRQ_USART3 /* Vector 16+39: USART3 global interrupt */
HANDLER stm32_exti1510, STM32_IRQ_EXTI1510 /* Vector 16+40: EXTI Line[15:10] interrupts */
HANDLER stm32_rtcalr, STM32_IRQ_RTCALRM /* Vector 16+41: RTC alarm through EXTI line interrupt */
HANDLER stm32_usbwkup, STM32_IRQ_USBWKUP /* Vector 16+42: USB wakeup from suspend through EXTI line interrupt*/
HANDLER stm32_tim8brk, STM32_IRQ_TIM8BRK /* Vector 16+43: TIM8 Break interrupt */
HANDLER stm32_tim8up, STM32_IRQ_TIM8UP /* Vector 16+44: TIM8 Update interrupt */
HANDLER stm32_tim8trgcom, STM32_IRQ_TIM8TRGCOM /* Vector 16+45: TIM8 Trigger and Commutation interrupts */
HANDLER stm32_tim8cc, STM32_IRQ_TIM8CC /* Vector 16+46: TIM8 Capture Compare interrupt */
HANDLER stm32_adc3, STM32_IRQ_ADC3 /* Vector 16+47: ADC3 global interrupt */
HANDLER stm32_fsmc, STM32_IRQ_FSMC /* Vector 16+48: FSMC global interrupt */
HANDLER stm32_sdio, STM32_IRQ_SDIO /* Vector 16+49: SDIO global interrupt */
HANDLER stm32_tim5, STM32_IRQ_TIM5 /* Vector 16+50: TIM5 global interrupt */
HANDLER stm32_spi3, STM32_IRQ_SPI3 /* Vector 16+51: SPI3 global interrupt */
HANDLER stm32_uart4, STM32_IRQ_UART4 /* Vector 16+52: UART4 global interrupt */
HANDLER stm32_uart5, STM32_IRQ_UART5 /* Vector 16+53: UART5 global interrupt */
HANDLER stm32_tim6, STM32_IRQ_TIM6 /* Vector 16+54: TIM6 global interrupt */
HANDLER stm32_tim7, STM32_IRQ_TIM7 /* Vector 16+55: TIM7 global interrupt */
HANDLER stm32_dma2ch1, STM32_IRQ_DMA2CH1 /* Vector 16+56: DMA2 Channel 1 global interrupt */
HANDLER stm32_dma2ch2, STM32_IRQ_DMA2CH2 /* Vector 16+57: DMA2 Channel 2 global interrupt */
HANDLER stm32_dma2ch3, STM32_IRQ_DMA2CH3 /* Vector 16+58: DMA2 Channel 3 global interrupt */
HANDLER stm32_dma2ch45, STM32_IRQ_DMA2CH45 /* Vector 16+59: DMA2 Channel 4&5 global interrupt */
# endif /* CONFIG_STM32_CONNECTIVITYLINE */
#elif defined(CONFIG_STM32_STM32F20XX)
HANDLER stm32_wwdg, STM32_IRQ_WWDG /* Vector 16+0: Window Watchdog interrupt */
HANDLER stm32_pvd, STM32_IRQ_PVD /* Vector 16+1: PVD through EXTI Line detection interrupt */
HANDLER stm32_tamper, STM32_IRQ_TAMPER /* Vector 16+2: Tamper and time stamp interrupts */
@ -387,6 +775,7 @@ handlers:
HANDLER stm32_dcmi, STM32_IRQ_DCMI /* Vector 16+78: DCMI global interrupt */
HANDLER stm32_cryp, STM32_IRQ_CRYP /* Vector 16+79: CRYP crypto global interrupt */
HANDLER stm32_hash, STM32_IRQ_HASH /* Vector 16+80: Hash and Rng global interrupt */
#elif defined(CONFIG_STM32_STM32F30XX)
# include "chip/stm32f30xxx_vectors.h"
#elif defined(CONFIG_STM32_STM32F37XX)

2
arch/arm/src/stm32/stm32_adc.c
View File

@ -1657,7 +1657,7 @@ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, FAR void *arg)
for (i = 0; i < priv->nchannels; i++)
{
priv->cb->au_receive(dev, priv->current, priv->dmabuffer[priv->current]);
priv->cb->au_receive(dev, priv->chanlist[priv->current], priv->dmabuffer[priv->current]);
priv->current++;
if (priv->current >= priv->nchannels)
{

4
arch/arm/src/stm32/stm32_bbsram.c
View File

@ -256,7 +256,7 @@ static void stm32_bbsram_semtake(FAR struct stm32_bbsram_s *priv)
static inline void stm32_bbsram_unlock(void)
{
(void)stm32_pwr_enablebkp(true);
stm32_pwr_enablebkp(true);
}
/****************************************************************************
@ -276,7 +276,7 @@ static inline void stm32_bbsram_unlock(void)
static inline void stm32_bbsram_lock(void)
{
(void)stm32_pwr_enablebkp(false);
stm32_pwr_enablebkp(false);
}
/****************************************************************************

15
arch/arm/src/stm32/stm32_eth.c
View File

@ -704,7 +704,10 @@ static void stm32_rxdescinit(FAR struct stm32_ethmac_s *priv);
#if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT)
static int stm32_phyintenable(FAR struct stm32_ethmac_s *priv);
#endif
#if defined(CONFIG_STM32_AUTONEG) || defined(CONFIG_NETDEV_PHY_IOCTL) || \
defined(CONFIG_ETH0_PHY_DM9161)
static int stm32_phyread(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t *value);
#endif
static int stm32_phywrite(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t value);
#ifdef CONFIG_ETH0_PHY_DM9161
static inline int stm32_dm9161(FAR struct stm32_ethmac_s *priv);
@ -1687,12 +1690,6 @@ static void stm32_receive(FAR struct stm32_ethmac_s *priv)
continue;
}
#ifdef CONFIG_NET_PKT
/* When packet sockets are enabled, feed the frame into the packet tap */
pkt_input(&priv->dev);
#endif
/* We only accept IP packets of the configured type and ARP packets */
#ifdef CONFIG_NET_IPv4
@ -3098,6 +3095,8 @@ static int stm32_phyintenable(struct stm32_ethmac_s *priv)
*
****************************************************************************/
#if defined(CONFIG_STM32_AUTONEG) || defined(CONFIG_NETDEV_PHY_IOCTL) || \
defined(CONFIG_ETH0_PHY_DM9161)
static int stm32_phyread(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t *value)
{
volatile uint32_t timeout;
@ -3134,6 +3133,7 @@ static int stm32_phyread(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t *val
return -ETIMEDOUT;
}
#endif
/****************************************************************************
* Function: stm32_phywrite
@ -3278,7 +3278,10 @@ static inline int stm32_dm9161(FAR struct stm32_ethmac_s *priv)
static int stm32_phyinit(FAR struct stm32_ethmac_s *priv)
{
#ifdef CONFIG_STM32_AUTOGEN
volatile uint32_t timeout;
#endif
uint32_t regval;
uint16_t phyval;
int ret;

33
arch/arm/src/stm32/stm32_freerun.c
View File

@ -53,7 +53,7 @@
#ifdef CONFIG_STM32_FREERUN
/****************************************************************************
* Private Functions
* Private Data
****************************************************************************/
static struct stm32_freerun_s *g_freerun;
@ -80,6 +80,7 @@ static struct stm32_freerun_s *g_freerun;
*
****************************************************************************/
#ifndef CONFIG_CLOCK_TIMEKEEPING
static int stm32_freerun_handler(int irq, void *context)
{
struct stm32_freerun_s *freerun = g_freerun;
@ -90,6 +91,7 @@ static int stm32_freerun_handler(int irq, void *context)
STM32_TIM_ACKINT(freerun->tch, 0);
return OK;
}
#endif /* CONFIG_CLOCK_TIMEKEEPING */
/****************************************************************************
* Public Functions
@ -140,15 +142,21 @@ int stm32_freerun_initialize(struct stm32_freerun_s *freerun, int chan,
* success.
*/
freerun->chan = chan;
freerun->running = false;
freerun->overflow = 0;
freerun->chan = chan;
freerun->running = false;
g_freerun = freerun;
#ifdef CONFIG_CLOCK_TIMEKEEPING
freerun->counter_mask = 0xffffffffull;
#endif
#ifndef CONFIG_CLOCK_TIMEKEEPING
freerun->overflow = 0;
g_freerun = freerun;
/* Set up to receive the callback when the counter overflow occurs */
STM32_TIM_SETISR(freerun->tch, stm32_freerun_handler, 0);
#endif
/* Set timer period */
@ -157,8 +165,11 @@ int stm32_freerun_initialize(struct stm32_freerun_s *freerun, int chan,
/* Start the counter */
STM32_TIM_SETMODE(freerun->tch, STM32_TIM_MODE_UP);
#ifndef CONFIG_CLOCK_TIMEKEEPING
STM32_TIM_ACKINT(freerun->tch, 0);
STM32_TIM_ENABLEINT(freerun->tch, 0);
#endif
return OK;
}
@ -182,6 +193,8 @@ int stm32_freerun_initialize(struct stm32_freerun_s *freerun, int chan,
*
****************************************************************************/
#ifndef CONFIG_CLOCK_TIMEKEEPING
int stm32_freerun_counter(struct stm32_freerun_s *freerun,
struct timespec *ts)
{
@ -257,6 +270,16 @@ int stm32_freerun_counter(struct stm32_freerun_s *freerun,
return OK;
}
#else /* CONFIG_CLOCK_TIMEKEEPING */
int stm32_freerun_counter(struct stm32_freerun_s *freerun, uint64_t *counter)
{
*counter = (uint64_t)STM32_TIM_GETCOUNTER(freerun->tch);
return OK;
}
#endif /* CONFIG_CLOCK_TIMEKEEPING */
/****************************************************************************
* Name: stm32_freerun_uninitialize
*

18
arch/arm/src/stm32/stm32_freerun.h
View File

@ -64,9 +64,16 @@ struct stm32_freerun_s
{
uint8_t chan; /* The timer/counter in use */
bool running; /* True: the timer is running */
uint32_t overflow; /* Timer counter overflow */
FAR struct stm32_tim_dev_s *tch; /* Handle returned by stm32_tim_init() */
uint32_t frequency;
#ifndef CONFIG_CLOCK_TIMEKEEPING
uint32_t overflow; /* Timer counter overflow */
#endif
#ifdef CONFIG_CLOCK_TIMEKEEPING
uint64_t counter_mask;
#endif
};
/****************************************************************************
@ -127,9 +134,18 @@ int stm32_freerun_initialize(struct stm32_freerun_s *freerun, int chan,
*
****************************************************************************/
#ifndef CONFIG_CLOCK_TIMEKEEPING
int stm32_freerun_counter(struct stm32_freerun_s *freerun,
struct timespec *ts);
#else /* CONFIG_CLOCK_TIMEKEEPING */
int stm32_freerun_counter(struct stm32_freerun_s *freerun,
uint64_t *counter);
#endif /* CONFIG_CLOCK_TIMEKEEPING */
/****************************************************************************
* Name: stm32_freerun_uninitialize
*

23
arch/arm/src/stm32/stm32_lse.c
View File

@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/stm32/stm32_lse.c
*
* Copyright (C) 2009, 2011, 2015 Gregory Nutt. All rights reserved.
* Copyright (C) 2009, 2011, 2015-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.orgr>
*
* Redistribution and use in source and binary forms, with or without
@ -45,18 +45,6 @@
#include "stm32_rcc.h"
#include "stm32_waste.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
@ -74,14 +62,12 @@
void stm32_rcc_enablelse(void)
{
bool bkpenabled;
/* The LSE is in the RTC domain and write access is denied to this domain
* after reset, you have to enable write access using DBP bit in the PWR CR
* register before to configuring the LSE.
*/
bkpenabled = stm32_pwr_enablebkp(true);
stm32_pwr_enablebkp(true);
#if defined(CONFIG_STM32_STM32L15XX)
/* Enable the External Low-Speed (LSE) oscillator by setting the LSEON bit
@ -115,8 +101,5 @@ void stm32_rcc_enablelse(void)
/* Disable backup domain access if it was disabled on entry */
if (!bkpenabled)
{
(void)stm32_pwr_enablebkp(false);
}
stm32_pwr_enablebkp(false);
}

345
arch/arm/src/stm32/stm32_oneshot_lowerhalf.c Normal file
View File

@ -0,0 +1,345 @@
/****************************************************************************
* arch/arm/src/stm32/stm32_oneshot_lowerhalf.c
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <time.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/kmalloc.h>
#include <nuttx/timers/oneshot.h>
#include "stm32_oneshot.h"
/****************************************************************************
* Private Types
****************************************************************************/
/* This structure describes the state of the oneshot timer lower-half driver */
struct stm32_oneshot_lowerhalf_s
{
/* This is the part of the lower half driver that is visible to the upper-
* half client of the driver. This must be the first thing in this
* structure so that pointers to struct oneshot_lowerhalf_s are cast
* compatible to struct stm32_oneshot_lowerhalf_s and vice versa.
*/
struct oneshot_lowerhalf_s lh; /* Common lower-half driver fields */
/* Private lower half data follows */
struct stm32_oneshot_s oneshot; /* STM32-specific oneshot state */
oneshot_callback_t callback; /* Internal handler that receives callback */
FAR void *arg; /* Argument that is passed to the handler */
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
static void stm32_oneshot_handler(void *arg);
static int stm32_max_delay(FAR struct oneshot_lowerhalf_s *lower,
FAR struct timespec *ts);
static int stm32_start(FAR struct oneshot_lowerhalf_s *lower,
oneshot_callback_t callback, FAR void *arg,
FAR const struct timespec *ts);
static int stm32_cancel(FAR struct oneshot_lowerhalf_s *lower,
FAR struct timespec *ts);
/****************************************************************************
* Private Data
****************************************************************************/
/* Lower half operations */
static const struct oneshot_operations_s g_oneshot_ops =
{
.max_delay = stm32_max_delay,
.start = stm32_start,
.cancel = stm32_cancel,
};
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_oneshot_handler
*
* Description:
* Timer expiration handler
*
* Input Parameters:
* arg - Should be the same argument provided when stm32_oneshot_start()
* was called.
*
* Returned Value:
* None
*
****************************************************************************/
static void stm32_oneshot_handler(void *arg)
{
FAR struct stm32_oneshot_lowerhalf_s *priv =
(FAR struct stm32_oneshot_lowerhalf_s *)arg;
oneshot_callback_t callback;
FAR void *cbarg;
DEBUGASSERT(priv != NULL);
/* Perhaps the callback was nullified in a race condition with
* stm32_cancel?
*/
if (priv->callback)
{
/* Sample and nullify BEFORE executing callback (in case the callback
* restarts the oneshot).
*/
callback = priv->callback;
cbarg = priv->arg;
priv->callback = NULL;
priv->arg = NULL;
/* Then perform the callback */
callback(&priv->lh, cbarg);
}
}
/****************************************************************************
* Name: stm32_max_delay
*
* Description:
* Determine the maximum delay of the one-shot timer (in microseconds)
*
* Input Parameters:
* lower An instance of the lower-half oneshot state structure. This
* structure must have been previously initialized via a call to
* oneshot_initialize();
* ts The location in which to return the maxumum delay.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on failure.
*
****************************************************************************/
static int stm32_max_delay(FAR struct oneshot_lowerhalf_s *lower,
FAR struct timespec *ts)
{
FAR struct stm32_oneshot_lowerhalf_s *priv =
(FAR struct stm32_oneshot_lowerhalf_s *)lower;
uint64_t usecs;
int ret;
DEBUGASSERT(priv != NULL && ts != NULL);
ret = stm32_oneshot_max_delay(&priv->oneshot, &usecs);
if (ret >= 0)
{
uint64_t sec = usecs / 1000000;
usecs -= 1000000 * sec;
ts->tv_sec = (time_t)sec;
ts->tv_nsec = (long)(usecs * 1000);
}
return ret;
}
/****************************************************************************
* Name: stm32_start
*
* Description:
* Start the oneshot timer
*
* Input Parameters:
* lower An instance of the lower-half oneshot state structure. This
* structure must have been previously initialized via a call to
* oneshot_initialize();
* handler The function to call when when the oneshot timer expires.
* arg An opaque argument that will accompany the callback.
* ts Provides the duration of the one shot timer.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on failure.
*
****************************************************************************/
static int stm32_start(FAR struct oneshot_lowerhalf_s *lower,
oneshot_callback_t callback, FAR void *arg,
FAR const struct timespec *ts)
{
FAR struct stm32_oneshot_lowerhalf_s *priv =
(FAR struct stm32_oneshot_lowerhalf_s *)lower;
irqstate_t flags;
int ret;
DEBUGASSERT(priv != NULL && callback != NULL && ts != NULL);
/* Save the callback information and start the timer */
flags = enter_critical_section();
priv->callback = callback;
priv->arg = arg;
ret = stm32_oneshot_start(&priv->oneshot,
stm32_oneshot_handler, priv, ts);
leave_critical_section(flags);
if (ret < 0)
{
tmrerr("ERROR: stm32_oneshot_start failed: %d\n", flags);
}
return ret;
}
/****************************************************************************
* Name: stm32_cancel
*
* Description:
* Cancel the oneshot timer and return the time remaining on the timer.
*
* NOTE: This function may execute at a high rate with no timer running (as
* when pre-emption is enabled and disabled).
*
* Input Parameters:
* lower Caller allocated instance of the oneshot state structure. This
* structure must have been previously initialized via a call to
* oneshot_initialize();
* ts The location in which to return the time remaining on the
* oneshot timer. A time of zero is returned if the timer is
* not running.
*
* Returned Value:
* Zero (OK) is returned on success. A call to up_timer_cancel() when
* the timer is not active should also return success; a negated errno
* value is returned on any failure.
*
****************************************************************************/
static int stm32_cancel(FAR struct oneshot_lowerhalf_s *lower,
FAR struct timespec *ts)
{
FAR struct stm32_oneshot_lowerhalf_s *priv =
(FAR struct stm32_oneshot_lowerhalf_s *)lower;
irqstate_t flags;
int ret;
DEBUGASSERT(priv != NULL);
/* Cancel the timer */
flags = enter_critical_section();
ret = stm32_oneshot_cancel(&priv->oneshot, ts);
priv->callback = NULL;
priv->arg = NULL;
leave_critical_section(flags);
if (ret < 0)
{
tmrerr("ERROR: stm32_oneshot_cancel failed: %d\n", flags);
}
return ret;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: oneshot_initialize
*
* Description:
* Initialize the oneshot timer and return a oneshot lower half driver
* instance.
*
* Input Parameters:
* chan Timer counter channel to be used.
* resolution The required resolution of the timer in units of
* microseconds. NOTE that the range is restricted to the
* range of uint16_t (excluding zero).
*
* Returned Value:
* On success, a non-NULL instance of the oneshot lower-half driver is
* returned. NULL is return on any failure.
*
****************************************************************************/
FAR struct oneshot_lowerhalf_s *oneshot_initialize(int chan,
uint16_t resolution)
{
FAR struct stm32_oneshot_lowerhalf_s *priv;
int ret;
/* Allocate an instance of the lower half driver */
priv = (FAR struct stm32_oneshot_lowerhalf_s *)
kmm_zalloc(sizeof(struct stm32_oneshot_lowerhalf_s));
if (priv == NULL)
{
tmrerr("ERROR: Failed to initialized state structure\n");
return NULL;
}
/* Initialize the lower-half driver structure */
priv->lh.ops = &g_oneshot_ops;
/* Initialize the contained STM32 oneshot timer */
ret = stm32_oneshot_initialize(&priv->oneshot, chan, resolution);
if (ret < 0)
{
tmrerr("ERROR: stm32_oneshot_initialize failed: %d\n", ret);
kmm_free(priv);
return NULL;
}
return &priv->lh;
}

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