nrf52 spi: build fixes and a missing register setting (polarity)
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@ -854,6 +854,8 @@ static void nrf52_spi_setmode(FAR struct spi_dev_s *dev,
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}
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}
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nrf52_spi_putreg(priv, NRF52_SPIM_CONFIG_OFFSET, regval);
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/* According to manual we have to set SCK pin output
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* value the same as CPOL value
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*/
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@ -1155,7 +1157,7 @@ static void nrf52_spi_exchange(FAR struct spi_dev_s *dev,
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if (nrf52_spi_getreg(priv, NRF52_SPIM_TXDAMOUNT_OFFSET) !=
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transfer_size)
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{
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spierr("Incomplete transfer wrote %" PRId32 " expected %d\n",
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spierr("Incomplete transfer wrote %" PRId32 " expected %zu\n",
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regval, nwords);
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}
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@ -1291,13 +1293,13 @@ static int nrf52_spi_pm_prepare(FAR struct pm_callback_s *cb, int domain,
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active |= nrf52_spi_getreg(&g_spi0dev, SPIM_EVENTS_STARTED);
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#endif
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#ifdef CONFIG_NRF52_SPI1_MASTER
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active |= nrf52_spi_getreg(&g_spi0dev, SPIM_EVENTS_STARTED);
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active |= nrf52_spi_getreg(&g_spi1dev, SPIM_EVENTS_STARTED);
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#endif
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#ifdef CONFIG_NRF52_SPI2_MASTER
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active |= nrf52_spi_getreg(&g_spi0dev, SPIM_EVENTS_STARTED);
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active |= nrf52_spi_getreg(&g_spi2dev, SPIM_EVENTS_STARTED);
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#endif
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#ifdef CONFIG_NRF52_SPI3_MASTER
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active |= nrf52_spi_getreg(&g_spi0dev, SPIM_EVENTS_STARTED);
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active |= nrf52_spi_getreg(&g_spi3dev, SPIM_EVENTS_STARTED);
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#endif
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if (active)
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