sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Merged in OSer916/nuttx/stm32f746g-disco-n25q (pull request #1074)

Browse Source 
stm32f746g-disco board add n25q128 support

* arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pinmap.h: fix QSPI pin
    config.

* arch/arm/src/stm32f7/stm32_qspi.c: fix gpio_dumpgpioconfig() function,
    fix qspi_command() function

* boards/arm/stm32f7/stm32f746g-disco/README.txt: fix board path

* boards/arm/stm32f7/stm32f746g-disco: add n25q128 function

* boards/arm/stm32f7/stm32f746g-disco/scripts/Make.defs: use st-flash tool to write fireware on Linux

Approved-by: Gregory Nutt <gnutt@nuttx.org>
This commit is contained in:
OSer 2019-11-21 13:39:45 +00:00 committed by Gregory Nutt
parent 677b0bf47e
commit e1f904c943
10 changed files with 248 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

44
arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pinmap.h
View File

@ -749,30 +749,30 @@
/* QuadSPI */
#define GPIO_QUADSPI_BK1_IO0_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTF|GPIO_PIN8)
#define GPIO_QUADSPI_BK1_IO0_2 (GPIO_ALT|GPIO_AF9|GPIO_PORTC|GPIO_PIN9)
#define GPIO_QUADSPI_BK1_IO0_3 (GPIO_ALT|GPIO_AF9|GPIO_PORTD|GPIO_PIN11)
#define GPIO_QUADSPI_BK1_IO1_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTF|GPIO_PIN9)
#define GPIO_QUADSPI_BK1_IO1_2 (GPIO_ALT|GPIO_AF9|GPIO_PORTC|GPIO_PIN10)
#define GPIO_QUADSPI_BK1_IO1_3 (GPIO_ALT|GPIO_AF9|GPIO_PORTD|GPIO_PIN12)
#define GPIO_QUADSPI_BK1_IO2_1 (GPIO_ALT|GPIO_AF9|GPIO_PORTE|GPIO_PIN2)
#define GPIO_QUADSPI_BK1_IO2_2 (GPIO_ALT|GPIO_AF9|GPIO_PORTF|GPIO_PIN7)
#define GPIO_QUADSPI_BK1_IO3_1 (GPIO_ALT|GPIO_AF9|GPIO_PORTA|GPIO_PIN1)
#define GPIO_QUADSPI_BK1_IO3_2 (GPIO_ALT|GPIO_AF9|GPIO_PORTD|GPIO_PIN13)
#define GPIO_QUADSPI_BK1_IO3_3 (GPIO_ALT|GPIO_AF9|GPIO_PORTF|GPIO_PIN6)
#define GPIO_QUADSPI_BK1_NCS (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN6)
#define GPIO_QUADSPI_BK1_IO0_1 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN8)
#define GPIO_QUADSPI_BK1_IO0_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN9)
#define GPIO_QUADSPI_BK1_IO0_3 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN11)
#define GPIO_QUADSPI_BK1_IO1_1 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN9)
#define GPIO_QUADSPI_BK1_IO1_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN10)
#define GPIO_QUADSPI_BK1_IO1_3 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN12)
#define GPIO_QUADSPI_BK1_IO2_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN2)
#define GPIO_QUADSPI_BK1_IO2_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN7)
#define GPIO_QUADSPI_BK1_IO3_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_100MHz|GPIO_PORTA|GPIO_PIN1)
#define GPIO_QUADSPI_BK1_IO3_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN13)
#define GPIO_QUADSPI_BK1_IO3_3 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN6)
#define GPIO_QUADSPI_BK1_NCS (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN6)
#define GPIO_QUADSPI_BK2_IO0_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN7)
#define GPIO_QUADSPI_BK2_IO0_2 (GPIO_ALT|GPIO_AF9|GPIO_PORTH|GPIO_PIN2)
#define GPIO_QUADSPI_BK2_IO1_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN8)
#define GPIO_QUADSPI_BK2_IO1_2 (GPIO_ALT|GPIO_AF9|GPIO_PORTH|GPIO_PIN3)
#define GPIO_QUADSPI_BK2_IO2_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN9)
#define GPIO_QUADSPI_BK2_IO2_2 (GPIO_ALT|GPIO_AF9|GPIO_PORTG|GPIO_PIN9)
#define GPIO_QUADSPI_BK2_IO3_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN10)
#define GPIO_QUADSPI_BK2_IO3_2 (GPIO_ALT|GPIO_AF9|GPIO_PORTG|GPIO_PIN14)
#define GPIO_QUADSPI_BK2_NCS (GPIO_ALT|GPIO_AF9|GPIO_PORTC|GPIO_PIN11)
#define GPIO_QUADSPI_BK2_IO0_1 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN7)
#define GPIO_QUADSPI_BK2_IO0_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN2)
#define GPIO_QUADSPI_BK2_IO1_1 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN8)
#define GPIO_QUADSPI_BK2_IO1_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN3)
#define GPIO_QUADSPI_BK2_IO2_1 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN9)
#define GPIO_QUADSPI_BK2_IO2_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN9)
#define GPIO_QUADSPI_BK2_IO3_1 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN10)
#define GPIO_QUADSPI_BK2_IO3_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN14)
#define GPIO_QUADSPI_BK2_NCS (GPIO_ALT|GPIO_AF9|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN11)
#define GPIO_QUADSPI_CLK (GPIO_ALT|GPIO_AF9|GPIO_PORTB|GPIO_PIN2)
#define GPIO_QUADSPI_CLK (GPIO_ALT|GPIO_AF9|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN2)
/* RTC */

56
arch/arm/src/stm32f7/stm32_qspi.c
View File

@ -578,22 +578,61 @@ static void qspi_dumpgpioconfig(const char *msg)
uint32_t regval;
spiinfo("%s:\n", msg);
regval = getreg32(STM32F7_GPIOE_MODER);
/* port B */
regval = getreg32(STM32_GPIOB_MODER);
spiinfo("B_MODER:%08x\n", regval);
regval = getreg32(STM32_GPIOB_OTYPER);
spiinfo("B_OTYPER:%08x\n", regval);
regval = getreg32(STM32_GPIOB_OSPEED);
spiinfo("B_OSPEED:%08x\n", regval);
regval = getreg32(STM32_GPIOB_PUPDR);
spiinfo("B_PUPDR:%08x\n", regval);
regval = getreg32(STM32_GPIOB_AFRL);
spiinfo("B_AFRL:%08x\n", regval);
regval = getreg32(STM32_GPIOB_AFRH);
spiinfo("B_AFRH:%08x\n", regval);
/* port D */
regval = getreg32(STM32_GPIOD_MODER);
spiinfo("D_MODER:%08x\n", regval);
regval = getreg32(STM32_GPIOD_OTYPER);
spiinfo("D_OTYPER:%08x\n", regval);
regval = getreg32(STM32_GPIOD_OSPEED);
spiinfo("D_OSPEED:%08x\n", regval);
regval = getreg32(STM32_GPIOD_PUPDR);
spiinfo("D_PUPDR:%08x\n", regval);
regval = getreg32(STM32_GPIOD_AFRL);
spiinfo("D_AFRL:%08x\n", regval);
regval = getreg32(STM32_GPIOD_AFRH);
spiinfo("D_AFRH:%08x\n", regval);
/* port E */
regval = getreg32(STM32_GPIOE_MODER);
spiinfo("E_MODER:%08x\n", regval);
regval = getreg32(STM32F7_GPIOE_OTYPER);
regval = getreg32(STM32_GPIOE_OTYPER);
spiinfo("E_OTYPER:%08x\n", regval);
regval = getreg32(STM32F7_GPIOE_OSPEED);
regval = getreg32(STM32_GPIOE_OSPEED);
spiinfo("E_OSPEED:%08x\n", regval);
regval = getreg32(STM32F7_GPIOE_PUPDR);
regval = getreg32(STM32_GPIOE_PUPDR);
spiinfo("E_PUPDR:%08x\n", regval);
regval = getreg32(STM32F7_GPIOE_AFRL);
regval = getreg32(STM32_GPIOE_AFRL);
spiinfo("E_AFRL:%08x\n", regval);
regval = getreg32(STM32F7_GPIOE_AFRH);
regval = getreg32(STM32_GPIOE_AFRH);
spiinfo("E_AFRH:%08x\n", regval);
}
#endif
@ -2079,9 +2118,7 @@ static int qspi_command(struct qspi_dev_s *dev,
/* Set up the Communications Configuration Register as per command info */
qspi_ccrconfig(priv, &xctn,
QSPICMD_ISWRITE(cmdinfo->flags) ? CCR_FMODE_INDWR :
CCR_FMODE_INDRD);
qspi_ccrconfig(priv, &xctn, CCR_FMODE_INDWR);
/* That may be it, unless there is also data to transfer */
@ -2502,7 +2539,6 @@ struct qspi_dev_s *stm32f7_qspi_initialize(int intf)
regval = getreg32(STM32_RCC_AHB3ENR);
regval |= RCC_AHB3ENR_QSPIEN;
putreg32(regval, STM32_RCC_AHB3ENR);
regval = getreg32(STM32_RCC_AHB3ENR);
/* Reset the QSPI peripheral */

12
boards/arm/stm32f7/stm32f746g-disco/Kconfig
View File

@ -5,4 +5,16 @@
if ARCH_BOARD_STM32F746G_DISCO
config STM32F746GDISCO_FLASH
bool "MTD driver for external 16Mbyte N25Q128A FLASH on QSPI port"
default n
select MTD
select MTD_N25QXXX
select MTD_SMART
select FS_SMARTFS
select STM32F7_QUADSPI
select MTD_BYTE_WRITE
---help---
Configures an MTD device for use with the onboard flash
endif # ARCH_BOARD_STM32F746G_DISCO

2
boards/arm/stm32f7/stm32f746g-disco/README.txt
View File

@ -55,7 +55,7 @@ Development Environment
The Development environments for the STM32F746G-DISCO board are identical
to the environments for other STM32F boards. For full details on the
environment options and setup, see the README.txt file in the
boards/stm32f746g-disco directory.
boards/arm/stm32f7/stm32f746g-disco directory.
LEDs and Buttons
================

9
boards/arm/stm32f7/stm32f746g-disco/include/board.h
View File

@ -457,4 +457,13 @@
#define GPIO_LTDC_DE GPIO_LTDC_DE_3
#define GPIO_LTDC_CLK GPIO_LTDC_CLK_3
/* QSPI pinset */
#define GPIO_QSPI_CS GPIO_QUADSPI_BK1_NCS
#define GPIO_QSPI_IO0 GPIO_QUADSPI_BK1_IO0_3
#define GPIO_QSPI_IO1 GPIO_QUADSPI_BK1_IO1_3
#define GPIO_QSPI_IO2 GPIO_QUADSPI_BK1_IO2_1
#define GPIO_QSPI_IO3 GPIO_QUADSPI_BK1_IO3_2
#define GPIO_QSPI_SCK GPIO_QUADSPI_CLK
#endif /* __BOARDS_ARM_STM32F7_STM32F746G_DISCO_INCLUDE_BOARD_H */

6
boards/arm/stm32f7/stm32f746g-disco/scripts/Make.defs
View File

@ -129,3 +129,9 @@ endif
HOSTINCLUDES = -I.
HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe
HOSTLDFLAGS =
ifneq ($(WINTOOL),y)
define DOWNLOAD
$(Q) st-flash write nuttx.bin 0x8000000
endef
endif

4
boards/arm/stm32f7/stm32f746g-disco/src/Makefile
View File

@ -76,4 +76,8 @@ ifeq ($(CONFIG_INPUT_FT5X06),y)
CSRCS += stm32_touchscreen.c
endif
ifeq ($(CONFIG_MTD_N25QXXX),y)
CSRCS += stm32_n25q.c
endif
include $(TOPDIR)/boards/Board.mk

8
boards/arm/stm32f7/stm32f746g-disco/src/stm32_bringup.c
View File

@ -139,6 +139,14 @@ int stm32_bringup(void)
}
#endif
#ifdef CONFIG_MTD_N25QXXX
ret = stm32_n25qxxx_setup();
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: stm32_n25qxxx_setup failed: %d\n", ret);
}
#endif
UNUSED(ret); /* May not be used */
return OK;
}

136
boards/arm/stm32f7/stm32f746g-disco/src/stm32_n25q.c Normal file
View File

@ -0,0 +1,136 @@
/****************************************************************************
* boards/arm/stm32f7/stm32f746g-disco/src/stm32_n25.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <sys/mount.h>
#include <stdio.h>
#include <syslog.h>
#include <errno.h>
#include <debug.h>
#include <string.h>
#include <stdlib.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>
#include <arch/board/board.h>
#include <nuttx/mtd/mtd.h>
#include <nuttx/drivers/drivers.h>
#include <nuttx/drivers/ramdisk.h>
#ifdef CONFIG_FS_NXFFS
#include <nuttx/fs/nxffs.h>
#endif
#ifdef CONFIG_FS_SMARTFS
#include <nuttx/fs/smart.h>
#endif
#include "stm32f746g-disco.h"
#include "stm32_qspi.h"
#define HAVE_N25QXXX_NXFFS
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_n25qxxx_setup
*
* Description:
* This function is called by board-bringup logic to configure the
* flash device.
*
* Returned Value:
* Zero is returned on success. Otherwise, a negated errno value is
* returned to indicate the nature of the failure.
*
****************************************************************************/
int stm32_n25qxxx_setup(void)
{
int ret = -1;
FAR struct qspi_dev_s *qspi_dev = stm32f7_qspi_initialize(0);
if (!qspi_dev)
{
_err("ERROR: Failed to initialize W25 minor %d: %d\n",
0, ret);
;
return -1;
}
FAR struct mtd_dev_s *mtd_dev = n25qxxx_initialize(qspi_dev, true);
if (!mtd_dev)
{
_err("ERROR: n25qxxx_initialize() failed!\n");
return -1;
}
#ifdef HAVE_N25QXXX_NXFFS
/* Initialize to provide NXFFS on the N25QXXX MTD interface */
ret = nxffs_initialize(mtd_dev);
if (ret < 0)
{
_err("ERROR: NXFFS initialization failed: %d\n", ret);
return ret;
}
ret = mount(NULL, "/mnt/nxffs", "nxffs", 0, NULL);
if (ret < 0)
{
_err("ERROR: Failed to mount the NXFFS volume: %d\n", errno);
return ret;
}
#endif
return 0;
}

4
boards/arm/stm32f7/stm32f746g-disco/src/stm32f746g-disco.h
View File

@ -212,6 +212,10 @@ void stm32_disablefmc(void);
int stm32_tsc_setup(int minor);
#endif
#ifdef CONFIG_MTD_N25QXXX
int stm32_n25qxxx_setup(void);
#endif
#endif /* __ASSEMBLY__ */
#endif /* __BOARDS_ARM_STM32F7_STM32F746G_DISCO_SRC_STM32F746G_DISCO_H */