SAMA5 PWM: PWM driver is now functional
This commit is contained in:
Gregory Nutt
parent
27c8c83b91
commit
e231270215
@ -5979,3 +5979,6 @@
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no errors (2013-11-6).
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* configs/sama5d3x-ek: Add support for the PWM test for the
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SAMA5D3x-EK board (2013-11-6).
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* arch/arm/src/sama5/sam_pwm.c and .h: SAMA5 PWM driver is now
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function (2013-11-7).
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@ -471,7 +471,7 @@ struct sam_pwm_s
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/* Register access */
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#ifdef CONFIG_SAMA5_PWM_REGDEBUG
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static bool pwm_checkreg(FAR struct sam_dev_s *chan, bool wr, uint32_t regval,
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static bool pwm_checkreg(FAR struct sam_pwm_s *chan, bool wr, uint32_t regval,
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uintptr_t regaddr);
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#else
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# define pwm_checkreg(chan,wr,regval,regaddr) (false)
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@ -693,7 +693,7 @@ static struct sam_pwm_chan_s g_pwm_chan3 =
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****************************************************************************/
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#ifdef CONFIG_SAMA5_PWM_REGDEBUG
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static bool pwm_checkreg(struct sam_pwm_chan_s *pwm, bool wr, uint32_t regval,
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static bool pwm_checkreg(FAR struct sam_pwm_s *pwm, bool wr, uint32_t regval,
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uintptr_t regaddr)
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{
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if (wr == pwm->wr && /* Same kind of access? */
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@ -747,26 +747,40 @@ static bool pwm_checkreg(struct sam_pwm_chan_s *pwm, bool wr, uint32_t regval,
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static uint32_t pwm_getreg(struct sam_pwm_chan_s *chan, int offset)
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{
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#ifdef PWM_SINGLE
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uintptr_t regaddr;
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uint32_t regval;
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#ifdef PWM_SINGLE
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regaddr = SAM_PWMC_VBASE + offset;
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#else
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struct sam_pwm_chan_s *pwm = chan->pwm;
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regaddr = pwm->base + offset;
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#endif
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regval = getreg32(regaddr);
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regval = getreg32(regaddr);
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#ifdef CONFIG_SAMA5_PWM_REGDEBUG
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if (pwm_checkreg(chan->pwm, false, regval, regaddr))
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if (pwm_checkreg(&g_pwm, false, regval, regaddr))
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{
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lldbg("%08x->%08x\n", regaddr, regval);
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}
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#endif
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return regval;
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#else
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struct sam_pwm_chan_s *pwm = chan->pwm;
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uintptr_t regaddr;
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uint32_t regval;
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regaddr = pwm->base + offset;
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regval = getreg32(regaddr);
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#ifdef CONFIG_SAMA5_PWM_REGDEBUG
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if (pwm_checkreg(pwm, false, regval, regaddr))
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{
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lldbg("%08x->%08x\n", regaddr, regval);
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}
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#endif
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return regval;
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#endif
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}
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/****************************************************************************
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@ -793,7 +807,11 @@ static uint32_t pwm_chan_getreg(struct sam_pwm_chan_s *chan, int offset)
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regval = getreg32(regaddr);
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#ifdef CONFIG_SAMA5_PWM_REGDEBUG
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#ifdef PWM_SINGLE
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if (pwm_checkreg(&g_pwm, false, regval, regaddr))
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#else
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if (pwm_checkreg(chan->pwm, false, regval, regaddr))
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#endif
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{
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lldbg("%08x->%08x\n", regaddr, regval);
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}
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@ -817,25 +835,35 @@ static uint32_t pwm_chan_getreg(struct sam_pwm_chan_s *chan, int offset)
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*
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****************************************************************************/
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static void pwm_putreg(struct sam_pwm_chan_s *chan, int offset, uint32_t regval)
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static void pwm_putreg(struct sam_pwm_chan_s *chan, int offset,
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uint32_t regval)
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{
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uintptr_t regaddr;
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#ifdef PWM_SINGLE
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regaddr = SAM_PWMC_VBASE + offset;
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#else
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struct sam_pwm_chan_s *pwm = chan->pwm;
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regaddr = pwm->base + offset;
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#endif
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uintptr_t regaddr = SAM_PWMC_VBASE + offset;
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#ifdef CONFIG_SAMA5_PWM_REGDEBUG
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if (pwm_checkreg(chan->pwm, true, regval, regaddr))
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if (pwm_checkreg(&g_pwm, true, regval, regaddr))
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{
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lldbg("%08x<-%08x\n", regaddr, regval);
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}
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#endif
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putreg32(regval, regaddr);
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#else
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struct sam_pwm_chan_s *pwm = chan->pwm;
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uintptr_t regaddr = pwm->base + offset;
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#ifdef CONFIG_SAMA5_PWM_REGDEBUG
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if (pwm_checkreg(pwm, true, regval, regaddr))
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{
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lldbg("%08x<-%08x\n", regaddr, regval);
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}
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#endif
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putreg32(regval, regaddr);
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#endif
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}
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/****************************************************************************
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@ -853,12 +881,17 @@ static void pwm_putreg(struct sam_pwm_chan_s *chan, int offset, uint32_t regval)
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*
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****************************************************************************/
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static void pwm_chan_putreg(struct sam_pwm_chan_s *chan, int offset, uint32_t regval)
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static void pwm_chan_putreg(struct sam_pwm_chan_s *chan, int offset,
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uint32_t regval)
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{
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uintptr_t regaddr = chan->base + offset;
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#ifdef CONFIG_SAMA5_PWM_REGDEBUG
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#ifdef PWM_SINGLE
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if (pwm_checkreg(&g_pwm, true, regval, regaddr))
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#else
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if (pwm_checkreg(chan->pwm, true, regval, regaddr))
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#endif
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{
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lldbg("%08x<-%08x\n", regaddr, regval);
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}
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@ -885,57 +918,57 @@ static void pwm_chan_putreg(struct sam_pwm_chan_s *chan, int offset, uint32_t re
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static void pwm_dumpregs(struct sam_pwm_chan_s *chan, FAR const char *msg)
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{
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pwmvdbg("PWM: %s\n", msg);
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pwmvdbg(" CLK: %04x SR: %04x IMR1: %04x ISR1: %04x\n",
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pwmvdbg(" CLK: %08x SR: %08x IMR1: %08x ISR1: %08x\n",
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pwm_getreg(chan, SAM_PWM_CLK_OFFSET),
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pwm_getreg(chan, SAM_PWM_SR_OFFSET),
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pwm_getreg(chan, SAM_PWM_IMR1_OFFSET),
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pwm_getreg(chan, SAM_PWM_ISR1_OFFSET));
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pwmvdbg(" SCM: %04x SCUC: %04x SCUP: %04x IMR2: %04x\n",
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pwmvdbg(" SCM: %08x SCUC: %08x SCUP: %08x IMR2: %08x\n",
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pwm_getreg(chan, SAM_PWM_SCM_OFFSET),
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pwm_getreg(chan, SAM_PWM_SCUC_OFFSET),
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pwm_getreg(chan, SAM_PWM_SCUP_OFFSET),
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pwm_getreg(chan, SAM_PWM_IMR2_OFFSET));
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pwmvdbg(" ISR2: %04x OOV: %04x OS: %04x FMR: %04x\n",
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pwmvdbg(" ISR2: %08x OOV: %08x OS: %08x FMR: %08x\n",
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pwm_getreg(chan, SAM_PWM_ISR2_OFFSET),
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pwm_getreg(chan, SAM_PWM_OOV_OFFSET),
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pwm_getreg(chan, SAM_PWM_OS_OFFSET),
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pwm_getreg(chan, SAM_PWM_FMR_OFFSET));
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pwmvdbg(" FSR: %04x FPV: %04x FPE: %04x ELMR0: %04x\n",
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pwmvdbg(" FSR: %08x FPV: %08x FPE: %08x ELMR0: %08x\n",
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pwm_getreg(chan, SAM_PWM_FSR_OFFSET),
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pwm_getreg(chan, SAM_PWM_FPV_OFFSET),
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pwm_getreg(chan, SAM_PWM_FPE_OFFSET),
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pwm_getreg(chan, SAM_PWM_ELMR0_OFFSET));
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pwmvdbg(" ELMR1: %04x SMMR: %04x WPSR: %04x\n",
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pwmvdbg(" ELMR1: %08x SMMR: %08x WPSR: %08x\n",
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pwm_getreg(chan, SAM_PWM_ELMR1_OFFSET),
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pwm_getreg(chan, SAM_PWM_SMMR_OFFSET),
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pwm_getreg(chan, SAM_PWM_WPSR_OFFSET));
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pwmvdbg(" CMPV0: %04x CMPM0: %04x CMPV1: %04x CMPM1: %04x\n",
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pwmvdbg(" CMPV0: %08x CMPM0: %08x CMPV1: %08x CMPM1: %08x\n",
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pwm_getreg(chan, SAM_PWM_CMPV0_OFFSET),
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pwm_getreg(chan, SAM_PWM_CMPM0_OFFSET),
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pwm_getreg(chan, SAM_PWM_CMPV1_OFFSET),
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pwm_getreg(chan, SAM_PWM_CMPM1_OFFSET));
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pwmvdbg(" CMPV2: %04x CMPM2: %04x CMPV3: %04x CMPM3: %04x\n",
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pwmvdbg(" CMPV2: %08x CMPM2: %08x CMPV3: %08x CMPM3: %08x\n",
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pwm_getreg(chan, SAM_PWM_CMPV2_OFFSET),
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pwm_getreg(chan, SAM_PWM_CMPM2_OFFSET),
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pwm_getreg(chan, SAM_PWM_CMPV3_OFFSET),
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pwm_getreg(chan, SAM_PWM_CMPM3_OFFSET));
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pwmvdbg(" CMPV4: %04x CMPM4: %04x CMPV5: %04x CMPM5: %04x\n",
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pwmvdbg(" CMPV4: %08x CMPM4: %08x CMPV5: %08x CMPM5: %08x\n",
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pwm_getreg(chan, SAM_PWM_CMPV4_OFFSET),
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pwm_getreg(chan, SAM_PWM_CMPM4_OFFSET),
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pwm_getreg(chan, SAM_PWM_CMPV5_OFFSET),
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pwm_getreg(chan, SAM_PWM_CMPM5_OFFSET));
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pwmvdbg(" CMPV6: %04x CMPM6: %04x CMPV7: %04x CMPM7: %04x\n",
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pwmvdbg(" CMPV6: %08x CMPM6: %08x CMPV7: %08x CMPM7: %08x\n",
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pwm_getreg(chan, SAM_PWM_CMPV6_OFFSET),
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pwm_getreg(chan, SAM_PWM_CMPM6_OFFSET),
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pwm_getreg(chan, SAM_PWM_CMPV7_OFFSET),
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pwm_getreg(chan, SAM_PWM_CMPM7_OFFSET));
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pwmvdbg("Channel %d: %s\n", chan->channel, msg);
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pwmvdbg(" CMR: %04x CDTY: %04x CPRD: %04x CCNT: %04x\n",
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pwmvdbg(" CMR: %08x CDTY: %08x CPRD: %08x CCNT: %08x\n",
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pwm_chan_getreg(chan, SAM_PWM_CMR_OFFSET),
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pwm_chan_getreg(chan, SAM_PWM_CDTY_OFFSET),
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pwm_chan_getreg(chan, SAM_PWM_CPRD_OFFSET),
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pwm_chan_getreg(chan, SAM_PWM_CCNT_OFFSET));
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pwmvdbg(" CT: %04x\n",
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pwmvdbg(" CT: %08x\n",
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pwm_chan_getreg(chan, SAM_PWM_DT_OFFSET));
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}
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#endif
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@ -1118,7 +1151,7 @@ static int pwm_start(FAR struct pwm_lowerhalf_s *dev,
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* the CPRDUPD) register.
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*/
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cprd = (info->frequency + (fsrc >> 1)) / fsrc;
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cprd = (fsrc + (info->frequency >> 1)) / info->frequency;
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pwm_chan_putreg(chan, SAM_PWM_CPRD_OFFSET, cprd);
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/* Set the PWM duty. Since the PWM is disabled, we can write directly
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@ -1128,12 +1161,13 @@ static int pwm_start(FAR struct pwm_lowerhalf_s *dev,
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regval = b16toi(info->duty * cprd + b16HALF);
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if (regval > cprd)
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{
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/* Rounding could cause the duty value to exceed CPRD */
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/* Rounding up could cause the duty value to exceed CPRD (?) */
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regval = cprd;
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}
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pwm_chan_putreg(chan, SAM_PWM_CDTY_OFFSET, regval);
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pwmvdbg("Fsrc=%d cprd=%d cdty=%d\n", fsrc, cprd, regval);
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/* Enable the channel */
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@ -852,36 +852,40 @@ SAMA5 PWM Support
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Where x=0..3.
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Care must be taken because all PWM output pins conflict with some other
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usage of the pin by other devices:
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usage of the pin by other devices. Furthermore, many of these pins have
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not been brought out to an external connector:
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-----+---+---+----+------+----------------
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PWM PIN PER PIO I/O CONFLICTS
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-----+---+---+----+------+----------------
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PWM0 FI B PC28 J2.30 SPI1, ISI
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H B PB0 --- GMAC
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B PA20 J1.14 LCDC, ISI
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L B PB1 --- GMAC
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B PA21 J1.16 LCDC, ISI
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-----+---+---+----+------+----------------
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PWM1 FI B PC31 J2.36 HDMI
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H B PB4 --- GMAC
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B PA22 J1.18 LCDC, ISI
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L B PB5 --- GMAC
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B PE31 J3.20 ISI, HDMI
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B PA23 J1.20 LCDC, ISI
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-----+---+---+----+------+----------------
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PWM2 FI B PC29 J2.29 UART0, ISI, HDMI
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H C PD5 --- HSMCI0
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B PB8 --- GMAC
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L C PD6 --- HSMCI0
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B PB9 --- GMAC
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-----+---+---+----+------+----------------
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PWM3 FI C PD16 --- SPI0, Audio
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H C PD7 --- HSMCI0
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B PB12 J3.7 GMAC
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L C PD8 --- HSMCI0
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B PB13 --- GMAC
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-----+---+---+----+--------------------
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PWM PIN PER PIO CONFLICTS
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-----+---+---+----+--------------------
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PWM0 FI B PC28 SPI1, ISI
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H B PB0 GMAC
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B PA20 LCDC, ISI
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L B PB1 GMAC
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B PA21 LCDC, ISI
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-----+---+---+----+--------------------
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PWM1 FI B PC31 HDMI
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H B PB4 GMAC
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B PA22 LCDC, ISI
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L B PB5 GMAC
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B PE31 ISI, HDMI
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B PA23 LCDC, ISI
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-----+---+---+----+--------------------
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PWM2 FI B PC29 UART0, ISI, HDMI
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H C PD5 HSMCI0
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B PB8 GMAC
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L C PD6 HSMCI0
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B PB9 GMAC
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-----+---+---+----+--------------------
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PWM3 FI C PD16 SPI0, Audio
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H C PD7 HSMCI0
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B PB12 GMAC
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L C PD8 HSMCI0
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B PB13 GMAC
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-----+---+---+----+--------------------
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See configs/sama5d3x-ek/include/board.h for all of the default PWM
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pin selections. I used PWM channel 0, pins PA20 and PA21 for testing.
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Clocking is addressed in the next paragraph.
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@ -889,7 +893,7 @@ SAMA5 PWM Support
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-----------------------
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PWM Channels can be clocked from either a coarsely divided divided down
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MCK or from a custom frequency from PWM CLKA and/or CLKB. If you want
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to use CLKA or CLKB, you must enable and configuratino them.
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to use CLKA or CLKB, you must enable and configure them.
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System Type -> PWM Configuration
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CONFIG_SAMA5_PWM_CLKA=y
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@ -901,7 +905,7 @@ SAMA5 PWM Support
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for that channel:
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System Type -> PWM Configuration
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CONFIG_SAMA5_PWM_CHANx_CLKA=y : Pick one of MCK, CLKA, or CLKB
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CONFIG_SAMA5_PWM_CHANx_CLKA=y : Pick one of MCK, CLKA, or CLKB (only)
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CONFIG_SAMA5_PWM_CHANx_CLKB=y
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CONFIG_SAMA5_PWM_CHANx_MCK=y
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CONFIG_SAMA5_PWM_CHANx_MCKDIV=128 : If MCK is selected, then the MCK divider must
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@ -921,6 +925,21 @@ SAMA5 PWM Support
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CONFIG_EXAMPLES_PWM_DEVPATH="/dev/pwm0"
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CONFIG_EXAMPLES_PWM_FREQUENCY=100
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Usage of the example is straightforward:
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nsh> pwm -h
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Usage: pwm [OPTIONS]
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Arguments are "sticky". For example, once the PWM frequency is
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specified, that frequency will be re-used until it is changed.
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"sticky" OPTIONS include:
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[-p devpath] selects the PWM device. Default: /dev/pwm0 Current: /dev/pwm0
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[-f frequency] selects the pulse frequency. Default: 100 Hz Current: 100 Hz
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[-d duty] selects the pulse duty as a percentage. Default: 50 % Current: 50 %
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[-t duration] is the duration of the pulse train in seconds. Default: 5 Current: 5
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[-h] shows this message and exits
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OV2640 Camera interface
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=======================
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@ -178,56 +178,88 @@
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/* PWM. There are no dedicated PWM output pins available to the user for PWM
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* testing. Care must be taken because all PWM output pins conflict with some other
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* usage of the pin by other devices:
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* usage of the pin by other devices. Furthermore, many of these pins have not been
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* brought out to an external connector:
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*
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* -----+---+---+----+--------------------
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* PWM PIN PER PIO CONFLICTS
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* -----+---+---+----+--------------------
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* PWM0 FI B PC28 SPI1, ISI
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* H B PB0 GMAC
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* B PA20 LCDC, ISI
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* L B PB1 GMAC
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* B PA21 LCDC, ISI
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* -----+---+---+----+--------------------
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* PWM1 FI B PC31 HDMI
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* H B PB4 GMAC
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* B PA22 LCDC, ISI
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* L B PB5 GMAC
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* B PE31 ISI, HDMI
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* B PA23 LCDC, ISI
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* -----+---+---+----+--------------------
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* PWM2 FI B PC29 UART0, ISI, HDMI
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* H C PD5 HSMCI0
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* B PB8 GMAC
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* L C PD6 HSMCI0
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* B PB9 GMAC
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* -----+---+---+----+--------------------
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* PWM3 FI C PD16 SPI0, Audio
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* H C PD7 HSMCI0
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* B PB12 GMAC
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* L C PD8 HSMCI0
|
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* B PB13 GMAC
|
||||
* -----+---+---+----+--------------------
|
||||
* -----+---+---+----+------+----------------
|
||||
* PWM PIN PER PIO I/O CONFLICTS
|
||||
* -----+---+---+----+------+----------------
|
||||
* PWM0 FI B PC28 J2.30 SPI1, ISI
|
||||
* H B PB0 --- GMAC
|
||||
* B PA20 J1.14 LCDC, ISI
|
||||
* L B PB1 --- GMAC
|
||||
* B PA21 J1.16 LCDC, ISI
|
||||
* -----+---+---+----+------+----------------
|
||||
* PWM1 FI B PC31 J2.36 HDMI
|
||||
* H B PB4 --- GMAC
|
||||
* B PA22 J1.18 LCDC, ISI
|
||||
* L B PB5 --- GMAC
|
||||
* B PE31 J3.20 ISI, HDMI
|
||||
* B PA23 J1.20 LCDC, ISI
|
||||
* -----+---+---+----+------+----------------
|
||||
* PWM2 FI B PC29 J2.29 UART0, ISI, HDMI
|
||||
* H C PD5 --- HSMCI0
|
||||
* B PB8 --- GMAC
|
||||
* L C PD6 --- HSMCI0
|
||||
* B PB9 --- GMAC
|
||||
* -----+---+---+----+------+----------------
|
||||
* PWM3 FI C PD16 --- SPI0, Audio
|
||||
* H C PD7 --- HSMCI0
|
||||
* B PB12 J3.7 GMAC
|
||||
* L C PD8 --- HSMCI0
|
||||
* B PB13 --- GMAC
|
||||
* -----+---+---+----+------+----------------
|
||||
*/
|
||||
|
||||
#if !defined(CONFIG_SAMA5_GMAC)
|
||||
/* PWM channel 0:
|
||||
*
|
||||
* PA20 and PA21 can be used if the LCDC or ISI are not selected. These outputs are
|
||||
* available on J1, pins 14 and 16, respectively.
|
||||
*
|
||||
* If the GMAC is not selected, then PB0 and PB1 could also be used. However,
|
||||
* these pins are not available at the I/O expansion connectors.
|
||||
*/
|
||||
|
||||
#if !defined(CONFIG_SAMA5_LCDC) && !defined(CONFIG_SAMA5_ISI)
|
||||
# define PIO_PWM0_H PIO_PWM0_H_2
|
||||
# define PIO_PWM0_L PIO_PWM0_L_2
|
||||
#elif !defined(CONFIG_SAMA5_GMAC)
|
||||
# define PIO_PWM0_H PIO_PWM0_H_1
|
||||
# define PIO_PWM0_L PIO_PWM0_L_1
|
||||
#elif !defined(CONFIG_SAMA5_LCDC) && !defined(CONFIG_SAMA5_ISI)
|
||||
# define PIO_PWM0_H PIO_PWM0_H_2
|
||||
# define PIO_PWM0_L PIO_PWM0_L_3
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_SAMA5_GMAC)
|
||||
# define PIO_PWM1_H PIO_PWM1_H_1
|
||||
# define PIO_PWM1_L PIO_PWM1_L_1
|
||||
#elif !defined(CONFIG_SAMA5_LCDC) && !defined(CONFIG_SAMA5_ISI)
|
||||
/* PWM channel 1:
|
||||
*
|
||||
* PA22 and PA23 can be used if the LCDC or ISI are not selected. These outputs are
|
||||
* available on J1, pins 18 and 20, respectively.
|
||||
*
|
||||
* PE31 can be used if the ISI is not selected (and the HDMI is not being used).
|
||||
* That signal is available at J3 pin 20.
|
||||
*
|
||||
* If the GMAC is not selected, then PB4 and PB5 could also be used. However,
|
||||
* these pins are not available at the I/O expansion connectors.
|
||||
*/
|
||||
|
||||
#if !defined(CONFIG_SAMA5_LCDC) && !defined(CONFIG_SAMA5_ISI)
|
||||
# define PIO_PWM1_H PIO_PWM1_H_2
|
||||
#elif !defined(CONFIG_SAMA5_GMAC)
|
||||
# define PIO_PWM1_H PIO_PWM1_H_1
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_SAMA5_LCDC) && !defined(CONFIG_SAMA5_ISI)
|
||||
# define PIO_PWM1_L PIO_PWM1_L_3
|
||||
#elif !defined(CONFIG_SAMA5_ISI)
|
||||
# define PIO_PWM1_L PIO_PWM1_L_2
|
||||
#elif !defined(CONFIG_SAMA5_GMAC)
|
||||
# define PIO_PWM1_L PIO_PWM1_L_1
|
||||
#endif
|
||||
|
||||
/* PWM channel 2:
|
||||
*
|
||||
* None of the output pin options are available at any of the I/O expansion
|
||||
* connectors for PWM channel 2
|
||||
*/
|
||||
|
||||
#if !defined(CONFIG_SAMA5_HSMCI0)
|
||||
# define PIO_PWM2_H PIO_PWM2_H_1
|
||||
# define PIO_PWM2_L PIO_PWM2_L_1
|
||||
@ -236,12 +268,18 @@
|
||||
# define PIO_PWM2_L PIO_PWM2_L_2
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_SAMA5_HSMCI0)
|
||||
# define PIO_PWM3_H PIO_PWM3_H_1
|
||||
# define PIO_PWM3_L PIO_PWM3_L_1
|
||||
#elif !defined(CONFIG_SAMA5_GMAC)
|
||||
/* PWM channel 3:
|
||||
*
|
||||
* If the GMAC is not selected, then PB12 can used and is available at J3 pin 7.
|
||||
* None of the other output pins are accessible at the I/O expansion connectors.
|
||||
*/
|
||||
|
||||
#if !defined(CONFIG_SAMA5_GMAC)
|
||||
# define PIO_PWM3_H PIO_PWM3_H_2
|
||||
# define PIO_PWM3_L PIO_PWM3_L_2
|
||||
#elif !defined(CONFIG_SAMA5_HSMCI0)
|
||||
# define PIO_PWM3_H PIO_PWM3_H_1
|
||||
# define PIO_PWM3_L PIO_PWM3_L_1
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
|
||||
Loading…
Reference in New Issue
Block a user