From e2905bc69cff5046b274018cc9c1d92bdaba5cff Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 8 Nov 2019 17:49:29 -0600 Subject: [PATCH] boards/arm/imxrt/imxrt1020-evk: Run all .c and .h files through tools/nxstyle and fix numerous coding violations. This sucks. The submitter of the patch is responsibile for doing this and dumping this on me is shit. --- .../arm/imxrt/imxrt1020-evk/include/board.h | 34 ++--- .../imxrt/imxrt1020-evk/src/imxrt_bringup.c | 1 + .../imxrt/imxrt1020-evk/src/imxrt_buttons.c | 1 + .../src/imxrt_flexspi_nor_boot.c | 2 +- .../src/imxrt_flexspi_nor_flash.c | 140 ++++++++++-------- .../src/imxrt_flexspi_nor_flash.h | 2 +- 6 files changed, 100 insertions(+), 80 deletions(-) diff --git a/boards/arm/imxrt/imxrt1020-evk/include/board.h b/boards/arm/imxrt/imxrt1020-evk/include/board.h index ce185028a7..5b32cbaee1 100644 --- a/boards/arm/imxrt/imxrt1020-evk/include/board.h +++ b/boards/arm/imxrt/imxrt1020-evk/include/board.h @@ -78,7 +78,7 @@ * IMXRT_PERCLK_PODF_DIVIDER = 2 * 62.5Mhz = 125Mhz / 2 * - * SEMC_CLK_ROOT = PERIPH_CLK / IMXRT_SEMC_PODF_DIVIDER + * SEMC_CLK_ROOT = PERIPH_CLK / IMXRT_SEMC_PODF_DIVIDER * IMXRT_SEMC_PODF_DIVIDER = 4 * 125Mhz = 500 / 4 * @@ -132,7 +132,8 @@ * * -------------------- ----------------------------- ---- * SYMBOL Meaning LED1 - * -------------------- ----------------------------- ---- */ + * -------------------- ----------------------------- ---- + */ #define LED_STARTED 0 /* NuttX has been started OFF */ #define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF */ @@ -144,8 +145,7 @@ #define LED_PANIC 7 /* The system has crashed FLASH */ #undef LED_IDLE /* Not used */ -/* - * The intention is that if the LED is statically on, NuttX has successfully +/* The intention is that if the LED is statically on, NuttX has successfully * booted and is, apparently, running normally. If the LED is flashing at * approximately 2Hz, then a fatal error has been detected and the system has * halted. @@ -194,9 +194,7 @@ #define BOARD_USDHC_SD4MODE_PRESCALER USDHC_SYSCTL_SDCLKFS_DIV8 #define BOARD_USDHC_SD4MODE_DIVISOR USDHC_SYSCTL_DVS_DIV(1) -/****************************************************************************/ -/*********************************** PINNING ********************************/ -/****************************************************************************/ +/* Pinning ******************************************************************/ /* LEDs *********************************************************************/ @@ -207,7 +205,7 @@ #define GPIO_SWWAKE (GPIO_INTERRUPT | GPIO_INT_FALLINGEDGE | | IOMUX_SWWAKE_DEFAULT \ GPIO_PORT5 | GPIO_PIN0 ) /* WAKE */ - + /* ETH Disambiguation ********************************************************/ #define GPIO_ENET_INT (IOMUX_ENET_INT_DEFAULT | GPIO_INTERRUPT | \ @@ -215,11 +213,13 @@ #define GPIO_ENET_IRQ IMXRT_IRQ_GPIO1_12 /* Make sure these entries match to allow interrupts to be present */ + #define GPIO_ENET_GRP IMXRT_GPIO1_16_31_IRQ -#ifndef GPIO_ENET_GRP -#ifdef CONFIG_IMXRT_ENET -#error GPIO_ENET_IRQ Host IRQ not defined! -#endif +# +ifndef GPIO_ENET_GRP +# ifdef CONFIG_IMXRT_ENET +# error GPIO_ENET_IRQ Host IRQ not defined! +# endif #endif #define GPIO_ENET_MDIO GPIO_ENET_MDIO_1|IOMUX_ENET_MDIO_DEFAULT @@ -231,8 +231,8 @@ #define GPIO_ENET_RX_DATA01 GPIO_ENET_RX_DATA01_2|IOMUX_ENET_DATA_DEFAULT #define GPIO_ENET_TX_DATA00 GPIO_ENET_TX_DATA00_2|IOMUX_ENET_DATA_DEFAULT #define GPIO_ENET_TX_DATA01 GPIO_ENET_TX_DATA01_2|IOMUX_ENET_DATA_DEFAULT -#define GPIO_ENET_RST (GPIO_OUTPUT | IOMUX_ENET_RST_DEFAULT | GPIO_OUTPUT_ZERO | \ - GPIO_PORT1 | GPIO_PIN4 ) /* AD_B0_04, Inverted logic */ +#define GPIO_ENET_RST (GPIO_OUTPUT | IOMUX_ENET_RST_DEFAULT | GPIO_OUTPUT_ZERO | \ + GPIO_PORT1 | GPIO_PIN4 ) /* AD_B0_04, Inverted logic */ /* LPI2Cs *******************************************************************/ @@ -263,8 +263,8 @@ #define PIN_USDHC1_D3 (GPIO_USDHC1_DATA3_1 | IOMUX_USDHC1_DATAX_DEFAULT) /* SD_B0_01 */ #define PIN_USDHC1_DCLK (GPIO_USDHC1_CLK_1 | IOMUX_USDHC1_CLK_DEFAULT) /* SD_B0_03 */ #define PIN_USDHC1_CMD (GPIO_USDHC1_CMD_1 | IOMUX_USDHC1_CMD_DEFAULT) /* SD_B0_02 */ -#define PIN_USDHC1_CD ( IOMUX_VSD_DEFAULT | \ - GPIO_PORT3 | GPIO_PIN19 ) /* SD_B0_06 */ +#define PIN_USDHC1_CD (IOMUX_VSD_DEFAULT | \ + GPIO_PORT3 | GPIO_PIN19 ) /* SD_B0_06 */ #define GPIO_VSDHIGH (GPIO_OUTPUT | IOMUX_VSD_DEFAULT | GPIO_OUTPUT_ONE | \ GPIO_PORT1 | GPIO_PIN22) /* AD_B1_07 */ #define PIN_USDHC1_PWREN (GPIO_OUTPUT | IOMUX_VSD_DEFAULT | GPIO_OUTPUT_ONE | \ @@ -296,7 +296,7 @@ extern "C" #endif /************************************************************************************ - * Public Functions + * Public Function Prototypes ************************************************************************************/ #undef EXTERN diff --git a/boards/arm/imxrt/imxrt1020-evk/src/imxrt_bringup.c b/boards/arm/imxrt/imxrt1020-evk/src/imxrt_bringup.c index 08cf103252..d3bf932615 100644 --- a/boards/arm/imxrt/imxrt1020-evk/src/imxrt_bringup.c +++ b/boards/arm/imxrt/imxrt1020-evk/src/imxrt_bringup.c @@ -139,6 +139,7 @@ static int nsh_sdmmc_initialize(void) ret); } } + return OK; } diff --git a/boards/arm/imxrt/imxrt1020-evk/src/imxrt_buttons.c b/boards/arm/imxrt/imxrt1020-evk/src/imxrt_buttons.c index e5647f4879..82c2294867 100644 --- a/boards/arm/imxrt/imxrt1020-evk/src/imxrt_buttons.c +++ b/boards/arm/imxrt/imxrt1020-evk/src/imxrt_buttons.c @@ -106,6 +106,7 @@ uint8_t board_buttons(void) { ret |= BUTTON_WAKE_BIT; } + return ret; } diff --git a/boards/arm/imxrt/imxrt1020-evk/src/imxrt_flexspi_nor_boot.c b/boards/arm/imxrt/imxrt1020-evk/src/imxrt_flexspi_nor_boot.c index f753fc3dd1..d5c9943042 100644 --- a/boards/arm/imxrt/imxrt1020-evk/src/imxrt_flexspi_nor_boot.c +++ b/boards/arm/imxrt/imxrt1020-evk/src/imxrt_flexspi_nor_boot.c @@ -42,6 +42,7 @@ /**************************************************************************** * Public Data ****************************************************************************/ + __attribute__((section(".boot_hdr.ivt"))) const struct ivt_s g_image_vector_table = { @@ -63,4 +64,3 @@ const struct boot_data_s g_boot_data = PLUGIN_FLAG, /* Plugin flag */ 0xffffffff /* empty - extra data word */ }; - diff --git a/boards/arm/imxrt/imxrt1020-evk/src/imxrt_flexspi_nor_flash.c b/boards/arm/imxrt/imxrt1020-evk/src/imxrt_flexspi_nor_flash.c index 08fd06557d..e51675ee67 100644 --- a/boards/arm/imxrt/imxrt1020-evk/src/imxrt_flexspi_nor_flash.c +++ b/boards/arm/imxrt/imxrt1020-evk/src/imxrt_flexspi_nor_flash.c @@ -44,11 +44,10 @@ * Public Data ******************************************************************************/ -/* - * This configuration is for an IS25LP064A. There will be slight differences for +/* This configuration is for an IS25LP064A. There will be slight differences for * other chips but it's not as painful or scary as it looks. Just get the flash - * datasheet and work through it slowly to make sure the codes match. You will - * get something minimal up just using an 0x03 read opcode, and you can optimise + * data sheet and work through it slowly to make sure the codes match. You will + * get something minimal up just using an 0x03 read opcode, and you can optimize * for the actual flash you've got from there. * * It's best to not use the QPI because then you lose the ability to communicate @@ -61,26 +60,29 @@ __attribute__((section(".boot_hdr.conf"))) const struct flexspi_nor_config_s g_flash_config = { - .mem_config = + .mem_config = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .read_sample_clksrc = FLASH_READ_SAMPLE_CLK_EXTERNALINPUT_FROM_DQSPAD, - .cs_hold_time = 3u, - .cs_setup_time = 3u, - .column_address_width = 3u, + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .read_sample_clksrc = FLASH_READ_SAMPLE_CLK_EXTERNALINPUT_FROM_DQSPAD, + .cs_hold_time = 3u, + .cs_setup_time = 3u, + .column_address_width = 3u, /* Enable DDR mode, Word addassable, Safe configuration, Differential clock */ - .controller_misc_option = (1u << FLEXSPIMISC_OFFSET_DDR_MODE_EN) | - (1u << FLEXSPIMISC_OFFSET_WORD_ADDRESSABLE_EN) | - (1u << FLEXSPIMISC_OFFSET_SAFECONFIG_FREQ_EN) | - (1u << FLEXSPIMISC_OFFSET_DIFFCLKEN), - .sflash_pad_type = SERIAL_FLASH_8PADS, - .serial_clk_freq = FLEXSPI_SERIAL_CLKFREQ_133MHz, - .sflash_a1size = 64u * 1024u * 1024u, - .data_valid_time = {16u, 16u}, - .lookup_table = + .controller_misc_option = (1u << FLEXSPIMISC_OFFSET_DDR_MODE_EN) | + (1u << FLEXSPIMISC_OFFSET_WORD_ADDRESSABLE_EN) | + (1u << FLEXSPIMISC_OFFSET_SAFECONFIG_FREQ_EN) | + (1u << FLEXSPIMISC_OFFSET_DIFFCLKEN), + .sflash_pad_type = SERIAL_FLASH_8PADS, + .serial_clk_freq = FLEXSPI_SERIAL_CLKFREQ_133MHz, + .sflash_a1size = 64u * 1024u * 1024u, + .data_valid_time = + { + 16u, 16u + }, + .lookup_table = { /* Read LUTs */ @@ -89,10 +91,10 @@ const struct flexspi_nor_config_s g_flash_config = FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0), }, }, - .page_size = 512u, - .sector_size = 256u * 1024u, - .blocksize = 256u * 1024u, - .is_uniform_blocksize = 1, + .page_size = 512u, + .sector_size = 256u * 1024u, + .blocksize = 256u * 1024u, + .is_uniform_blocksize = 1, }; #elif defined (CONFIG_IMXRT1020_EVK_QSPI_FLASH) __attribute__((section(".boot_hdr.conf"))) @@ -100,54 +102,70 @@ const struct flexspi_nor_config_s g_flash_config = { .mem_config = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .read_sample_clksrc = FLASH_READ_SAMPLE_CLK_LOOPBACK_INTERNELLY, - .cs_hold_time = 3u, - .cs_setup_time = 3u, - .device_mode_cfg_enable = true, - .device_mode_seq.seq_num= 1, - .device_mode_seq.seq_id = 4, /* These commands set the Quad bit */ - .device_mode_arg = 0x40, /* on the flash to drive 4 pins. */ - .device_type = FLEXSPI_DEVICE_TYPE_SERIAL_NOR, - .sflash_pad_type = SERIAL_FLASH_4PADS, - .serial_clk_freq = FLEXSPI_SERIAL_CLKFREQ_100MHz, - .sflash_a1size = 8u * 1024u * 1024u, - .data_valid_time = {16u, 16u}, - - .lookup_table = + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .read_sample_clksrc = FLASH_READ_SAMPLE_CLK_LOOPBACK_INTERNELLY, + .cs_hold_time = 3u, + .cs_setup_time = 3u, + .device_mode_cfg_enable = true, + .device_mode_seq.seq_num = 1, + .device_mode_seq.seq_id = 4, /* These commands set the Quad bit */ + .device_mode_arg = 0x40, /* on the flash to drive 4 pins. */ + .device_type = FLEXSPI_DEVICE_TYPE_SERIAL_NOR, + .sflash_pad_type = SERIAL_FLASH_4PADS, + .serial_clk_freq = FLEXSPI_SERIAL_CLKFREQ_100MHz, + .sflash_a1size = 8u * 1024u * 1024u, + .data_valid_time = + { + 16u, 16u + }, + .lookup_table = { /* 0 - Quad Input/output read sequence - with optimised XIP support */ - [0]=FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18), - [1]=FLEXSPI_LUT_SEQ(MODE8_SDR, FLEXSPI_4PAD, 0xA0, DUMMY_SDR, FLEXSPI_4PAD, 0x04), - [2]=FLEXSPI_LUT_SEQ(READ_SDR, FLEXSPI_4PAD, 0x04, JMP_ON_CS, 0, 1), + + [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xeb, RADDR_SDR, + FLEXSPI_4PAD, 0x18), + [1] = FLEXSPI_LUT_SEQ(MODE8_SDR, FLEXSPI_4PAD, 0xa0, DUMMY_SDR, + FLEXSPI_4PAD, 0x04), + [2] = FLEXSPI_LUT_SEQ(READ_SDR, FLEXSPI_4PAD, 0x04, JMP_ON_CS, 0, 1), /* 1 - Read Status */ - [1*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x01), - + + [1 * 4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, + FLEXSPI_1PAD, 0x01), + /* 3 - Write Enable */ - [3*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, 0, 0), - + + [3 * 4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, 0, 0), + /* 4 - Write status */ - [4*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01, WRITE_SDR, FLEXSPI_1PAD, 0x1), + + [4 * 4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01, WRITE_SDR, + FLEXSPI_1PAD, 0x1), /* 5 - Erase Sector */ - [5*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD7, RADDR_SDR, FLEXSPI_1PAD, 0x18), - - /* 9 - Page Program */ - [9*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02, RADDR_SDR, FLEXSPI_1PAD, 0x18), - [9*4+1] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x8, STOP, FLEXSPI_1PAD, 0x0), - - /* 11 - Chip Erase */ - [11*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xC7, STOP, FLEXSPI_1PAD, 0x0), + [5 * 4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xd7, RADDR_SDR, + FLEXSPI_1PAD, 0x18), + + /* 9 - Page Program */ + + [9 * 4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02, RADDR_SDR, + FLEXSPI_1PAD, 0x18), + [9 * 4 + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x8, STOP, + FLEXSPI_1PAD, 0x0), + + /* 11 - Chip Erase */ + + [11 * 4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xc7, STOP, + FLEXSPI_1PAD, 0x0), }, }, - - .page_size = 256u, - .sector_size = 4u * 1024u, - .blocksize = 32u * 1024u, - .is_uniform_blocksize = false, + + .page_size = 256u, + .sector_size = 4u * 1024u, + .blocksize = 32u * 1024u, + .is_uniform_blocksize = false, }; #else # error Boot Flash type not chosen! diff --git a/boards/arm/imxrt/imxrt1020-evk/src/imxrt_flexspi_nor_flash.h b/boards/arm/imxrt/imxrt1020-evk/src/imxrt_flexspi_nor_flash.h index 7627226691..1f1cbc4348 100644 --- a/boards/arm/imxrt/imxrt1020-evk/src/imxrt_flexspi_nor_flash.h +++ b/boards/arm/imxrt/imxrt1020-evk/src/imxrt_flexspi_nor_flash.h @@ -228,7 +228,7 @@ enum flexspi_serial_clockmode_e enum flash_read_sample_clk_e { - FLASH_READ_SAMPLE_CLK_LOOPBACK_INTERNELLY= 0, + FLASH_READ_SAMPLE_CLK_LOOPBACK_INTERNELLY = 0, FLASH_READ_SAMPLE_CLK_LOOPBACK_FROM_DQSPAD = 1, FLASH_READ_SAMPLE_CLK_LOOPBACK_FROM_SCKPAD = 2, FLASH_READ_SAMPLE_CLK_EXTERNALINPUT_FROM_DQSPAD = 3,