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Fix some common typos

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This commit is contained in:
Gregory Nutt 2015-08-16 10:59:10 -06:00
parent 9e5e91c204
commit e29220183a
16 changed files with 24 additions and 24 deletions
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2
arch/arm/src/efm32/efm32_usbhost.c
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@ -1171,7 +1171,7 @@ static int efm32_chan_wait(FAR struct efm32_usbhost_s *priv,
/* Loop, testing for an end of transfer condition. The channel 'result'
* was set to EBUSY and 'waiter' was set to true before the transfer; 'waiter'
* will be set to false and 'result' will be set appropriately when the
* tranfer is completed.
* transfer is completed.
*/
do

2
arch/arm/src/lpc17xx/lpc17_gpdma.h
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@ -60,7 +60,7 @@ typedef FAR void *DMA_HANDLE;
* function is called at the completion of the DMA transfer. 'arg' is the
* same 'arg' value that was provided when lpc17_dmastart() was called and
* result indicates the result of the transfer: Zero indicates a successful
* tranfers. On failure, a negated errno is returned indicating the general
* transfers. On failure, a negated errno is returned indicating the general
* nature of the DMA faiure.
*/

2
arch/arm/src/lpc17xx/lpc17_usbdev.c
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@ -2457,7 +2457,7 @@ static int lpc17_dmasetup(struct lpc17_usbdev_s *priv, uint8_t epphy,
dmadesc->size = (uint32_t)packet;
#endif
/* Enable DMA tranfer for this endpoint */
/* Enable DMA transfer for this endpoint */
putreq32(1 << epphy, LPC17_USBDEV_EPDMAEN);

2
arch/arm/src/lpc214x/lpc214x_usbdev.c
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@ -2422,7 +2422,7 @@ static int lpc214x_dmasetup(struct lpc214x_usbdev_s *priv, uint8_t epphy,
dmadesc->size = (uint32_t)packet;
#endif
/* Enable DMA tranfer for this endpoint */
/* Enable DMA transfer for this endpoint */
putreq32(1 << epphy, LPC214X_USBDEV_EPDMAEN);

2
arch/arm/src/nuc1xx/chip/nuc_gcr.h
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@ -356,7 +356,7 @@
# define GCR_REGWRPROT_2 (0x16)
# define GCR_REGWRPROT_3 (0x88)
/* Read: */
#define GCR_REGWRPROT_DIS (1 << 0) /* Bit 0: Register write protectino disable index */
#define GCR_REGWRPROT_DIS (1 << 0) /* Bit 0: Register write protection disable index */
/********************************************************************************************
* Public Types

2
arch/arm/src/sam34/sam_dmac.c
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@ -1225,7 +1225,7 @@ static inline int sam_multiple(struct sam_dma_s *dmach)
* Additionally, the CTRLA DONE bit is asserted when the buffer transfer has completed.
*
* The DMAC transfer continues until the CTRLB register disables the descriptor
* (DSCR bits) registers at the final buffer tranfer.
* (DSCR bits) registers at the final buffer transfer.
*
* Enable error, buffer complete and transfer complete interrupts. We
* don't really need the buffer complete interrupts, but we will take them

4
arch/arm/src/sama5/sam_dmac.c
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@ -1721,7 +1721,7 @@ static inline int sam_multiple(struct sam_dmach_s *dmach)
* buffer transfer has completed.
*
* The DMAC transfer continues until the CTRLB register disables the
* descriptor (DSCR bits) registers at the final buffer tranfer.
* descriptor (DSCR bits) registers at the final buffer transfer.
*
* Enable error, buffer complete and transfer complete interrupts. We
* don't really need the buffer complete interrupts, but we will take them
@ -2309,7 +2309,7 @@ int sam_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg)
dmach->callback = callback;
dmach->arg = arg;
/* Is this a single block transfer? Or a multiple block tranfer? */
/* Is this a single block transfer? Or a multiple block transfer? */
if (dmach->llhead == dmach->lltail)
{

4
arch/arm/src/sama5/sam_udphs.c
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@ -1280,7 +1280,7 @@ static void sam_req_wrsetup(struct sam_usbdev_s *priv,
* When a request is queued, the request 'len' is the number of bytes
* to transfer and 'xfrd' and 'inflight' must be zero.
*
* When this function starts a tranfer it will update the request
* When this function starts a transfer it will update the request
* 'inflight' field to indicate the size of the transfer.
*
* When the transfer completes, the the 'inflight' field must hold the
@ -1547,7 +1547,7 @@ static void sam_req_rddisable(uint8_t epno)
* - When receiving data via DMA, then data has already been transferred
* and this function is called on the terminating event. The transfer
* is complete and we just need to check for end of request events and
* if we need to setup the tranfer for the next request.
* if we need to setup the transfer for the next request.
* - When receiving via the FIFO, the transfer is not complete. The
* data is in the FIFO and must be transferred from the FIFO to the
* request buffer. No setup is needed for the next transfer other than

2
arch/arm/src/sama5/sam_xdmac.c
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@ -2355,7 +2355,7 @@ int sam_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg)
xdmach->callback = callback;
xdmach->arg = arg;
/* Is this a single block transfer? Or a multiple block tranfer? */
/* Is this a single block transfer? Or a multiple block transfer? */
if (xdmach->llhead == xdmach->lltail)
{

2
arch/arm/src/samdl/chip/saml_eic.h
View File

@ -106,7 +106,7 @@
# define EIC_NVMICTRL_NMISENSE_HIGH (4 << EIC_NVMICTRL_NMISENSE_SHIFT) /* High level detection */
# define EIC_NVMICTRL_NMISENSE_LOW (5 << EIC_NVMICTRL_NMISENSE_SHIFT) /* Low level detection */
#define EIC_NVMICTRL_NMIFLTEN (1 << 3) /* Bit 3: Non-maskable interrupt filter enable */
#define EIC_NVMICTRL_ASYNC (1 << 4) /* Bit 4: Asynchronous edge detectino mode */
#define EIC_NVMICTRL_ASYNC (1 << 4) /* Bit 4: Asynchronous edge detection mode */
/* Non-maskable interrupt flas status and clear register */

4
arch/arm/src/samv7/sam_emac.c
View File

@ -2103,7 +2103,7 @@ static void sam_txdone(struct sam_emac_s *priv, int qid)
*
* Parameters:
* priv - Reference to the driver state structure
* quid - Index of the tranfer queue that generated the interrupt
* quid - Index of the transfer queue that generated the interrupt
*
* Returned Value:
* None
@ -2230,7 +2230,7 @@ static void sam_txerr_interrupt(FAR struct sam_emac_s *priv, int qid)
*
* Parameters:
* priv - Reference to the driver state structure
* quid - Index of the tranfer queue that generated the interrupt
* quid - Index of the transfer queue that generated the interrupt
*
* Returned Value:
* None

10
arch/arm/src/samv7/sam_usbdevhs.c
View File

@ -571,14 +571,14 @@ static const struct usb_epdesc_s g_ep0desc =
#ifdef CONFIG_SAMV7_USBDEVHS_SCATTERGATHER
#ifdef CONFIG_SAMV7_USBDEVHS_PREALLOCATE
/* This is a properly aligned pool of preallocated DMA transfer desciptors */
/* This is a properly aligned pool of preallocated DMA transfer descriptors */
static struct sam_dtd_s g_dtdpool[CONFIG_SAMV7_USBDEVHS_NDTDS]
__attribute__ ((aligned(16)));
#endif
#endif
/* Device error strings that may be enabled for more desciptive USB trace
/* Device error strings that may be enabled for more descriptive USB trace
* output.
*/
@ -619,7 +619,7 @@ const struct trace_msg_t g_usb_trace_strings_deverror[] =
};
#endif
/* Interrupt event strings that may be enabled for more desciptive USB trace
/* Interrupt event strings that may be enabled for more descriptive USB trace
* output.
*/
@ -1287,7 +1287,7 @@ static void sam_req_wrsetup(struct sam_usbdev_s *priv,
* When a request is queued, the request 'len' is the number of bytes
* to transfer and 'xfrd' and 'inflight' must be zero.
*
* When this function starts a tranfer it will update the request
* When this function starts a transfer it will update the request
* 'inflight' field to indicate the size of the transfer.
*
* When the transfer completes, the the 'inflight' field must hold the
@ -1544,7 +1544,7 @@ static void sam_req_rddisable(uint8_t epno)
* - When receiving data via DMA, then data has already been transferred
* and this function is called on the terminating event. The transfer
* is complete and we just need to check for end of request events and
* if we need to setup the tranfer for the next request.
* if we need to setup the transfer for the next request.
* - When receiving via the FIFO, the transfer is not complete. The
* data is in the FIFO and must be transferred from the FIFO to the
* request buffer. No setup is needed for the next transfer other than

2
arch/arm/src/stm32/stm32_otgfshost.c
View File

@ -1093,7 +1093,7 @@ static int stm32_chan_wait(FAR struct stm32_usbhost_s *priv,
/* Loop, testing for an end of transfer condition. The channel 'result'
* was set to EBUSY and 'waiter' was set to true before the transfer; 'waiter'
* will be set to false and 'result' will be set appropriately when the
* tranfer is completed.
* transfer is completed.
*/
do

2
arch/arm/src/stm32/stm32_otghshost.c
View File

@ -1093,7 +1093,7 @@ static int stm32_chan_wait(FAR struct stm32_usbhost_s *priv,
/* Loop, testing for an end of transfer condition. The channel 'result'
* was set to EBUSY and 'waiter' was set to true before the transfer; 'waiter'
* will be set to false and 'result' will be set appropriately when the
* tranfer is completed.
* transfer is completed.
*/
do

4
arch/avr/src/at32uc3/at32uc3_ssc.h
View File

@ -114,7 +114,7 @@
#define SSC_RCMR_CKI (1 << 5) /* Bit 5: Receive Clock Inversion */
#define SSC_RCMR_CKG_SHIFT (6) /* Bits 6-7: Receive Clock Gating Selection */
#define SSC_RCMR_CKG_MASK (3 << SSC_RCMR_CKG_SHIFT)
# define SSC_RCMR_CKG_NONE (0 << SSC_RCMR_CKG_SHIFT) /* None, continous clock */
# define SSC_RCMR_CKG_NONE (0 << SSC_RCMR_CKG_SHIFT) /* None, continuous clock */
# define SSC_RCMR_CKG_LOW (1 << SSC_RCMR_CKG_SHIFT) /* Enable if RX_FRAME_SYNC low */
# define SSC_RCMR_CKG_HIGH (2 << SSC_RCMR_CKG_SHIFT) /* Enable if RX_FRAME_SYNC high */
#define SSC_RCMR_START_SHIFT (8) /* Bits 8-11: Receive Start Selection */
@ -171,7 +171,7 @@
#define SSC_TCMR_CKI (1 << 5) /* Bit 5: Transmit Clock Inversion */
#define SSC_TCMR_CKG_SHIFT (6) /* Bits 6-7: Transmit Clock Gating Selection */
#define SSC_TCMR_CKG_MASK (3 << SSC_TCMR_CKG_SHIFT)
# define SSC_TCMR_CKG_NONE (0 << SSC_TCMR_CKG_SHIFT) /* None, continous clock */
# define SSC_TCMR_CKG_NONE (0 << SSC_TCMR_CKG_SHIFT) /* None, continuous clock */
# define SSC_TCMR_CKG_LOW (1 << SSC_TCMR_CKG_SHIFT) /* Enable if TX_FRAME_SYNC low */
# define SSC_TCMR_CKG_HIGH (2 << SSC_TCMR_CKG_SHIFT) /* Enable if TX_FRAME_SYNC high */
#define SSC_TCMR_START_SHIFT (8) /* Bits 8-11: Transmit Start Selection */

2
arch/mips/src/pic32mx/pic32mx-usbdev.c
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@ -2876,7 +2876,7 @@ static int pic32mx_interrupt(int irq, void *context)
usbtrace(TRACE_INTDECODE(PIC32MX_TRACEINTID_TRNCS), regval);
/* Handle the endpoint tranfer complete event. */
/* Handle the endpoint transfer complete event. */
epno = (regval & USB_STAT_ENDPT_MASK) >> USB_STAT_ENDPT_SHIFT;
if (epno == 0)