sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

arch/arm/src/stm32/stm32_adc: add interface to configure EXTSEL/JEXTSEL from low-level ops

Browse Source
This commit is contained in:
raiden00pl 2020-04-26 20:21:37 +02:00 committed by Alan Carvalho de Assis
parent d4bf61c523
commit e2a3266857
3 changed files with 221 additions and 78 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

56
arch/arm/src/stm32/Kconfig
View File

@ -7758,6 +7758,62 @@ config STM32_ADC4_INJECTED_CHAN
---help---
Support for ADC4 injected channels.
config STM32_ADC1_EXTSEL
bool "ADC1 external trigger for regular group"
depends on STM32_ADC1 && !STM32_HAVE_ADC1_TIMER
default n
---help---
Enable EXTSEL for ADC1.
config STM32_ADC2_EXTSEL
bool "ADC2 external trigger for regular group"
depends on STM32_ADC2 && !STM32_HAVE_ADC2_TIMER
default n
---help---
Enable EXTSEL for ADC2.
config STM32_ADC3_EXTSEL
bool "ADC3 external trigger for regular group"
depends on STM32_ADC3 && !STM32_HAVE_ADC3_TIMER
default n
---help---
Enable EXTSEL for ADC3.
config STM32_ADC4_EXTSEL
bool "ADC4 external trigger for regular group"
depends on STM32_ADC4 && !STM32_HAVE_ADC4_TIMER
default n
---help---
Enable EXTSEL for ADC4.
config STM32_ADC1_JEXTSEL
bool "ADC1 external trigger for injected group"
depends on STM32_ADC1
default n
---help---
Enable JEXTSEL for ADC1.
config STM32_ADC2_JEXTSEL
bool "ADC2 external trigger for injected group"
depends on STM32_ADC2
default n
---help---
Enable JEXTSEL for ADC2.
config STM32_ADC3_JEXTSEL
bool "ADC3 external trigger for injected group"
depends on STM32_ADC3
default n
---help---
Enable JEXTSEL for ADC3.
config STM32_ADC4_JEXTSEL
bool "ADC4 external trigger for injected group"
depends on STM32_ADC4
default n
---help---
Enable JEXTSEL for ADC4.
endmenu
menu "SDADC Configuration"

116
arch/arm/src/stm32/stm32_adc.c
View File

@ -351,64 +351,6 @@
# undef HAVE_ADC_CMN_DATA
#endif
/* ADCx_EXTSEL_VALUE can be set by this driver (look at stm32_adc.h) or
* by board specific logic in board.h file.
*/
#ifdef ADC1_EXTSEL_VALUE
# define ADC1_HAVE_EXTCFG 1
# define ADC1_EXTCFG_VALUE (ADC1_EXTSEL_VALUE | ADC_EXTREG_EXTEN_DEFAULT)
#else
# undef ADC1_HAVE_EXTCFG
#endif
#ifdef ADC2_EXTSEL_VALUE
# define ADC2_HAVE_EXTCFG 1
# define ADC2_EXTCFG_VALUE (ADC2_EXTSEL_VALUE | ADC_EXTREG_EXTEN_DEFAULT)
#else
# undef ADC2_HAVE_EXTCFG
#endif
#ifdef ADC3_EXTSEL_VALUE
# define ADC3_HAVE_EXTCFG 1
# define ADC3_EXTCFG_VALUE (ADC3_EXTSEL_VALUE | ADC_EXTREG_EXTEN_DEFAULT)
#else
# undef ADC3_HAVE_EXTCFG
#endif
#ifdef ADC4_EXTSEL_VALUE
# define ADC4_HAVE_EXTCFG 1
# define ADC4_EXTCFG_VALUE (ADC4_EXTSEL_VALUE | ADC_EXTREG_EXTEN_DEFAULT)
#else
# undef ADC4_HAVE_EXTCFG
#endif
#if defined(ADC1_HAVE_EXTCFG) || defined(ADC2_HAVE_EXTCFG) || \
defined(ADC3_HAVE_EXTCFG) || defined(ADC3_HAVE_EXTCFG)
# define ADC_HAVE_EXTCFG
#endif
/* Injected channels external trigger support */
#ifdef ADC1_JEXTSEL_VALUE
# define ADC1_HAVE_JEXTCFG 1
# define ADC1_JEXTCFG_VALUE (ADC1_JEXTSEL_VALUE | ADC_JEXTREG_JEXTEN_DEFAULT)
#endif
#ifdef ADC2_JEXTSEL_VALUE
# define ADC2_HAVE_JEXTCFG 1
# define ADC2_JEXTCFG_VALUE (ADC2_JEXTSEL_VALUE | ADC_JEXTREG_JEXTEN_DEFAULT)
#endif
#ifdef ADC3_JEXTSEL_VALUE
# define ADC3_HAVE_JEXTCFG 1
# define ADC3_JEXTCFG_VALUE (ADC3_JEXTSEL_VALUE | ADC_JEXTREG_JEXTEN_DEFAULT)
#endif
#ifdef ADC4_JEXTSEL_VALUE
# define ADC4_HAVE_JEXTCFG 1
# define ADC4_JEXTCFG_VALUE (ADC4_JEXTSEL_VALUE | ADC_JEXTREG_JEXTEN_DEFAULT)
#endif
#if defined(ADC1_HAVE_JEXTCFG) || defined(ADC2_HAVE_JEXTCFG) || \
defined(ADC3_HAVE_JEXTCFG) || defined(ADC4_HAVE_JEXTCFG)
# define ADC_HAVE_JEXTCFG
#endif
/* Max 4 injected channels */
#define ADC_INJ_MAX_SAMPLES 4
@ -646,10 +588,10 @@ static int adc_inj_set_ch(FAR struct adc_dev_s *dev, uint8_t ch);
#endif
#ifdef ADC_HAVE_EXTCFG
static int adc_extcfg_set(FAR struct adc_dev_s *dev, uint32_t extcfg);
static int adc_extcfg_set(FAR struct stm32_dev_s *priv, uint32_t extcfg);
#endif
#ifdef ADC_HAVE_JEXTCFG
static int adc_jextcfg_set(FAR struct adc_dev_s *dev, uint32_t jextcfg);
static int adc_jextcfg_set(FAR struct stm32_dev_s *priv, uint32_t jextcfg);
#endif
static void adc_dumpregs(FAR struct stm32_dev_s *priv);
@ -664,6 +606,14 @@ static void adc_llops_reg_startconv(FAR struct stm32_adc_dev_s *dev,
bool enable);
static int adc_offset_set(FAR struct stm32_adc_dev_s *dev, uint8_t ch,
uint8_t i, uint16_t offset);
# ifdef ADC_HAVE_EXTCFG
static void adc_llops_extcfg_set(FAR struct stm32_adc_dev_s *dev,
uint32_t extcfg);
# endif
# ifdef ADC_HAVE_JEXTCFG
static void adc_llops_jextcfg_set(FAR struct stm32_adc_dev_s *dev,
uint32_t jextcfg);
# endif
# ifdef ADC_HAVE_DMA
static int adc_regbufregister(FAR struct stm32_adc_dev_s *dev,
uint16_t *buffer, uint8_t len);
@ -716,6 +666,12 @@ static const struct stm32_adc_ops_s g_adc_llops =
# ifdef ADC_HAVE_DMA
.regbuf_reg = adc_regbufregister,
# endif
# ifdef ADC_HAVE_EXTCFG
.extcfg_set = adc_llops_extcfg_set,
# endif
# ifdef ADC_HAVE_JEXTCFG
.jextcfg_set = adc_llops_jextcfg_set,
# endif
# ifdef ADC_HAVE_INJECTED
.inj_get = adc_injget,
.inj_startconv = adc_llops_inj_startconv,
@ -2788,7 +2744,7 @@ static void adc_configure(FAR struct adc_dev_s *dev)
#ifdef ADC_HAVE_EXTCFG
/* Configure external event for regular group */
adc_extcfg_set(dev, priv->extcfg);
adc_extcfg_set(priv, priv->extcfg);
#endif
/* Enable ADC */
@ -2798,7 +2754,7 @@ static void adc_configure(FAR struct adc_dev_s *dev)
#ifdef ADC_HAVE_JEXTCFG
/* Configure external event for injected group when ADC enabled */
adc_jextcfg_set(dev, priv->jextcfg);
adc_jextcfg_set(priv, priv->jextcfg);
#if defined(HAVE_IP_ADC_V2)
/* For ADC IPv2 there is queue of context for injected conversion.
@ -3210,9 +3166,8 @@ errout:
****************************************************************************/
#ifdef ADC_HAVE_EXTCFG
static int adc_extcfg_set(FAR struct adc_dev_s *dev, uint32_t extcfg)
static int adc_extcfg_set(FAR struct stm32_dev_s *priv, uint32_t extcfg)
{
FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
uint32_t exten = 0;
uint32_t extsel = 0;
uint32_t setbits = 0;
@ -3252,9 +3207,8 @@ static int adc_extcfg_set(FAR struct adc_dev_s *dev, uint32_t extcfg)
****************************************************************************/
#ifdef ADC_HAVE_JEXTCFG
static int adc_jextcfg_set(FAR struct adc_dev_s *dev, uint32_t jextcfg)
static int adc_jextcfg_set(FAR struct stm32_dev_s *priv, uint32_t jextcfg)
{
FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
uint32_t jexten = 0;
uint32_t jextsel = 0;
uint32_t setbits = 0;
@ -4312,6 +4266,34 @@ errout:
}
#endif
/****************************************************************************
* Name: adc_llops_extcfg_set
****************************************************************************/
#ifdef ADC_HAVE_EXTCFG
static void adc_llops_extcfg_set(FAR struct stm32_adc_dev_s *dev,
uint32_t extcfg)
{
FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev;
adc_extcfg_set(priv, extcfg);
}
#endif
/****************************************************************************
* Name: adc_llops_jextcfg_set
****************************************************************************/
#ifdef ADC_HAVE_JEXTCFG
static void adc_llops_jextcfg_set(FAR struct stm32_adc_dev_s *dev,
uint32_t jextcfg)
{
FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev;
adc_jextcfg_set(priv, jextcfg);
}
#endif
/****************************************************************************
* Name: adc_regbufregister
****************************************************************************/
@ -4337,7 +4319,7 @@ static int adc_regbufregister(FAR struct stm32_adc_dev_s *dev,
#endif /* ADC_HAVE_DMA */
/****************************************************************************
* Name: adc_inj_get
* Name: adc_injget
****************************************************************************/
#ifdef ADC_HAVE_INJECTED

127
arch/arm/src/stm32/stm32_adc.h
View File

@ -61,8 +61,10 @@
# define ADC_DMAREG_DMA ADC_CR2_DMA
# define STM32_ADC_EXTREG_OFFSET STM32_ADC_CR2_OFFSET
# define ADC_EXTREG_EXTSEL_MASK ADC_CR2_EXTSEL_MASK
# define ADC_EXTREG_EXTSEL_SHIFT ADC_CR2_EXTSEL_SHIFT
# define STM32_ADC_JEXTREG_OFFSET STM32_ADC_CR2_OFFSET
# define ADC_JEXTREG_JEXTSEL_MASK ADC_CR2_JEXTSEL_MASK
# define ADC_EXTREG_JEXTSEL_SHIFT ADC_CR2_JEXTSEL_SHIFT
# define STM32_ADC_ISR_OFFSET STM32_ADC_SR_OFFSET
# define STM32_ADC_IER_OFFSET STM32_ADC_CR1_OFFSET
# ifdef HAVE_BASIC_ADC
@ -85,10 +87,12 @@
# define ADC_DMAREG_DMA ADC_CFGR1_DMAEN
# define STM32_ADC_EXTREG_OFFSET STM32_ADC_CFGR1_OFFSET
# define ADC_EXTREG_EXTSEL_MASK ADC_CFGR1_EXTSEL_MASK
# define ADC_EXTREG_EXTSEL_SHIFT ADC_CFGR1_EXTSEL_SHIFT
# define ADC_EXTREG_EXTEN_MASK ADC_CFGR1_EXTEN_MASK
# define ADC_EXTREG_EXTEN_DEFAULT ADC_CFGR1_EXTEN_RISING
# define STM32_ADC_JEXTREG_OFFSET STM32_ADC_JSQR_OFFSET
# define ADC_JEXTREG_JEXTSEL_MASK ADC_JSQR_JEXTSEL_MASK
# define ADC_EXTREG_JEXTSEL_SHIFT ADC_JSQR_JEXTSEL_SHIFT
# define ADC_JEXTREG_JEXTEN_MASK ADC_JSQR_JEXTEN_MASK
# define ADC_JEXTREG_JEXTEN_DEFAULT ADC_JSQR_JEXTEN_RISING
#endif
@ -1346,6 +1350,11 @@
/* EXTSEL configuration *************************************************************/
/* NOTE: this configuration if used only if CONFIG_STM32_TIMx_ADCy is selected.
* You can still connect the ADC with a timer trigger using the
* CONFIG_STM32_ADCx_EXTSEL option.
*/
#if defined(CONFIG_STM32_TIM1_ADC1)
# if CONFIG_STM32_ADC1_TIMTRIG == 0
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC1
@ -1880,35 +1889,115 @@
# endif
#endif
/* Regular channels external trigger support */
#ifdef ADC1_EXTSEL_VALUE
# define ADC1_HAVE_EXTCFG 1
# define ADC1_EXTCFG_VALUE (ADC1_EXTSEL_VALUE | ADC_EXTREG_EXTEN_DEFAULT)
#elif defined(CONFIG_STM32_ADC1_EXTSEL)
# define ADC1_HAVE_EXTCFG 1
# define ADC1_EXTCFG_VALUE 0
#else
# undef ADC1_HAVE_EXTCFG
#endif
#ifdef ADC2_EXTSEL_VALUE
# define ADC2_HAVE_EXTCFG 1
# define ADC2_EXTCFG_VALUE (ADC2_EXTSEL_VALUE | ADC_EXTREG_EXTEN_DEFAULT)
#elif defined(CONFIG_STM32_ADC2_EXTSEL)
# define ADC2_HAVE_EXTCFG 1
# define ADC2_EXTCFG_VALUE 0
#else
# undef ADC2_HAVE_EXTCFG
#endif
#ifdef ADC3_EXTSEL_VALUE
# define ADC3_HAVE_EXTCFG 1
# define ADC3_EXTCFG_VALUE (ADC3_EXTSEL_VALUE | ADC_EXTREG_EXTEN_DEFAULT)
#elif defined(CONFIG_STM32_ADC3_EXTSEL)
# define ADC3_HAVE_EXTCFG 1
# define ADC3_EXTCFG_VALUE 0
#else
# undef ADC3_HAVE_EXTCFG
#endif
#ifdef ADC4_EXTSEL_VALUE
# define ADC4_HAVE_EXTCFG 1
# define ADC4_EXTCFG_VALUE (ADC4_EXTSEL_VALUE | ADC_EXTREG_EXTEN_DEFAULT)
#elif defined(CONFIG_STM32_ADC4_EXTSEL)
# define ADC4_HAVE_EXTCFG 1
# define ADC4_EXTCFG_VALUE 0
#else
# undef ADC4_HAVE_EXTCFG
#endif
#if defined(ADC1_HAVE_EXTCFG) || defined(ADC2_HAVE_EXTCFG) || \
defined(ADC3_HAVE_EXTCFG) || defined(ADC3_HAVE_EXTCFG)
# define ADC_HAVE_EXTCFG
#endif
/* JEXTSEL configuration ************************************************************/
/* TODO: ADC1 JEXTSEL trigger */
/* There is no automatic timer tirgger configuration from Kconfig for injected
* channels conversion.
*/
/* ADC1 HRTIM JEXTSEL trigger */
#if defined(CONFIG_STM32_HRTIM_ADC1_TRG2)
# define ADC1_JEXTSEL_VALUE ADC1_JEXTSEL_HRTTRG2
#elif defined(CONFIG_STM32_HRTIM_ADC1_TRG4)
# define ADC1_JEXTSEL_VALUE ADC1_JEXTSEL_HRTTRG4
#else
# undef ADC1_JEXTSEL_VALUE
#endif
/* TODO: ADC2 JEXTSEL trigger */
/* ADC1 HRTIM JEXTSEL trigger */
#if defined(CONFIG_STM32_HRTIM_ADC2_TRG2)
# define ADC2_JEXTSEL_VALUE ADC2_JEXTSEL_HRTTRG2
#elif defined(CONFIG_STM32_HRTIM_ADC2_TRG4)
# define ADC2_JEXTSEL_VALUE ADC2_JEXTSEL_HRTTRG4
#else
# undef ADC2_JEXTSEL_VALUE
#endif
/* TODO: ADC3 JEXTSEL trigger */
/* Injected channels external trigger support */
#undef ADC3_JEXTSEL_VALUE
#ifdef ADC1_JEXTSEL_VALUE
# define ADC1_HAVE_JEXTCFG 1
# define ADC1_JEXTCFG_VALUE (ADC1_JEXTSEL_VALUE | ADC_JEXTREG_JEXTEN_DEFAULT)
#elif defined(CONFIG_STM32_ADC1_JEXTSEL)
# define ADC1_HAVE_JEXTCFG 1
# define ADC1_JEXTCFG_VALUE 0
#else
# undef ADC1_HAVE_JEXTCFG
#endif
#ifdef ADC2_JEXTSEL_VALUE
# define ADC2_HAVE_JEXTCFG 1
# define ADC2_JEXTCFG_VALUE (ADC2_JEXTSEL_VALUE | ADC_JEXTREG_JEXTEN_DEFAULT)
#elif defined(CONFIG_STM32_ADC2_JEXTSEL)
# define ADC2_HAVE_JEXTCFG 1
# define ADC2_JEXTCFG_VALUE 0
#else
# undef ADC2_HAVE_JEXTCFG
#endif
#ifdef ADC3_JEXTSEL_VALUE
# define ADC3_HAVE_JEXTCFG 1
# define ADC3_JEXTCFG_VALUE (ADC3_JEXTSEL_VALUE | ADC_JEXTREG_JEXTEN_DEFAULT)
#elif defined(CONFIG_STM32_ADC3_JEXTSEL)
# define ADC3_HAVE_JEXTCFG 1
# define ADC3_JEXTCFG_VALUE 0
#else
# undef ADC3_HAVE_JEXTCFG
#endif
#ifdef ADC4_JEXTSEL_VALUE
# define ADC4_HAVE_JEXTCFG 1
# define ADC4_JEXTCFG_VALUE (ADC4_JEXTSEL_VALUE | ADC_JEXTREG_JEXTEN_DEFAULT)
#elif defined(CONFIG_STM32_ADC4_JEXTSEL)
# define ADC4_HAVE_JEXTCFG 1
# define ADC4_JEXTCFG_VALUE 0
#else
# undef ADC4_HAVE_JEXTCFG
#endif
/* TODO: ADC4 JEXTSEL trigger */
#undef ADC4_JEXTSEL_VALUE
#if defined(ADC1_HAVE_JEXTCFG) || defined(ADC2_HAVE_JEXTCFG) || \
defined(ADC3_HAVE_JEXTCFG) || defined(ADC4_HAVE_JEXTCFG)
# define ADC_HAVE_JEXTCFG
#endif
/* ADC interrupts *******************************************************************/
@ -1964,10 +2053,14 @@
(adc)->llops->reg_startconv(adc, state)
#define STM32_ADC_OFFSET_SET(adc, ch, i, o) \
(adc)->llops->offset_set(adc, ch, i, o)
#define STM32_ADC_EXTCFG_SET(adc, c) \
(adc)->llops->extcfg_set(adc, c)
#define STM32_ADC_INJ_STARTCONV(adc, state) \
(adc)->llops->inj_startconv(adc, state)
#define STM32_ADC_INJDATA_GET(adc, chan) \
(adc)->llops->inj_get(adc, chan)
#define STM32_ADC_JEXTCFG_SET(adc, c) \
(adc)->llops->jextcfg_set(adc, c)
#define STM32_ADC_SAMPLETIME_SET(adc, time_samples) \
(adc)->llops->stime_set(adc, time_samples)
#define STM32_ADC_SAMPLETIME_WRITE(adc) \
@ -2101,6 +2194,18 @@ struct stm32_adc_ops_s
int (*offset_set)(FAR struct stm32_adc_dev_s *dev, uint8_t ch, uint8_t i,
uint16_t offset);
#ifdef ADC_HAVE_EXTCFG
/* Configure the ADC external trigger for regular conversion */
void (*extcfg_set)(FAR struct stm32_adc_dev_s *dev, uint32_t extcfg);
#endif
#ifdef ADC_HAVE_JEXTCFG
/* Configure the ADC external trigger for injected conversion */
void (*jextcfg_set)(FAR struct stm32_adc_dev_s *dev, uint32_t jextcfg);
#endif
#ifdef ADC_HAVE_INJECTED
/* Get current ADC injected data register */