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Add support for the STM32152 and STM32162 Medium+ density parts (plus miscellaneous other improvements to the original STM32151 logic). From Jussi Kivilinna and Sami Pelkonen

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This commit is contained in:
Gregory Nutt 2014-05-08 09:20:11 -06:00
parent b5efb9dd77
commit e2b8eb6aad
19 changed files with 459 additions and 67 deletions
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10
ChangeLog
View File

@ -7305,4 +7305,12 @@
logic is incomplete and really nothing more than a thought experiment
to determine the feasibility of the P-code binary format (2014-5-7).
* drivers/sensors/Make.defs: Correct build dependency. Sourceforge
ticket #41 from Kosma Moczek (2014-8-14).
ticket #41 from Kosma Moczek (2014-5-8).
* drivers/serial.c, include/nuttx/serial.h, arch/arm/src/stm32/stm32_serial.c
and minor updates to all other drivers using the serial interface: Add an
rxflowcontrol method to the serial interface to better support RX flow control.
From Jussi Kivilinna (2014-5-8).
* arch/arm/include/stm32 and src/stm32: Add support for the STM32152 and
STM32162 Medium+ density parts (plus miscellaneous other improvements to
the original STM32151 logi). From Jussi Kivilinna and Sami Pelkonen
(2014-5-8).

135
arch/arm/include/stm32/chip.h
View File

@ -68,6 +68,9 @@
* STM32L15XX6 -- 32KB FLASH, 10KB SRAM, 4KB EEPROM
* STM32L15XX8 -- 64KB FLASH, 10KB SRAM, 4KB EEPROM
* STM32L15XXB -- 128KB FLASH, 16KB SRAM, 4KB EEPROM
*
* STM32L15XXC -- 256KB FLASH, 32KB SRAM, 8KB EEPROM (medium+ density)
*
*/
#if defined(CONFIG_ARCH_CHIP_STM32L151C6) || defined(CONFIG_ARCH_CHIP_STM32L151C8) || \
@ -76,8 +79,9 @@
# define CONFIG_STM32_ENERGYLITE 1 /* STM32L EnergyLite family */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# define CONFIG_STM32_LOWDENSITY 1 /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes
* and all STM32L15xxx */
* and STM32L15xxx */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
@ -114,8 +118,9 @@
# define CONFIG_STM32_ENERGYLITE 1 /* STM32L EnergyLite family */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# define CONFIG_STM32_LOWDENSITY 1 /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes
* and all STM32L15xxx */
* and STM32L15xxx */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
@ -152,8 +157,9 @@
# define CONFIG_STM32_ENERGYLITE 1 /* STM32L EnergyLite family */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# define CONFIG_STM32_LOWDENSITY 1 /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes
* and all STM32L15xxx */
* and STM32L15xxx */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
@ -190,8 +196,9 @@
# define CONFIG_STM32_ENERGYLITE 1 /* STM32L EnergyLite family */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# define CONFIG_STM32_LOWDENSITY 1 /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes
* and all STM32L15xxx */
* and STM32L15xxx */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
@ -228,8 +235,9 @@
# define CONFIG_STM32_ENERGYLITE 1 /* STM32L EnergyLite family */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# define CONFIG_STM32_LOWDENSITY 1 /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes
* and all STM32L15xxx */
* and STM32L15xxx */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
@ -266,8 +274,9 @@
# define CONFIG_STM32_ENERGYLITE 1 /* STM32L EnergyLite family */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# define CONFIG_STM32_LOWDENSITY 1 /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes
* and all STM32L15xxx */
* and STM32L15xxx */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
@ -298,6 +307,83 @@
# define STM32_NRNG 0 /* No random number generator (RNG) */
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32L152RC)
# define CONFIG_STM32_STM32L15XX 1 /* STM32L151xx and STM32L152xx family */
# define CONFIG_STM32_ENERGYLITE 1 /* STM32L EnergyLite vamily */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes
* and STM32L15xxx */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# define CONFIG_STM32_MEDIUMPLUSDENSITY 1 /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 0 /* No advanced timers */
# define STM32_NGTIM 6 /* (3) 16-bit general up/down timers TIM2,3,4 with DMA */
/* (3) 16-bit general up timers TIM9, 10, 11 without DMA */
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */
# define STM32_NSPI 3 /* SPI1-3 */
# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */
# define STM32_NUSART 3 /* USART1-3 */
# define STM32_NI2C 2 /* I2C1-2 */
# define STM32_NCAN 0 /* No CAN */
# define STM32_NSDIO 0 /* No SDIO */
# define STM32_NLCD 1 /* LCD 4x44, 8x40*/
# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */
# define STM32_NGPIO 83 /* GPIOA-E,H */
# define STM32_NADC 1 /* ADC1, 24-channels */
# define STM32_NDAC 2 /* DAC 1-2, 2 channels */
/* (2) Comparators */
# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */
# define STM32_NCRC 1 /* CRC */
# define STM32_NETHERNET 0 /* No ethernet */
# define STM32_NRNG 0 /* No random number generator (RNG) */
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32L162ZD)
# define CONFIG_STM32_STM32L15XX 1 /* STM32L151xx and STM32L152xx family */
# define CONFIG_STM32_ENERGYLITE 1 /* STM32L EnergyLite vamily */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes
* and STM32L15xxx */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# define CONFIG_STM32_HIGHDENSITY 1 /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes, STM32L16x w/ 48/384 Kbytes. */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 0 /* No advanced timers */
# define STM32_NGTIM 4 /* 16-bit general timers TIM2,3,4 with DMA
* 32-bit general timer TIM5 with DMA */
# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 without DMA */
# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */
# define STM32_NSPI 3 /* SPI1-3 */
# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */
# define STM32_NUSART 5 /* USART1-3, UART4-5 */
# define STM32_NI2C 2 /* I2C1-2 */
# define STM32_NCAN 0 /* No CAN */
# define STM32_NSDIO 1 /* SDIO */
# define STM32_NLCD 1 /* LCD 4x44, 8x40*/
# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */
# define STM32_NGPIO 115 /* GPIOA-G,H */
# define STM32_NADC 1 /* ADC1, 24-channels */
# define STM32_NDAC 2 /* DAC 1-2, 2 channels */
/* (2) Comparators */
# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */
# define STM32_NCRC 1 /* CRC */
# define STM32_NETHERNET 0 /* No ethernet */
# define STM32_NRNG 0 /* No random number generator (RNG) */
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
/* STM32 F100 Value Line ************************************************************/
#elif defined(CONFIG_ARCH_CHIP_STM32F100C8) || defined(CONFIG_ARCH_CHIP_STM32F100CB) \
@ -307,6 +393,7 @@
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# define CONFIG_STM32_MEDIUMDENSITY 1 /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# define CONFIG_STM32_VALUELINE 1 /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
@ -342,6 +429,7 @@
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# define CONFIG_STM32_MEDIUMDENSITY 1 /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# define CONFIG_STM32_VALUELINE 1 /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
@ -380,6 +468,7 @@
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# define CONFIG_STM32_HIGHDENSITY 1 /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# define CONFIG_STM32_VALUELINE 1 /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
@ -416,6 +505,7 @@
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# define CONFIG_STM32_HIGHDENSITY 1 /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# define CONFIG_STM32_VALUELINE 1 /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
@ -453,6 +543,7 @@
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
# define CONFIG_STM32_LOWDENSITY 1 /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
@ -487,6 +578,7 @@
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# define CONFIG_STM32_MEDIUMDENSITY 1 /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# define CONFIG_STM32_PERFORMANCELINE 1 /* STM32F103x8 and STM32F103xB */
@ -522,6 +614,7 @@
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# define CONFIG_STM32_MEDIUMDENSITY 1 /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# define CONFIG_STM32_PERFORMANCELINE 1 /* STM32F103x8 and STM32F103xB */
@ -557,6 +650,7 @@
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# define CONFIG_STM32_MEDIUMDENSITY 1 /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# define CONFIG_STM32_PERFORMANCELINE 1 /* STM32F103x8 and STM32F103xB */
@ -597,6 +691,7 @@
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# define CONFIG_STM32_HIGHDENSITY 1 /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
@ -635,6 +730,7 @@
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# define CONFIG_STM32_HIGHDENSITY 1 /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
@ -673,6 +769,7 @@
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# define CONFIG_STM32_HIGHDENSITY 1 /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
@ -709,6 +806,7 @@
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# define CONFIG_STM32_CONNECTIVITYLINE 1 /* STM32F105x and STM32F107x */
@ -743,6 +841,7 @@
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# define CONFIG_STM32_CONNECTIVITYLINE 1 /* STM32F105x and STM32F107x */
@ -779,6 +878,7 @@
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
@ -815,6 +915,7 @@
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
@ -861,6 +962,7 @@
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
@ -899,6 +1001,7 @@
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
@ -937,6 +1040,7 @@
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
@ -975,6 +1079,7 @@
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
@ -1013,6 +1118,7 @@
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
@ -1051,6 +1157,7 @@
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
@ -1091,6 +1198,7 @@
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
@ -1127,6 +1235,7 @@
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
@ -1163,6 +1272,7 @@
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
@ -1199,6 +1309,7 @@
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
@ -1235,6 +1346,7 @@
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
@ -1271,6 +1383,7 @@
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
@ -1307,6 +1420,7 @@
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
@ -1343,6 +1457,7 @@
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
@ -1379,6 +1494,7 @@
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
@ -1415,6 +1531,7 @@
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
@ -1451,6 +1568,7 @@
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
@ -1487,6 +1605,7 @@
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
@ -1523,6 +1642,7 @@
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
@ -1559,6 +1679,7 @@
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
@ -1595,6 +1716,7 @@
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
@ -1631,6 +1753,7 @@
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */

4
arch/arm/include/stm32/stm32l15xxx_irq.h
View File

@ -227,8 +227,8 @@
# define STM32_IRQ_SDIO (STM32_IRQ_INTERRUPTS+45) /* 45: SDIO Global interrupt */
# define STM32_IRQ_TIM5 (STM32_IRQ_INTERRUPTS+46) /* 46: TIM5 global interrupt */
# define STM32_IRQ_SPI3 (STM32_IRQ_INTERRUPTS+47) /* 47: SPI3 global interrupt */
# define STM32_IRQ_USART4 (STM32_IRQ_INTERRUPTS+48) /* 48: USART4 global interrupt */
# define STM32_IRQ_USART5 (STM32_IRQ_INTERRUPTS+49) /* 49: USART5 global interrupt */
# define STM32_IRQ_UART4 (STM32_IRQ_INTERRUPTS+48) /* 48: UART4 global interrupt */
# define STM32_IRQ_UART5 (STM32_IRQ_INTERRUPTS+49) /* 49: UART5 global interrupt */
# define STM32_IRQ_DMA2CH1 (STM32_IRQ_INTERRUPTS+50) /* 50: DMA2 channel 1 global interrupt */
# define STM32_IRQ_DMA2CH2 (STM32_IRQ_INTERRUPTS+51) /* 51: DMA2 channel 2 global interrupt */
# define STM32_IRQ_DMA2CH3 (STM32_IRQ_INTERRUPTS+52) /* 52: DMA2 channel 3 global interrupt */

13
arch/arm/src/stm32/Kconfig
View File

@ -163,6 +163,16 @@ config ARCH_CHIP_STM32L152VB
STM32L 100-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPRROM with
4x44/8x40 LCD interface
config ARCH_CHIP_STM32L162ZD
bool "STM32L162ZD"
select ARCH_CORTEXM3
select STM32_STM32L15XX
select STM32_ENERGYLITE
select STM32_HIGHDENSITY
---help---
STM32L 144-pin EnergyLite, 384KB FLASH, 48KB SRAM, 12KB EEPRROM with
8x40 LCD interface
config ARCH_CHIP_STM32F100C8
bool "STM32F100C8"
select ARCH_CORTEXM3
@ -563,6 +573,7 @@ config ARCH_CHIP_STM32F429N
endchoice
# This is really 15XX/16XX, but we treat the two the same.
config STM32_STM32L15XX
bool
default n
@ -2808,7 +2819,7 @@ config USART1_RS485_DIR_POLARITY
config USART1_RXDMA
bool "USART1 Rx DMA"
default n
depends on STM32_USART1 && ((STM32STM32F10XX && STM32_DMA1) || (!STM32_STM32F10XX && STM32_DMA2))
depends on STM32_USART1 && (((STM32_STM32F10XX || STM32_STM32L15XX) && STM32_DMA1) || (!STM32_STM32F10XX && STM32_DMA2))
---help---
In high data rate usage, Rx DMA may eliminate Rx overrun errors

2
arch/arm/src/stm32/chip/stm32_usbdev.h
View File

@ -43,7 +43,7 @@
#include <nuttx/config.h>
#include <chip.h>
#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
/************************************************************************************
* Definitions

4
arch/arm/src/stm32/chip/stm32l15xxx_memorymap.h
View File

@ -95,8 +95,8 @@
#define STM32_SPI3_BASE 0x40003c00 /* 0x40003c00-0x40003fff SPI3 */
#define STM32_USART2_BASE 0x40004400 /* 0x40004400-0x400047ff USART2 */
#define STM32_USART3_BASE 0x40004800 /* 0x40004800-0x40004bff USART3 */
#define STM32_USART4_BASE 0x40004c00 /* 0x40004c00-0x40004fff USART4 */
#define STM32_USART5_BASE 0x40005000 /* 0x40005000-0x400053ff USART5 */
#define STM32_UART4_BASE 0x40004c00 /* 0x40004c00-0x40004fff UART4 */
#define STM32_UART5_BASE 0x40005000 /* 0x40005000-0x400053ff UART5 */
#define STM32_I2C1_BASE 0x40005400 /* 0x40005400-0x400057ff I2C1 */
#define STM32_I2C2_BASE 0x40005800 /* 0x40005800-0x40005bff I2C2 */
#define STM32_USB_BASE 0x40005c00 /* 0x40005c00-0x40005fff USB device FS */

67
arch/arm/src/stm32/chip/stm32l15xxx_pinmap.h
View File

@ -105,7 +105,7 @@
/* I2C */
#define GPIO_I2C1_SCL_1 (GPIO_ALT | GPIO_AF3 | GPIO_SPEED_40MHz | GPIO_OPENDRAIN | GPIO_PORTB | GPIO_PIN6)
#define GPIO_I2C1_SCL_1 (GPIO_ALT | GPIO_AF4 | GPIO_SPEED_40MHz | GPIO_OPENDRAIN | GPIO_PORTB | GPIO_PIN6)
#define GPIO_I2C1_SCL_2 (GPIO_ALT | GPIO_AF4 | GPIO_SPEED_40MHz | GPIO_OPENDRAIN | GPIO_PORTB | GPIO_PIN8)
#define GPIO_I2C1_SDA_1 (GPIO_ALT | GPIO_AF4 | GPIO_SPEED_40MHz | GPIO_OPENDRAIN | GPIO_PORTB | GPIO_PIN7)
#define GPIO_I2C1_SDA_2 (GPIO_ALT | GPIO_AF4 | GPIO_SPEED_40MHz | GPIO_OPENDRAIN | GPIO_PORTB | GPIO_PIN9)
@ -277,6 +277,38 @@
#define GPIO_PE13_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTE | GPIO_PIN13)
#define GPIO_PE14_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTE | GPIO_PIN14)
#define GPIO_PE15_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTE | GPIO_PIN15)
#define GPIO_PF0_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTF | GPIO_PIN0)
#define GPIO_PF1_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTF | GPIO_PIN1)
#define GPIO_PF2_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTF | GPIO_PIN2)
#define GPIO_PF3_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTF | GPIO_PIN3)
#define GPIO_PF4_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTF | GPIO_PIN4)
#define GPIO_PF5_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTF | GPIO_PIN5)
#define GPIO_PF6_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTF | GPIO_PIN6)
#define GPIO_PF7_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTF | GPIO_PIN7)
#define GPIO_PF8_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTF | GPIO_PIN8)
#define GPIO_PF9_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTF | GPIO_PIN9)
#define GPIO_PF10_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTF | GPIO_PIN10)
#define GPIO_PF11_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTF | GPIO_PIN11)
#define GPIO_PF12_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTF | GPIO_PIN12)
#define GPIO_PF13_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTF | GPIO_PIN13)
#define GPIO_PF14_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTF | GPIO_PIN14)
#define GPIO_PF15_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTF | GPIO_PIN15)
#define GPIO_PG0_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTG | GPIO_PIN0)
#define GPIO_PG1_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTG | GPIO_PIN1)
#define GPIO_PG2_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTG | GPIO_PIN2)
#define GPIO_PG3_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTG | GPIO_PIN3)
#define GPIO_PG4_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTG | GPIO_PIN4)
#define GPIO_PG5_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTG | GPIO_PIN5)
#define GPIO_PG6_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTG | GPIO_PIN6)
#define GPIO_PG7_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTG | GPIO_PIN7)
#define GPIO_PG8_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTG | GPIO_PIN8)
#define GPIO_PG9_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTG | GPIO_PIN9)
#define GPIO_PG10_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTG | GPIO_PIN10)
#define GPIO_PG11_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTG | GPIO_PIN11)
#define GPIO_PG12_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTG | GPIO_PIN12)
#define GPIO_PG13_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTG | GPIO_PIN13)
#define GPIO_PG14_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTG | GPIO_PIN14)
#define GPIO_PG15_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTG | GPIO_PIN15)
/* RTC */
@ -311,12 +343,21 @@
#define GPIO_SPI2_SCK_1 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN13)
#define GPIO_SPI2_SCK_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTD | GPIO_PIN1)
#define GPIO_SPI3_MISO_1 (GPIO_ALT | GPIO_AF6 | GPIO_PORTB | GPIO_PIN4)
#define GPIO_SPI3_MISO_2 (GPIO_ALT | GPIO_AF6 | GPIO_PORTC | GPIO_PIN11)
#define GPIO_SPI3_MOSI_1 (GPIO_ALT | GPIO_AF6 | GPIO_PORTB | GPIO_PIN5)
#define GPIO_SPI3_MOSI_2 (GPIO_ALT | GPIO_AF6 | GPIO_PORTC | GPIO_PIN12)
#define GPIO_SPI3_NSS_1 (GPIO_ALT | GPIO_AF6 | GPIO_PORTA | GPIO_PIN4)
#define GPIO_SPI3_NSS_2 (GPIO_ALT | GPIO_AF6 | GPIO_PORTA | GPIO_PIN15)
#define GPIO_SPI3_SCK_1 (GPIO_ALT | GPIO_AF6 | GPIO_PORTB | GPIO_PIN3)
#define GPIO_SPI3_SCK_2 (GPIO_ALT | GPIO_AF6 | GPIO_PORTC | GPIO_PIN10)
/* Timers */
#define GPIO_TIM2_CH1_ETR_1 (GPIO_ALT | GPIO_FLOAT | GPIO_AF1 | GPIO_SPEED_40MHz | GPIO_PORTA | GPIO_PIN0)
#define GPIO_TIM2_CH1_ETR_2 (GPIO_ALT | GPIO_FLOAT | GPIO_AF1 | GPIO_SPEED_40MHz | GPIO_PORTA | GPIO_PIN15)
#define GPIO_TIM2_CH1_ETR_3 (GPIO_ALT | GPIO_FLOAT | GPIO_AF1 | GPIO_SPEED_40MHz | GPIO_PORTE | GPIO_PIN9)
#define GPIO_TIM2_CH1_ETR_4 (GPIO_ALT |GPIO_FLOAT | GPIO_AF2 | GPIO_SPEED_40MHz | GPIO_PORTA | GPIO_PIN5)
#define GPIO_TIM2_CH1_ETR_4 (GPIO_ALT | GPIO_FLOAT | GPIO_AF2 | GPIO_SPEED_40MHz | GPIO_PORTA | GPIO_PIN5)
#define GPIO_TIM2_CH2IN_1 (GPIO_ALT | GPIO_FLOAT | GPIO_AF1 | GPIO_SPEED_40MHz | GPIO_PORTA | GPIO_PIN1)
#define GPIO_TIM2_CH2IN_2 (GPIO_ALT | GPIO_FLOAT | GPIO_AF1 | GPIO_SPEED_40MHz | GPIO_PORTB | GPIO_PIN3)
#define GPIO_TIM2_CH2IN_3 (GPIO_ALT | GPIO_FLOAT | GPIO_AF1 | GPIO_SPEED_40MHz | GPIO_PORTE | GPIO_PIN10)
@ -393,6 +434,22 @@
#define GPIO_TIM4_CH4OUT_2 (GPIO_ALT |GPIO_PUSHPULL | GPIO_AF2 | GPIO_SPEED_40MHz | GPIO_PORTD | GPIO_PIN15)
#define GPIO_TIM4_ETR (GPIO_ALT | GPIO_FLOAT | GPIO_AF2 | GPIO_SPEED_40MHz | GPIO_PORTE | GPIO_PIN0)
#define GPIO_TIM5_CH1IN_1 (GPIO_ALT | GPIO_FLOAT | GPIO_AF2 | GPIO_SPEED_40MHz | GPIO_PORTA | GPIO_PIN0)
#define GPIO_TIM5_CH1OUT_1 (GPIO_ALT | GPIO_PUSHPULL | GPIO_AF2 | GPIO_SPEED_40MHz | GPIO_PORTA | GPIO_PIN0)
#define GPIO_TIM5_CH2IN_1 (GPIO_ALT | GPIO_FLOAT | GPIO_AF2 | GPIO_SPEED_40MHz | GPIO_PORTA | GPIO_PIN2)
#define GPIO_TIM5_CH2OUT_1 (GPIO_ALT | GPIO_PUSHPULL | GPIO_AF2 | GPIO_SPEED_40MHz | GPIO_PORTA | GPIO_PIN2)
#define GPIO_TIM5_CH2IN_2 (GPIO_ALT | GPIO_FLOAT | GPIO_AF2 | GPIO_SPEED_40MHz | GPIO_PORTF | GPIO_PIN7)
#define GPIO_TIM5_CH2OUT_2 (GPIO_ALT | GPIO_PUSHPULL | GPIO_AF2 | GPIO_SPEED_40MHz | GPIO_PORTF | GPIO_PIN7)
#define GPIO_TIM5_CH3IN_1 (GPIO_ALT | GPIO_FLOAT | GPIO_AF2 | GPIO_SPEED_40MHz | GPIO_PORTA | GPIO_PIN3)
#define GPIO_TIM5_CH3OUT_1 (GPIO_ALT | GPIO_PUSHPULL | GPIO_AF2 | GPIO_SPEED_40MHz | GPIO_PORTA | GPIO_PIN3)
#define GPIO_TIM5_CH3IN_2 (GPIO_ALT | GPIO_FLOAT | GPIO_AF2 | GPIO_SPEED_40MHz | GPIO_PORTF | GPIO_PIN8)
#define GPIO_TIM5_CH3OUT_2 (GPIO_ALT | GPIO_PUSHPULL | GPIO_AF2 | GPIO_SPEED_40MHz | GPIO_PORTF | GPIO_PIN8)
#define GPIO_TIM5_CH4IN_1 (GPIO_ALT | GPIO_FLOAT | GPIO_AF2 | GPIO_SPEED_40MHz | GPIO_PORTA | GPIO_PIN4)
#define GPIO_TIM5_CH4OUT_1 (GPIO_ALT | GPIO_PUSHPULL | GPIO_AF2 | GPIO_SPEED_40MHz | GPIO_PORTA | GPIO_PIN4)
#define GPIO_TIM5_CH4IN_2 (GPIO_ALT | GPIO_FLOAT | GPIO_AF2 | GPIO_SPEED_40MHz | GPIO_PORTF | GPIO_PIN9)
#define GPIO_TIM5_CH4OUT_2 (GPIO_ALT | GPIO_PUSHPULL | GPIO_AF2 | GPIO_SPEED_40MHz | GPIO_PORTF | GPIO_PIN9)
#define GPIO_TIM5_ETR (GPIO_ALT | GPIO_FLOAT | GPIO_AF2 | GPIO_SPEED_40MHz | GPIO_PORTF | GPIO_PIN6)
#define GPIO_TIM9_CH1IN_1 (GPIO_ALT | GPIO_FLOAT | GPIO_AF3 | GPIO_SPEED_40MHz | GPIO_PORTA | GPIO_PIN2)
#define GPIO_TIM9_CH1IN_2 (GPIO_ALT | GPIO_FLOAT | GPIO_AF3 | GPIO_SPEED_40MHz | GPIO_PORTB | GPIO_PIN13)
#define GPIO_TIM9_CH1IN_3 (GPIO_ALT | GPIO_FLOAT | GPIO_AF3 | GPIO_SPEED_40MHz | GPIO_PORTD | GPIO_PIN0)
@ -531,6 +588,12 @@
#define GPIO_USART3_TX_2 (GPIO_ALT | GPIO_PULLUP | GPIO_AF7 | GPIO_SPEED_40MHz | GPIO_PUSHPULL | GPIO_PORTC | GPIO_PIN10)
#define GPIO_USART3_TX_3 (GPIO_ALT | GPIO_PULLUP | GPIO_AF7 | GPIO_SPEED_40MHz | GPIO_PUSHPULL | GPIO_PORTD | GPIO_PIN8)
#define GPIO_UART4_RX (GPIO_ALT | GPIO_PULLUP | GPIO_AF8 | GPIO_SPEED_40MHz | GPIO_PUSHPULL | GPIO_PORTC | GPIO_PIN11)
#define GPIO_UART4_TX (GPIO_ALT | GPIO_PULLUP | GPIO_AF8 | GPIO_SPEED_40MHz | GPIO_PUSHPULL | GPIO_PORTC | GPIO_PIN10)
#define GPIO_UART5_RX (GPIO_ALT | GPIO_PULLUP | GPIO_AF8 | GPIO_SPEED_40MHz | GPIO_PUSHPULL | GPIO_PORTD | GPIO_PIN2)
#define GPIO_UART5_TX (GPIO_ALT | GPIO_PULLUP | GPIO_AF8 | GPIO_SPEED_40MHz | GPIO_PUSHPULL | GPIO_PORTC | GPIO_PIN12)
/* USB */
#define GPIO_USB_DM (GPIO_ALT | GPIO_AF10 | GPIO_SPEED_40MHz | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN11)

12
arch/arm/src/stm32/chip/stm32l15xxx_rcc.h
View File

@ -283,8 +283,8 @@
/* Bit 16: Reserved */
#define RCC_APB1RSTR_USART2RST (1 << 17) /* Bit 17: USART 2 reset */
#define RCC_APB1RSTR_USART3RST (1 << 18) /* Bit 18: USART 3 reset */
#define RCC_APB1RSTR_USART4RST (1 << 19) /* Bit 19: USART 4 reset */
#define RCC_APB1RSTR_USART5RST (1 << 20) /* Bit 20: USART 5 reset */
#define RCC_APB1RSTR_UART4RST (1 << 19) /* Bit 19: UART 4 reset */
#define RCC_APB1RSTR_UART5RST (1 << 20) /* Bit 20: UART 5 reset */
#define RCC_APB1RSTR_I2C1RST (1 << 21) /* Bit 21: I2C 1 reset */
#define RCC_APB1RSTR_I2C2RST (1 << 22) /* Bit 22: I2C 2 reset */
#define RCC_APB1RSTR_USBRST (1 << 23) /* Bit 23: USB reset */
@ -352,8 +352,8 @@
/* Bit 16: Reserved */
#define RCC_APB1ENR_USART2EN (1 << 17) /* Bit 17: USART 2 clock enable */
#define RCC_APB1ENR_USART3EN (1 << 18) /* Bit 18: USART 3 clock enable */
#define RCC_APB1ENR_USART4EN (1 << 19) /* Bit 19: USART 4 clock enable */
#define RCC_APB1ENR_USART5EN (1 << 20) /* Bit 20: USART 5 clock enable */
#define RCC_APB1ENR_UART4EN (1 << 19) /* Bit 19: UART 4 clock enable */
#define RCC_APB1ENR_UART5EN (1 << 20) /* Bit 20: UART 5 clock enable */
#define RCC_APB1ENR_I2C1EN (1 << 21) /* Bit 21: I2C 1 clock enable */
#define RCC_APB1ENR_I2C2EN (1 << 22) /* Bit 22: I2C 2 clock enable */
#define RCC_APB1ENR_USBEN (1 << 23) /* Bit 23: USB clock enable */
@ -421,8 +421,8 @@
/* Bit 16: Reserved */
#define RCC_APB1LPENR_USART2LPEN (1 << 17) /* Bit 17: USART 2 clock enable during sleep mode */
#define RCC_APB1LPENR_USART3LPEN (1 << 18) /* Bit 18: USART 3 clock enable during sleep mode */
#define RCC_APB1LPENR_USART4LPEN (1 << 19) /* Bit 19: USART 4 clock enable during sleep mode */
#define RCC_APB1LPENR_USART5LPEN (1 << 20) /* Bit 20: USART 5 clock enable during sleep mode */
#define RCC_APB1LPENR_UART4LPEN (1 << 19) /* Bit 19: UART 4 clock enable during sleep mode */
#define RCC_APB1LPENR_UART5LPEN (1 << 20) /* Bit 20: UART 5 clock enable during sleep mode */
#define RCC_APB1LPENR_I2C1LPEN (1 << 21) /* Bit 21: I2C 1 clock enable during sleep mode */
#define RCC_APB1LPENR_I2C2LPEN (1 << 22) /* Bit 22: I2C 2 clock enable during sleep mode */
#define RCC_APB1LPENR_USBLPEN (1 << 23) /* Bit 23: USB clock enable during sleep mode */

24
arch/arm/src/stm32/chip/stm32l15xxx_uart.h
View File

@ -93,21 +93,21 @@
#endif
#if STM32_NUSART > 3
# define STM32_USART4_SR (STM32_USART4_BASE+STM32_USART_SR_OFFSET)
# define STM32_USART4_DR (STM32_USART4_BASE+STM32_USART_DR_OFFSET)
# define STM32_USART4_BRR (STM32_USART4_BASE+STM32_USART_BRR_OFFSET)
# define STM32_USART4_CR1 (STM32_USART4_BASE+STM32_USART_CR1_OFFSET)
# define STM32_USART4_CR2 (STM32_USART4_BASE+STM32_USART_CR2_OFFSET)
# define STM32_USART4_CR3 (STM32_USART4_BASE+STM32_USART_CR3_OFFSET)
# define STM32_UART4_SR (STM32_UART4_BASE+STM32_USART_SR_OFFSET)
# define STM32_UART4_DR (STM32_UART4_BASE+STM32_USART_DR_OFFSET)
# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET)
# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET)
# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET)
# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET)
#endif
#if STM32_NUSART > 4
# define STM32_USART5_SR (STM32_USART5_BASE+STM32_USART_SR_OFFSET)
# define STM32_USART5_DR (STM32_USART5_BASE+STM32_USART_DR_OFFSET)
# define STM32_USART5_BRR (STM32_USART5_BASE+STM32_USART_BRR_OFFSET)
# define STM32_USART5_CR1 (STM32_USART5_BASE+STM32_USART_CR1_OFFSET)
# define STM32_USART5_CR2 (STM32_USART5_BASE+STM32_USART_CR2_OFFSET)
# define STM32_USART5_CR3 (STM32_USART5_BASE+STM32_USART_CR3_OFFSET)
# define STM32_UART5_SR (STM32_UART5_BASE+STM32_USART_SR_OFFSET)
# define STM32_UART5_DR (STM32_UART5_BASE+STM32_USART_DR_OFFSET)
# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET)
# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET)
# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET)
# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET)
#endif
/* Register Bitfield Definitions ****************************************************/

4
arch/arm/src/stm32/chip/stm32l15xxx_vectors.h
View File

@ -242,8 +242,8 @@
VECTOR(stm32_sdio, STM32_IRQ_SDIO) /* 45: SDIO Global interrupt */
VECTOR(stm32_tim5, STM32_IRQ_TIM5) /* 46: TIM5 global interrupt */
VECTOR(stm32_spi3, STM32_IRQ_SPI3) /* 47: SPI3 global interrupt */
VECTOR(stm32_usart4, STM32_IRQ_USART4) /* 48: USART4 global interrupt */
VECTOR(stm32_usart5, STM32_IRQ_USART5) /* 49: USART5 global interrupt */
VECTOR(stm32_usart4, STM32_IRQ_UART4) /* 48: UART4 global interrupt */
VECTOR(stm32_usart5, STM32_IRQ_UART5) /* 49: UART5 global interrupt */
VECTOR(stm32_dma2ch1, STM32_IRQ_DMA2CH1) /* 50: DMA2 channel 1 global interrupt */
VECTOR(stm32_dma2ch2, STM32_IRQ_DMA2CH2) /* 51: DMA2 channel 2 global interrupt */
VECTOR(stm32_dma2ch3, STM32_IRQ_DMA2CH3) /* 52: DMA2 channel 3 global interrupt */

17
arch/arm/src/stm32/stm32_gpio.c
View File

@ -89,6 +89,21 @@ const uint32_t g_gpiobase[STM32_NGPIO_PORTS] =
#if STM32_NGPIO_PORTS > 4
STM32_GPIOE_BASE,
#endif
#if defined(CONFIG_STM32_STM32L15XX)
#if STM32_NGPIO_PORTS > 5
STM32_GPIOH_BASE,
#endif
#if STM32_NGPIO_PORTS > 6
STM32_GPIOF_BASE,
#endif
#if STM32_NGPIO_PORTS > 7
STM32_GPIOG_BASE,
#endif
#else
#if STM32_NGPIO_PORTS > 5
STM32_GPIOF_BASE,
#endif
@ -101,6 +116,8 @@ const uint32_t g_gpiobase[STM32_NGPIO_PORTS] =
#if STM32_NGPIO_PORTS > 8
STM32_GPIOI_BASE,
#endif
#endif /* CONFIG_STM32_STM32L15XX */
};
/****************************************************************************

6
arch/arm/src/stm32/stm32_gpio.h
View File

@ -354,12 +354,18 @@
# define GPIO_PORTC (2 << GPIO_PORT_SHIFT) /* GPIOC */
# define GPIO_PORTD (3 << GPIO_PORT_SHIFT) /* GPIOD */
# define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */
#if defined (CONFIG_STM32_STM32L15XX)
# define GPIO_PORTH (5 << GPIO_PORT_SHIFT) /* GPIOH */
# define GPIO_PORTF (6 << GPIO_PORT_SHIFT) /* GPIOF */
# define GPIO_PORTG (7 << GPIO_PORT_SHIFT) /* GPIOG */
#else
# define GPIO_PORTF (5 << GPIO_PORT_SHIFT) /* GPIOF */
# define GPIO_PORTG (6 << GPIO_PORT_SHIFT) /* GPIOG */
# define GPIO_PORTH (7 << GPIO_PORT_SHIFT) /* GPIOH */
# define GPIO_PORTI (8 << GPIO_PORT_SHIFT) /* GPIOI */
# define GPIO_PORTJ (9 << GPIO_PORT_SHIFT) /* GPIOJ */
# define GPIO_PORTK (10 << GPIO_PORT_SHIFT) /* GPIOK */
#endif
/* This identifies the bit in the port:
*

20
arch/arm/src/stm32/stm32_i2c.c
View File

@ -7,7 +7,7 @@
*
* With extensions, modifications by:
*
* Copyright (C) 2011-2013 Gregory Nutt. All rights reserved.
* Copyright (C) 2011-2014 Gregory Nutt. All rights reserved.
* Author: Gregroy Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -95,17 +95,19 @@
/* At least one I2C peripheral must be enabled */
#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || defined(CONFIG_STM32_I2C3)
#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || \
defined(CONFIG_STM32_I2C3)
/* This implementation is for the STM32 F1, F2, and F4 only */
/* Experimentally enabled for STM32L15XX */
#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F20XX) || \
defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \
defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Configuration ********************************************************************/
/* CONFIG_I2C_POLLED may be set so that I2C interrrupts will not be used. Instead,
/* CONFIG_I2C_POLLED may be set so that I2C interrupts will not be used. Instead,
* CPU-intensive polling will be used.
*/
@ -143,7 +145,10 @@
/* Macros to convert a I2C pin to a GPIO output */
#if defined(CONFIG_STM32_STM32F10XX)
#if defined(CONFIG_STM32_STM32L15XX)
# define I2C_OUTPUT (GPIO_OUTPUT | GPIO_OUTPUT_SET | GPIO_OPENDRAIN | \
GPIO_SPEED_40MHz)
#elif defined(CONFIG_STM32_STM32F10XX)
# define I2C_OUTPUT (GPIO_OUTPUT | GPIO_OUTPUT_SET | GPIO_CNF_OUTOD | \
GPIO_MODE_50MHz)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
@ -1284,7 +1289,8 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
* the F1 in that BTF is not set after data is received (only RXNE).
*/
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) || \
defined(CONFIG_STM32_STM32L15XX)
if (priv->dcnt <= 0 && (status & (I2C_SR1_BTF|I2C_SR1_RXNE)) != 0)
#else
if (priv->dcnt <= 0 && (status & I2C_SR1_BTF) != 0)

1
arch/arm/src/stm32/stm32_idle.c
View File

@ -39,6 +39,7 @@
#include <arch/board/board.h>
#include <nuttx/config.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/power/pm.h>

20
arch/arm/src/stm32/stm32_lowputc.c
View File

@ -63,6 +63,8 @@
# if defined(CONFIG_USART1_SERIAL_CONSOLE)
# define STM32_CONSOLE_BASE STM32_USART1_BASE
# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY
# define STM32_CONSOLE_APBREG STM32_RCC_APB2ENR
# define STM32_CONSOLE_APBEN RCC_APB2ENR_USART1EN
# define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD
# define STM32_CONSOLE_BITS CONFIG_USART1_BITS
# define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY
@ -80,6 +82,8 @@
# elif defined(CONFIG_USART2_SERIAL_CONSOLE)
# define STM32_CONSOLE_BASE STM32_USART2_BASE
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR
# define STM32_CONSOLE_APBEN RCC_APB1ENR_USART2EN
# define STM32_CONSOLE_BAUD CONFIG_USART2_BAUD
# define STM32_CONSOLE_BITS CONFIG_USART2_BITS
# define STM32_CONSOLE_PARITY CONFIG_USART2_PARITY
@ -97,6 +101,8 @@
# elif defined(CONFIG_USART3_SERIAL_CONSOLE)
# define STM32_CONSOLE_BASE STM32_USART3_BASE
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR
# define STM32_CONSOLE_APBEN RCC_APB1ENR_USART3EN
# define STM32_CONSOLE_BAUD CONFIG_USART3_BAUD
# define STM32_CONSOLE_BITS CONFIG_USART3_BITS
# define STM32_CONSOLE_PARITY CONFIG_USART3_PARITY
@ -114,6 +120,8 @@
# elif defined(CONFIG_UART4_SERIAL_CONSOLE)
# define STM32_CONSOLE_BASE STM32_UART4_BASE
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR
# define STM32_CONSOLE_APBEN RCC_APB1ENR_UART4EN
# define STM32_CONSOLE_BAUD CONFIG_UART4_BAUD
# define STM32_CONSOLE_BITS CONFIG_UART4_BITS
# define STM32_CONSOLE_PARITY CONFIG_UART4_PARITY
@ -131,6 +139,8 @@
# elif defined(CONFIG_UART5_SERIAL_CONSOLE)
# define STM32_CONSOLE_BASE STM32_UART5_BASE
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR
# define STM32_CONSOLE_APBEN RCC_APB1ENR_UART5EN
# define STM32_CONSOLE_BAUD CONFIG_UART5_BAUD
# define STM32_CONSOLE_BITS CONFIG_UART5_BITS
# define STM32_CONSOLE_PARITY CONFIG_UART5_PARITY
@ -148,6 +158,8 @@
# elif defined(CONFIG_USART6_SERIAL_CONSOLE)
# define STM32_CONSOLE_BASE STM32_USART6_BASE
# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY
# define STM32_CONSOLE_APBREG STM32_RCC_APB2ENR
# define STM32_CONSOLE_APBEN RCC_APB2ENR_USART6EN
# define STM32_CONSOLE_BAUD CONFIG_USART6_BAUD
# define STM32_CONSOLE_BITS CONFIG_USART6_BITS
# define STM32_CONSOLE_PARITY CONFIG_USART6_PARITY
@ -165,6 +177,8 @@
# elif defined(CONFIG_UART7_SERIAL_CONSOLE)
# define STM32_CONSOLE_BASE STM32_UART7_BASE
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR
# define STM32_CONSOLE_APBEN RCC_APB1ENR_UART7EN
# define STM32_CONSOLE_BAUD CONFIG_UART7_BAUD
# define STM32_CONSOLE_BITS CONFIG_UART7_BITS
# define STM32_CONSOLE_PARITY CONFIG_UART7_PARITY
@ -182,6 +196,8 @@
# elif defined(CONFIG_UART8_SERIAL_CONSOLE)
# define STM32_CONSOLE_BASE STM32_UART8_BASE
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR
# define STM32_CONSOLE_APBEN RCC_APB1ENR_UART8EN
# define STM32_CONSOLE_BAUD CONFIG_UART8_BAUD
# define STM32_CONSOLE_BITS CONFIG_UART8_BITS
# define STM32_CONSOLE_PARITY CONFIG_UART8_PARITY
@ -556,6 +572,10 @@ void stm32_lowsetup(void)
uint32_t cr;
#endif
/* Enable USART APB1/2 clock */
modifyreg32(STM32_CONSOLE_APBREG, 0, STM32_CONSOLE_APBEN);
/* Enable the console USART and configure GPIO pins needed for rx/tx.
*
* NOTE: Clocking for selected U[S]ARTs was already provided in stm32_rcc.c

131
arch/arm/src/stm32/stm32_pwm.c
View File

@ -80,7 +80,12 @@
#define TIMTYPE_ADVANCED 4 /* Advanced timers: TIM1-8 */
#define TIMTYPE_TIM1 TIMTYPE_ADVANCED
#ifdef CONFIG_STM32_STM32F10XX
#ifdef CONFIG_STM32_STM32L15XX
# define TIMTYPE_TIM2 TIMTYPE_GENERAL16
# define TIMTYPE_TIM3 TIMTYPE_GENERAL16
# define TIMTYPE_TIM4 TIMTYPE_GENERAL16
# define TIMTYPE_TIM5 TIMTYPE_GENERAL32
#elif defined(CONFIG_STM32_STM32F10XX)
# define TIMTYPE_TIM2 TIMTYPE_GENERAL16
# define TIMTYPE_TIM3 TIMTYPE_GENERAL16
# define TIMTYPE_TIM4 TIMTYPE_GENERAL16
@ -131,7 +136,7 @@
/****************************************************************************
* Private Types
****************************************************************************/
/* This structure representst the state of one PWM timer */
/* This structure represents the state of one PWM timer */
struct stm32_pwmtimer_s
{
@ -1106,6 +1111,113 @@ static uint8_t pwm_pulsecount(uint32_t count)
}
#endif
/****************************************************************************
* Name: pwm_set_apb_clock
*
* Description:
* Enable or disable APB clock for the timer peripheral
*
* Input parameters:
* dev - A reference to the lower half PWM driver state structure
* on - Enable clock if 'on' is 'true' and disable if 'false'
*
****************************************************************************/
static void pwm_set_apb_clock(FAR struct stm32_pwmtimer_s *priv, bool on)
{
uint32_t en_bit;
uint32_t regaddr;
/* Determine which timer to configure */
switch (priv->timid)
{
#ifdef CONFIG_STM32_TIM1_PWM
case 1:
regaddr = STM32_RCC_APB2ENR;
en_bit = RCC_APB2ENR_TIM1EN;
break;
#endif
#ifdef CONFIG_STM32_TIM2_PWM
case 2:
regaddr = STM32_RCC_APB1ENR;
en_bit = RCC_APB1ENR_TIM2EN;
break;
#endif
#ifdef CONFIG_STM32_TIM3_PWM
case 3:
regaddr = STM32_RCC_APB1ENR;
en_bit = RCC_APB1ENR_TIM3EN;
break;
#endif
#ifdef CONFIG_STM32_TIM4_PWM
case 4:
regaddr = STM32_RCC_APB1ENR;
en_bit = RCC_APB1ENR_TIM4EN;
break;
#endif
#ifdef CONFIG_STM32_TIM5_PWM
case 5:
regaddr = STM32_RCC_APB1ENR;
en_bit = RCC_APB1ENR_TIM5EN;
break;
#endif
#ifdef CONFIG_STM32_TIM8_PWM
case 8:
regaddr = STM32_RCC_APB2ENR;
en_bit = RCC_APB2ENR_TIM8EN;
break;
#endif
#ifdef CONFIG_STM32_TIM9_PWM
case 9:
regaddr = STM32_RCC_APB2ENR;
en_bit = RCC_APB2ENR_TIM9EN;
break;
#endif
#ifdef CONFIG_STM32_TIM10_PWM
case 10:
regaddr = STM32_RCC_APB2ENR;
en_bit = RCC_APB2ENR_TIM10EN;
break;
#endif
#ifdef CONFIG_STM32_TIM11_PWM
case 11:
regaddr = STM32_RCC_APB2ENR;
en_bit = RCC_APB2ENR_TIM11EN;
break;
#endif
#ifdef CONFIG_STM32_TIM12_PWM
case 12:
regaddr = STM32_RCC_APB1ENR;
en_bit = RCC_APB1ENR_TIM12EN;
break;
#endif
#ifdef CONFIG_STM32_TIM13_PWM
case 13:
regaddr = STM32_RCC_APB1ENR;
en_bit = RCC_APB1ENR_TIM13EN;
break;
#endif
#ifdef CONFIG_STM32_TIM14_PWM
case 14:
regaddr = STM32_RCC_APB1ENR;
en_bit = RCC_APB1ENR_TIM14EN;
break;
#endif
}
/* Enable/disable APB 1/2 clock for timer */
if (on)
{
modifyreg32(regaddr, 0, en_bit);
}
else
{
modifyreg32(regaddr, en_bit, 0);
}
}
/****************************************************************************
* Name: pwm_setup
*
@ -1121,8 +1233,8 @@ static uint8_t pwm_pulsecount(uint32_t count)
* Zero on success; a negated errno value on failure
*
* Assumptions:
* AHB1 or 2 clocking for the GPIOs and timer has already been configured
* by the RCC logic at power up.
* APB1 or 2 clocking for the GPIOs has already been configured by the RCC
* logic at power up.
*
****************************************************************************/
@ -1133,6 +1245,10 @@ static int pwm_setup(FAR struct pwm_lowerhalf_s *dev)
pwmvdbg("TIM%d pincfg: %08x\n", priv->timid, priv->pincfg);
pwm_dumpregs(priv, "Initially");
/* Enable APB1/2 clocking for timer. */
pwm_set_apb_clock(priv, true);
/* Configure the PWM output pin, but do not start the timer yet */
stm32_configgpio(priv->pincfg);
@ -1167,13 +1283,18 @@ static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev)
pwm_stop(dev);
/* Disable APB1/2 clocking for timer. */
pwm_set_apb_clock(priv, false);
/* Then put the GPIO pin back to the default state */
pincfg = priv->pincfg & (GPIO_PORT_MASK|GPIO_PIN_MASK);
#if defined(CONFIG_STM32_STM32F10XX)
pincfg |= (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT);
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) || \
defined(CONFIG_STM32_STM32L15XX)
pincfg |= (GPIO_INPUT|GPIO_FLOAT);
#else
# error "Unrecognized STM32 chip"

9
arch/arm/src/stm32/stm32_spi.c
View File

@ -107,7 +107,7 @@
# if defined(CONFIG_SPI_DMAPRIO)
# define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO
# elif defined(CONFIG_STM32_STM32F10XX)
# elif defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32L15XX)
# define SPI_DMA_PRIO DMA_CCR_PRIMED
# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define SPI_DMA_PRIO DMA_SCR_PRIMED
@ -115,7 +115,7 @@
# error "Unknown STM32 DMA"
# endif
# if defined(CONFIG_STM32_STM32F10XX)
# if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32L15XX)
# if (SPI_DMA_PRIO & ~DMA_CCR_PL_MASK) != 0
# error "Illegal value for CONFIG_SPI_DMAPRIO"
# endif
@ -131,7 +131,8 @@
/* DMA channel configuration */
#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32L15XX)
# define SPI_RXDMA16_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_16BITS|DMA_CCR_PSIZE_16BITS|DMA_CCR_MINC )
# define SPI_RXDMA8_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS |DMA_CCR_MINC )
# define SPI_RXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_16BITS )
@ -1035,7 +1036,9 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
actual = priv->spiclock >> 8;
}
spi_modifycr1(priv, 0, SPI_CR1_SPE);
spi_modifycr1(priv, setbits, SPI_CR1_BR_MASK);
spi_modifycr1(priv, SPI_CR1_SPE, 0);
/* Save the frequency selection so that subsequent reconfigurations will be
* faster.

23
arch/arm/src/stm32/stm32f10xxx_dma.c
View File

@ -56,9 +56,9 @@
#include "stm32_dma.h"
#include "stm32.h"
/* Only for the STM32F10xx family for now */
#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32L15XX)
/****************************************************************************
* Pre-processor Definitions
@ -157,7 +157,8 @@ static struct stm32_dma_s g_dma[DMA_NCHANNELS] =
},
{
.chan = 3,
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F30XX)
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32L15XX)
.irq = STM32_IRQ_DMA2CH4,
#else
.irq = STM32_IRQ_DMA2CH45,
@ -166,7 +167,8 @@ static struct stm32_dma_s g_dma[DMA_NCHANNELS] =
},
{
.chan = 4,
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F30XX)
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32L15XX)
.irq = STM32_IRQ_DMA2CH5,
#else
.irq = STM32_IRQ_DMA2CH45,
@ -288,7 +290,8 @@ static int stm32_dmainterrupt(int irq, void *context)
}
else
#if STM32_NDMA > 1
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F30XX)
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32L15XX)
if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH5)
#else
if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH45)
@ -637,24 +640,24 @@ bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr)
* multiply.
*/
switch (ccr & STM32_DMA_SCR_MSIZE_MASK)
switch (ccr & DMA_CCR_MSIZE_MASK)
{
case DMA_SCR_MSIZE_8BITS:
case DMA_CCR_MSIZE_8BITS:
transfer_size = 1;
mend = maddr + count - 1;
break;
case DMA_SCR_MSIZE_16BITS:
case DMA_CCR_MSIZE_16BITS:
transfer_size = 2;
mend = maddr + (count << 1) - 1;
break;
case DMA_SCR_MSIZE_32BITS:
case DMA_CCR_MSIZE_32BITS:
transfer_size = 4;
mend = maddr + (count << 2) - 1;
break;
default
default:
return false;
}

24
arch/arm/src/stm32/stm32l15xxx_rcc.c
View File

@ -303,25 +303,33 @@ static inline void rcc_enableapb1(void)
#ifdef CONFIG_STM32_USART2
/* USART 2 clock enable */
#ifdef CONFIG_STM32_FORCEPOWER
regval |= RCC_APB1ENR_USART2EN;
#endif
#endif
#ifdef CONFIG_STM32_USART3
/* USART 3 clock enable */
#ifdef CONFIG_STM32_FORCEPOWER
regval |= RCC_APB1ENR_USART3EN;
#endif
#ifdef CONFIG_STM32_USART4
/* USART 4 clock enable */
regval |= RCC_APB1ENR_USART4EN;
#endif
#ifdef CONFIG_STM32_USART5
#ifdef CONFIG_STM32_UART4
/* USART 4 clock enable */
#ifdef CONFIG_STM32_FORCEPOWER
regval |= RCC_APB1ENR_UART4EN;
#endif
#endif
#ifdef CONFIG_STM32_UART5
/* USART 5 clock enable */
regval |= RCC_APB1ENR_USART5EN;
#ifdef CONFIG_STM32_FORCEPOWER
regval |= RCC_APB1ENR_UART5EN;
#endif
#endif
#ifdef CONFIG_STM32_I2C1
@ -431,7 +439,9 @@ static inline void rcc_enableapb2(void)
#ifdef CONFIG_STM32_USART1
/* USART1 clock enable */
#ifdef CONFIG_STM32_FORCEPOWER
regval |= RCC_APB2ENR_USART1EN;
#endif
#endif
putreg32(regval, STM32_RCC_APB2ENR);