Add PHY setup for STM3240G-EVAL Ethernet driver
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4151 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
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@ -374,10 +374,29 @@ STM3240G-EVAL-specific Configuration Options
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CONFIG_SDIO_WIDTH_D1_ONLY - Select 1-bit transfer mode. Default:
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4-bit transfer mode.
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CONFIG_STM32_PHYADDR - The 5-bit address of the PHY on the board
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CONFIG_STM32_MII - Support Ethernet MII interface
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CONFIG_STM32_MII_MCO1 - Use MCO1 to clock the MII interface
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CONFIG_STM32_MII_MCO2 - Use MCO2 to clock the MII interface
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CONFIG_STM32_RMII - Support Ethernet RMII interface
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CONFIG_STM32_AUTONEG - Use PHY autonegotion to determine speed and mode
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CONFIG_STM32_ETHFD - If CONFIG_STM32_AUTONEG is not defined, then this
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may be defined to select full duplex mode. Default: half-duplex
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CONFIG_STM32_ETH100MBPS - If CONFIG_STM32_AUTONEG is not defined, then this
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may be defined to select 100 MBps speed. Default: 10 Mbps
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CONFIG_STM32_PHYSR - This must be provided if CONFIG_STM32_AUTONEG is
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defined. The PHY status register address may diff from PHY to PHY. This
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configuration sets the address of the PHY status register.
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CONFIG_STM32_PHYSR_SPEED - This must be provided if CONFIG_STM32_AUTONEG is
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defined. This provides bit mask indicating 10 or 100MBps speed.
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CONFIG_STM32_PHYSR_100MBPS - This must be provided if CONFIG_STM32_AUTONEG is
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defined. This provides the value of the speed bit(s) indicating 100MBps speed.
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CONFIG_STM32_PHYSR_MODE - This must be provided if CONFIG_STM32_AUTONEG is
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defined. This provide bit mask indicating full or half duplex modes.
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CONFIG_STM32_PHYSR_FULLDUPLEX - This must be provided if CONFIG_STM32_AUTONEG is
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defined. This provides the value of the mode bits indicating full duplex mode.
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CONFIG_STM32_ETH_PTP - Precision Time Protocol (PTP). Not supported
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but some hooks are indicated with this condition.
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STM3240G-EVAL LCD Hardware Configuration
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@ -172,8 +172,26 @@
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# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT)
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#endif
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/* LED definitions ******************************************************************/
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/* Ethernet *************************************************************************/
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/* We need to provide clocking to the MII PHY via MCO1 (PA8) */
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#if defined(CONFIG_NET) && defined(CONFIG_STM32_ETHMAC)
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# if !defined(CONFIG_STM32_MII)
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# warning "CONFIG_STM32_MII required for Ethernet"
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# elif !defined(CONFIG_STM32_MII_MCO1)
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# warning "CONFIG_STM32_MII_MCO1 required for Ethernet MII"
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# else
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/* Output HSE clock (25MHz) on MCO1 pin (PA8) to clock the PHY */
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# define BOARD_CFGR_MC01_SOURCE RCC_CFGR_MCO1_HSE
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# define BOARD_CFGR_MC01_DIVIDER RCC_CFGR_MCO1PRE_NONE
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# endif
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#endif
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/* LED definitions ******************************************************************/
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/* The STM3240G-EVAL board has 4 LEDs that we will encode as: */
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#define LED_STARTED 0 /* LED1 */
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@ -185,6 +203,7 @@
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#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */
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#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */
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/* Button definitions ***************************************************************/
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/* The STM3240G-EVAL supports three buttons: */
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#define BUTTON_WAKEUP 0
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@ -200,6 +219,7 @@
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/* Alternate function pin selections ************************************************/
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/* UART3:
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*
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* - PC11 is MicroSDCard_D3 & RS232/IrDA_RX (JP22 open)
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* - PC10 is MicroSDCard_D2 & RSS232/IrDA_TX
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*/
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@ -258,15 +258,44 @@ CONFIG_SSI_POLLWAIT=y
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#
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# STM32F40xxx Ethernet device driver settings
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#
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# CONFIG_STM32_PHYADDR - The 5-bit address of the PHY on the board
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# CONFIG_STM32_MII - Support Ethernet MII interface
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# CONFIG_STM32_MII_MCO1 - Use MCO1 to clock the MII interface
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# CONFIG_STM32_MII_MCO2 - Use MCO2 to clock the MII interface
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# CONFIG_STM32_RMII - Support Ethernet RMII interface
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# CONFIG_STM32_AUTONEG - Use PHY autonegotion to determine speed and mode
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# CONFIG_STM32_ETHFD - If CONFIG_STM32_AUTONEG is not defined, then this
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# may be defined to select full duplex mode. Default: half-duplex
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# CONFIG_STM32_ETH100MBPS - If CONFIG_STM32_AUTONEG is not defined, then this
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# may be defined to select 100 MBps speed. Default: 10 Mbps
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# CONFIG_STM32_PHYSR - This must be provided if CONFIG_STM32_AUTONEG is
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# defined. The PHY status register address may diff from PHY to PHY. This
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# configuration sets the address of the PHY status register.
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# CONFIG_STM32_PHYSR_SPEED - This must be provided if CONFIG_STM32_AUTONEG is
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# defined. This provides bit mask indicating 10 or 100MBps speed.
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# CONFIG_STM32_PHYSR_100MBPS - This must be provided if CONFIG_STM32_AUTONEG is
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# defined. This provides the value of the speed bit(s) indicating 100MBps speed.
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# CONFIG_STM32_PHYSR_MODE - This must be provided if CONFIG_STM32_AUTONEG is
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# defined. This provide bit mask indicating full or half duplex modes.
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# CONFIG_STM32_PHYSR_FULLDUPLEX - This must be provided if CONFIG_STM32_AUTONEG is
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# defined. This provides the value of the mode bits indicating full duplex mode.
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# CONFIG_STM32_ETH_PTP - Precision Time Protocol (PTP). Not supported
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# but some hooks are indicated with this condition.
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#
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CONFIG_STM32_PHYADDR=0x01
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CONFIG_STM32_MII=y
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CONFIG_STM32_MII_MCO1=y
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CONFIG_STM32_MII_MCO2=n
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CONFIG_STM32_RMII=n
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CONFIG_STM32_AUTONEG=y
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#CONFIG_STM32_ETHFD
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#CONFIG_STM32_ETH100MB
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CONFIG_STM32_PHYSR=16
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CONFIG_STM32_PHYSR_SPEED=0x0002
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CONFIG_STM32_PHYSR_100MBPS=0x0000
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CONFIG_STM32_PHYSR_MODE=0x0004
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CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004
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CONFIG_STM32_ETH_PTP=n
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#
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# General build options
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@ -684,7 +713,7 @@ CONFIG_NET=n
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CONFIG_NET_IPv6=n
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CONFIG_NSOCKET_DESCRIPTORS=10
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CONFIG_NET_SOCKOPTS=y
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CONFIG_NET_BUFSIZE=420
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CONFIG_NET_BUFSIZE=562
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CONFIG_NET_TCP=y
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CONFIG_NET_TCP_CONNS=40
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CONFIG_NET_MAX_LISTENPORTS=40
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@ -258,15 +258,44 @@ CONFIG_SSI_POLLWAIT=y
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#
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# STM32F40xxx Ethernet device driver settings
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#
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# CONFIG_STM32_PHYADDR - The 5-bit address of the PHY on the board
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# CONFIG_STM32_MII - Support Ethernet MII interface
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# CONFIG_STM32_MII_MCO1 - Use MCO1 to clock the MII interface
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# CONFIG_STM32_MII_MCO2 - Use MCO2 to clock the MII interface
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# CONFIG_STM32_RMII - Support Ethernet RMII interface
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# CONFIG_STM32_AUTONEG - Use PHY autonegotion to determine speed and mode
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# CONFIG_STM32_ETHFD - If CONFIG_STM32_AUTONEG is not defined, then this
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# may be defined to select full duplex mode. Default: half-duplex
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# CONFIG_STM32_ETH100MBPS - If CONFIG_STM32_AUTONEG is not defined, then this
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# may be defined to select 100 MBps speed. Default: 10 Mbps
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# CONFIG_STM32_PHYSR - This must be provided if CONFIG_STM32_AUTONEG is
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# defined. The PHY status register address may diff from PHY to PHY. This
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# configuration sets the address of the PHY status register.
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# CONFIG_STM32_PHYSR_SPEED - This must be provided if CONFIG_STM32_AUTONEG is
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# defined. This provides bit mask indicating 10 or 100MBps speed.
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# CONFIG_STM32_PHYSR_100MBPS - This must be provided if CONFIG_STM32_AUTONEG is
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# defined. This provides the value of the speed bit(s) indicating 100MBps speed.
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# CONFIG_STM32_PHYSR_MODE - This must be provided if CONFIG_STM32_AUTONEG is
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# defined. This provide bit mask indicating full or half duplex modes.
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# CONFIG_STM32_PHYSR_FULLDUPLEX - This must be provided if CONFIG_STM32_AUTONEG is
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# defined. This provides the value of the mode bits indicating full duplex mode.
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# CONFIG_STM32_ETH_PTP - Precision Time Protocol (PTP). Not supported
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# but some hooks are indicated with this condition.
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#
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CONFIG_STM32_PHYADDR=0x01
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CONFIG_STM32_MII=y
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CONFIG_STM32_MII_MCO1=y
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CONFIG_STM32_MII_MCO2=n
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CONFIG_STM32_RMII=n
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CONFIG_STM32_AUTONEG=y
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#CONFIG_STM32_ETHFD
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#CONFIG_STM32_ETH100MBPS
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CONFIG_STM32_PHYSR=16
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CONFIG_STM32_PHYSR_SPEED=0x0002
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CONFIG_STM32_PHYSR_100MBPS=0x0000
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CONFIG_STM32_PHYSR_MODE=0x0004
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CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004
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CONFIG_STM32_ETH_PTP=n
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#
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# General build options
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@ -648,7 +677,7 @@ CONFIG_NET=n
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CONFIG_NET_IPv6=n
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CONFIG_NSOCKET_DESCRIPTORS=0
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CONFIG_NET_SOCKOPTS=y
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CONFIG_NET_BUFSIZE=420
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CONFIG_NET_BUFSIZE=562
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CONFIG_NET_TCP=n
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CONFIG_NET_TCP_CONNS=40
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CONFIG_NET_MAX_LISTENPORTS=40
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