Add register definitions for SAM4L BPM and SCIF blocks; SAM4L clock initialization now selects an optimal power scaling mode
This commit is contained in:
Gregory Nutt
parent
93b67f1598
commit
e352d4f3ad
@ -4910,4 +4910,7 @@
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logic (leveraged from AVR32).
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* nuttx/arch/arm/src/sam34/sam4l_periphclks.c/h: Add common
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logic to enabled/disable SAM4L peripheral clocking (2013-6-5).
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* nuttx/arch/arm/src/sam34/chip/sam4l_bpm.h and sam4l_scif.h: Add
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register definitions for the SAM4L BMP and SCIF blocks (2013-6-6).
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* nuttx/arch/arm/src/sam34/sam4l_clockconfig.c: New selects an
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optimal power scaling mode (2013-6-6).
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@ -333,6 +333,36 @@
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#define FLASH_CMD_HSEN 16 /* High Speed Mode Enable */
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#define FLASH_CMD_HSDIS 17 /* High Speed Mode Disable */
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/* Maximum CPU frequency for 0 and 1 FLASH wait states (FWS) in various modes
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* (Table 42-30 in the big data sheet).
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*
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* ------- ------------------- ---------- ----------
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* Power Flash Read Mode Flash Maximum
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* Sclaing Wait Operating
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* Mode HSEN HSDIS FASTWKUP States Frequency
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* ------- ---- ----- -------- ---------- ----------
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* PS0 X X 1 12MHz
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* " " X 0 18MHz
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* " " X 1 36MHz
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* PS1 X X 1 12MHz
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* " " X 0 8MHz
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* " " X 1 12MHz
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* PS2 X 0 24Mhz
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* " " X 1 48MHz
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* ------- ---- ----- -------- ---------- ----------
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*/
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#define FLASH_MAXFREQ_PS0_HSDIS_FASTWKUP_FWS1 (12000000ul)
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#define FLASH_MAXFREQ_PS0_HSDIS_FWS0 (18000000ul)
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#define FLASH_MAXFREQ_PS0_HSDIS_FWS1 (36000000ul)
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#define FLASH_MAXFREQ_PS1_HSDIS_FASTWKUP_FWS1 (12000000ul)
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#define FLASH_MAXFREQ_PS1_HSDIS_FWS0 (8000000ul)
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#define FLASH_MAXFREQ_PS1_HSDIS_FWS1 (12000000ul)
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#define FLASH_MAXFREQ_PS2_HSEN_FWS0 (24000000ul)
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#define FLASH_MAXFREQ_PS2_HSEN_FWS1 (48000000ul)
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/************************************************************************************
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* Public Types
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************************************************************************************/
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@ -55,6 +55,17 @@
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/****************************************************************************
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* Private Definitions
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****************************************************************************/
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/* Nominal frequencies in on-chip RC oscillators. These may frequencies
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* may vary with temperature changes.
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*/
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#define SAM_RCSYS_FREQUENCY 115000 /* Nominal frequency of RCSYS (Hz) */
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#define SAM_RC32K_FREQUENCY 32768 /* Nominal frequency of RC32K (Hz) */
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#define SAM_RC80M_FREQUENCY 80000000 /* Nominal frequency of RC80M (Hz) */
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#define SAM_RCFAST4M_FREQUENCY 4000000 /* Nominal frequency of RCFAST4M (Hz) */
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#define SAM_RCFAST8M_FREQUENCY 8000000 /* Nominal frequency of RCFAST8M (Hz) */
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#define SAM_RCFAST12M_FREQUENCY 12000000 /* Nominal frequency of RCFAST12M (Hz) */
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#define SAM_RC1M_FREQUENCY 1000000 /* Nominal frequency of RC1M (Hz) */
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#if defined(SAM_CLOCK_OSC0) || \
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(defined (SAM_CLOCK_PLL0) && defined(SAM_CLOCK_PLL0_OSC0)) || \
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@ -62,12 +73,6 @@
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# define NEED_OSC0
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#endif
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#if defined(SAM_CLOCK_OSC1) || \
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(defined (SAM_CLOCK_PLL0) && defined(SAM_CLOCK_PLL0_OSC1)) || \
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(defined (SAM_CLOCK_PLL1) && defined(SAM_CLOCK_PLL1_OSC1))
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# define NEED_OSC1
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#endif
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/****************************************************************************
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* Private Types
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****************************************************************************/
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@ -192,55 +197,6 @@ static inline void sam_enableosc0(void)
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}
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#endif
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/****************************************************************************
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* Name: sam_enableosc1
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*
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* Description:
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* Initialiaze OSC0 settings per the definitions in the board.h file.
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*
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****************************************************************************/
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#ifdef NEED_OSC1
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static inline void sam_enableosc1(void)
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{
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uint32_t regval;
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/* Enable OSC1 in the correct crystal mode by setting the mode value in OSCCTRL1 */
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regval = getreg32(SAM_PM_OSCCTRL1);
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regval &= ~PM_OSCCTRL_MODE_MASK;
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#if SAM_FOSC1 < 900000
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regval |= PM_OSCCTRL_MODE_XTALp9; /* Crystal XIN 0.4-0.9MHz */
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#elif SAM_FOSC1 < 3000000
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regval |= PM_OSCCTRL_MODE_XTAL3; /* Crystal XIN 0.9-3.0MHz */
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#elif SAM_FOSC1 < 8000000
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regval |= PM_OSCCTRL_MODE_XTAL8; /* Crystal XIN 3.0-8.0MHz */
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#else
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regval |= PM_OSCCTRL_MODE_XTALHI; /* Crystal XIN above 8.0MHz */
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#endif
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putreg32(regval, SAM_PM_OSCCTRL1);
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/* Enable OSC1 using the startup time provided in board.h. This startup time
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* is critical and depends on the characteristics of the crystal.
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*/
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regval = getreg32(SAM_PM_OSCCTRL1);
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regval &= ~PM_OSCCTRL_STARTUP_MASK;
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regval |= (SAM_OSC1STARTUP << PM_OSCCTRL_STARTUP_SHIFT);
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putreg32(regval, SAM_PM_OSCCTRL1);
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/* Enable OSC1 */
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regval = getreg32(SAM_PM_MCCTRL);
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regval |= PM_MCCTRL_OSC1EN;
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putreg32(regval, SAM_PM_MCCTRL);
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/* Wait for OSC1 to be ready */
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while ((getreg32(SAM_PM_POSCSR) & PM_POSCSR_OSC1RDY) == 0);
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}
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#endif
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/****************************************************************************
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* Name: sam_enablepll0
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*
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@ -505,17 +461,75 @@ static inline void sam_usbclock(void)
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void sam_clockconfig(void)
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{
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uint32_t regval;
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uint32_t bpmps;
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bool fastwkup;
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/* Enable clocking to the PICOCACHE */
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sam_picocache();
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/* Configure dividers derived clocks. These divider definitions must be
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* provided in the board.h header file.
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/* Configure dividers for derived clocks. These divider definitions must
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* be provided in the board.h header file.
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*/
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sam_setdividers(BOARD_SYSCLK_CPU_DIV, BOARD_SYSCLK_PBA_DIV,
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BOARD_SYSCLK_PBB_DIV, BOARD_SYSCLK_PBC_DIV,
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BOARD_SYSCLK_PBD_DIV);
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sam_setdividers(BOARD_CPU_SHIFT, BOARD_PBA_SHIFT, BOARD_PBB_SHIFT,
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BOARD_PBC_SHIFT, BOARD_PBD_SHIFT);
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/* Select a power scaling mode and possible fast wakeup so that we get the
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* best possible flash performance. The following table shows the maximum
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* CPU frequency for 0 and 1 FLASH wait states (FWS) in various modes
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* (Table 42-30 in the big data sheet).
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*
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* ------- ------------------- ---------- ----------
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* Power Flash Read Mode Flash Maximum
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* Sclaing Wait Operating
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* Mode HSEN HSDIS FASTWKUP States Frequency
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* ------- ---- ----- -------- ---------- ----------
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* PS0 X X 1 12MHz
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* " " X 0 18MHz
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* " " X 1 36MHz
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* PS1 X X 1 12MHz
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* " " X 0 8MHz
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* " " X 1 12MHz
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* PS2 X 0 24Mhz
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* " " X 1 48MHz
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* ------- ---- ----- -------- ---------- ----------
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*/
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#ifdef CONFIG_SAM_FLASH_HSEN
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/* The high speed FLASH mode has been enabled. Select power scaling mode 2 */
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bpmps = BPM_PMCON_PS2;
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fastwkup = false;
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#else
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/* Not high speed mode. Check if we can go to power scaling mode 1. */
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if (BOARD_CPU_FREQUENCY <= FLASH_MAXFREQ_PS1_HSDIS_FWS1)
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{
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/* Yes.. Do we also need to enable fast wakeup? */
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bpmps = BPM_PMCON_PS1;
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if (BOARD_CPU_FREQUENCY > FLASH_MAXFREQ_PS1_HSDIS_FWS0)
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{
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/* Yes.. enable fast wakeup */
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regval = getreg32(SAM_BPM_PMCON);
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regval |= BPM_PMCON_FASTWKUP;
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putreg32(BPM_UNLOCK_KEY(0xaa) | BPM_UNLOCK_ADDR(SAM_BPM_PMCON_OFFSET), SAM_BPM_UNLOCK);
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putreg32(regval, SAM_BPM_PMCON);
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/* We need to remember that we did this */
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fastwkup = true;
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}
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}
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else
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{
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bpmps = BPM_PMCON_PS0;
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}
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#endif
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#ifdef SAM_CLOCK_OSC32
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/* Enable the 32KHz oscillator (need by the RTC module) */
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@ -98,7 +98,7 @@
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static inline void up_enableosc32(void)
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{
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uint32_t regval;
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/* Select the 32KHz oscillator crystal */
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regval = getreg32(AVR32_PM_OSCCTRL32);
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@ -225,7 +225,7 @@ static inline void up_enableosc1(void)
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static inline void up_enablepll0(void)
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{
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/* Setup PLL0 */
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regval = (AVR32_PLL0_DIV << PM_PLL_PLLDIV_SHIFT) | (AVR32_PLL0_MUL << PM_PLL_PLLMUL_SHIFT) | (16 << PM_PLL_PLLCOUNT_SHIFT)
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/* Select PLL0/1 oscillator */
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@ -256,7 +256,7 @@ static inline void up_enablepll0(void)
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regval = getreg32(AVR32_PM_PLL0);
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regval |= PM_PLL_PLLEN;
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putreg32(regval, AVR32_PM_PLL0)
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/* Wait for PLL0 locked. */
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while ((getreg32(AVR32_PM_POSCSR) & PM_POSCSR_LOCK0) == 0);
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@ -275,11 +275,11 @@ static inline void up_enablepll0(void)
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static inline void up_enablepll1(void)
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{
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/* Setup PLL1 */
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regval = (AVR32_PLL1_DIV << PM_PLL_PLLDIV_SHIFT) | (AVR32_PLL1_MUL << PM_PLL_PLLMUL_SHIFT) | (16 << PM_PLL_PLLCOUNT_SHIFT)
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/* Select PLL0/1 oscillator */
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#if AVR32_CLOCK_PLL_OSC1
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regval |= PM_PLL_PLLOSC;
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#endif
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@ -363,7 +363,7 @@ static inline void up_clksel(void)
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static void up_fws(uint32_t cpuclock)
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{
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uint32_t regval;
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regval = getreg32(AVR32_FLASHC_FCR);
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if (cpuclock > AVR32_FLASHC_FWS0_MAXFREQ)
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{
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@ -387,7 +387,7 @@ static void up_fws(uint32_t cpuclock)
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static inline void up_mainclk(uint32_t mcsel)
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{
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uint32_t regval;
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regval = getreg32(AVR32_PM_MCCTRL);
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regval &= ~PM_MCCTRL_MCSEL_MASK;
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regval |= mcsel;
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@ -422,7 +422,7 @@ static inline void up_usbclock(void)
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putreg32(regval, AVR32_PM_GCCTRL(AVR32_PM_GCLK_USBB))
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/* Enable USB GCLK */
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regval = getreg32(AVR32_PM_GCCTRL(AVR32_PM_GCLK_USBB))
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regval |= PM_GCCTRL_CEN;
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putreg32(regval, AVR32_PM_GCCTRL(AVR32_PM_GCLK_USBB))
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@ -441,7 +441,7 @@ static inline void up_usbclock(void)
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* file.
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*
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**************************************************************************/
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void up_clkinitialize(void)
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{
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#ifdef AVR32_CLOCK_OSC32
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@ -458,7 +458,7 @@ void up_clkinitialize(void)
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/* Set up FLASH wait states */
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up_fws(AVR32_FOSC0);
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/* Then switch the main clock to OSC0 */
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up_mainclk(PM_MCCTRL_MCSEL_OSC0);
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@ -474,11 +474,11 @@ void up_clkinitialize(void)
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/* Enable PLL0 using the settings in board.h */
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up_enablepll0();
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/* Set up FLASH wait states */
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up_fws(AVR32_CPU_CLOCK);
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/* Then switch the main clock to PLL0 */
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up_mainclk(PM_MCCTRL_MCSEL_PLL0);
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@ -54,66 +54,73 @@
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************************************************************************************/
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/* Clocking *************************************************************************/
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/* After power-on reset, the sam3u device is running on a 4MHz internal RC. These
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* definitions will configure clocking with MCK = 48MHz, PLLA = 96, and CPU=48MHz.
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/* Select the DFLL as the source of the system clock.
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*
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* Options (define one):
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* BOARD_SYSCLK_SOURCE_RCSYS - System RC oscillator
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* BOARD_SYSCLK_SOURCE_OSC0 - Oscillator 0
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* BOARD_SYSCLK_SOURCE_PLL0 - Phase Locked Loop 0
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* BOARD_SYSCLK_SOURCE_DFLL0 - Digital Frequency Locked Loop
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* BOARD_SYSCLK_SOURCE_RC80M - 80 MHz RC oscillator
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* BOARD_SYSCLK_SOURCE_FCFAST12M - 12 MHz RC oscillator
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* BOARD_SYSCLK_SOURCE_FCFAST8M - 8 MHz RC oscillator
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* BOARD_SYSCLK_SOURCE_FCFAST4M - 4 MHz RC oscillator
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* BOARD_SYSCLK_SOURCE_RC1M - 1 MHz RC oscillator
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*/
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/* Main oscillator register settings */
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#define BOARD_SYSCLK_SOURCE_DFLL0 1
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#define BOARD_CKGR_MOR_MOSCXTST (63 << CKGR_MOR_MOSCXTST_SHIFT) /* Start-up Time */
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/* Nominal frequencies in on-chip RC oscillators. These are *not* configurable
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* but appear here for use in frequency calculations. NOTE: These may frequencies
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* may vary with temperature changes.
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*/
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/* PLLA configuration */
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#define BOARD_RCSYS_FREQUENCY 115000 /* Nominal frequency of RCSYS (Hz) */
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#define BOARD_RC32K_FREQUENCY 32768 /* Nominal frequency of RC32K (Hz) */
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#define BOARD_RC80M_FREQUENCY 80000000 /* Nominal frequency of RC80M (Hz) */
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#define BOARD_RCFAST4M_FREQUENCY 4000000 /* Nominal frequency of RCFAST4M (Hz) */
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#define BOARD_RCFAST8M_FREQUENCY 8000000 /* Nominal frequency of RCFAST8M (Hz) */
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#define BOARD_RCFAST12M_FREQUENCY 12000000 /* Nominal frequency of RCFAST12M (Hz) */
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#define BOARD_RC1M_FREQUENCY 1000000 /* Nominal frequency of RC1M (Hz) */
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#define BOARD_CKGR_PLLAR_MULA (7 << CKGR_PLLAR_MULA_SHIFT)
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#define BOARD_CKGR_PLLAR_STMODE CKGR_PLLAR_STMODE_FAST
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#define BOARD_CKGR_PLLAR_PLLACOUNT (63 << CKGR_PLLAR_PLLACOUNT_SHIFT)
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#define BOARD_CKGR_PLLAR_DIVA CKGR_PLLAR_DIVA_BYPASS
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/* On-board crystal frequencies */
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/* PMC master clock register settings */
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#define BOARD_OSC32_FREQUENCY 32768
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#define BOARD_PMC_MCKR_CSS PMC_MCKR_CSS_PLLA
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#define BOARD_PMC_MCKR_PRES PMC_MCKR_PRES_DIV2
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/* Digital Frequency Locked Loop configuration
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* Fdfll = (Fclk * DFLLmul) / DFLLdiv
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* = 32768 * (48000000/32760) / 1 = 48MHz
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*
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* DFLL0 source options (select one):
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* BOARD_DFLL0_SOURCE_RCSYS - System RC oscillator
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* BOARD_DFLL0_SOURCE_OSC32K - 32.768KHz oscillator
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* BOARD_DFLL0_SOURCE_OSC0 - Oscillator 0
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* BOARD_DFLL0_SOURCE_RC80M - 80 MHz RC oscillator
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* BOARD_DFLL0_SOURCE_RC32K - 32 kHz RC oscillator
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*/
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/* USB UTMI PLL start-up time */
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#define BOARD_DFLL0_SOURCE_OSC32K 1
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#define BOARD_FDLL0_FREQUENCY 48000000
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#define BOARD_FDLL0_MUL (BOARD_FDLL0_FREQUENCY / BOARD_OSC32_FREQUENCY)
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#define BOARD_FDLL0_DIV 1
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#define BOARD_CKGR_UCKR_UPLLCOUNT (3 << CKGR_UCKR_UPLLCOUNT_SHIFT)
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/* System clock dividers: Fbus = Fsys >> BUSshift */
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/* System clock dividers: Fbus = Fsys / (2 ^ BUS_div) */
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#define BOARD_SYSCLK_CPU_DIV 0
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#define BOARD_SYSCLK_PBA_DIV 0
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#define BOARD_SYSCLK_PBB_DIV 0
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#define BOARD_SYSCLK_PBC_DIV 0
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#define BOARD_SYSCLK_PBD_DIV 0
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#define BOARD_CPU_SHIFT 0 /* Fcpu = Fsys = 48MHz */
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#define BOARD_PBA_SHIFT 0 /* Fpba = Fsys = 48MHz */
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#define BOARD_PBB_SHIFT 0 /* Fpbb = Fsys = 48MHz */
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#define BOARD_PBC_SHIFT 0 /* Fpbc = Fsys = 48MHz */
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#define BOARD_PBD_SHIFT 0 /* Fpbd = Fsys = 48MHz */
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/* Resulting frequencies */
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#define SAM_MAINOSC_FREQUENCY (12000000)
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#define SAM_MCK_FREQUENCY (48000000)
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#define SAM_PLLA_FREQUENCY (96000000)
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#define SAM_CPU_FREQUENCY (48000000)
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/* HSMCI clocking
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*
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* Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK)
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* divided by (2*(CLKDIV+1)).
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*
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* MCI_SPEED = MCK / (2*(CLKDIV+1))
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* CLKDIV = MCI / MCI_SPEED / 2 - 1
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*/
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/* MCK = 48MHz, CLKDIV = 59, MCI_SPEED = 48MHz / 2 * (59+1) = 400 KHz */
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#define HSMCI_INIT_CLKDIV (59 << HSMCI_MR_CLKDIV_SHIFT)
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/* MCK = 48MHz, CLKDIV = 1, MCI_SPEED = 48MHz / 2 * (1+1) = 12 MHz */
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#define HSMCI_MMCXFR_CLKDIV (3 << HSMCI_MR_CLKDIV_SHIFT)
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|
||||
/* MCK = 48MHz, CLKDIV = 0, MCI_SPEED = 48MHz / 2 * (0+1) = 24 MHz */
|
||||
|
||||
#define HSMCI_SDXFR_CLKDIV (0 << HSMCI_MR_CLKDIV_SHIFT)
|
||||
#define HSMCI_SDWIDEXFR_CLKDIV HSMCI_SDXFR_CLKDIV
|
||||
#define BOARD_MAIN_FREQUENCY (12000000)
|
||||
#define BOARD_CPU_FREQUENCY (BOARD_MAIN_FREQUENCY >> BOARD_CPU_SHIFT)
|
||||
#define BOARD_PBA_FREQUENCY (BOARD_MAIN_FREQUENCY >> BOARD_PBA_SHIFT)
|
||||
#define BOARD_PBB_FREQUENCY (BOARD_MAIN_FREQUENCY >> BOARD_PBB_SHIFT)
|
||||
#define BOARD_PBC_FREQUENCY (BOARD_MAIN_FREQUENCY >> BOARD_PBC_SHIFT)
|
||||
#define BOARD_PBD_FREQUENCY (BOARD_MAIN_FREQUENCY >> BOARD_PBD_SHIFT)
|
||||
|
||||
/* LED definitions ******************************************************************/
|
||||
/* There are three LEDs on board the SAM4L Xplained Pro board: The EDBG
|
||||
|
||||
Loading…
Reference in New Issue
Block a user