arch/arm/src/stm32l4: add initial support for STM32L412 and STM32L422 chips
This commit is contained in:
Juha Niskanen
Gregory Nutt
parent
8193c28e91
commit
e37f260d67
@ -93,12 +93,12 @@
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defined(CONFIG_STM32L4_STM32L462XX)
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# define STM32L4_SRAM1_SIZE (128*1024) /* 128Kb SRAM1 on AHB bus Matrix */
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# define STM32L4_SRAM2_SIZE (32*1024) /* 32Kb SRAM2 on AHB bus Matrix */
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#elif defined(CONFIG_STM32L4_STM32L432XX)
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# define STM32L4_SRAM1_SIZE (48*1024) /* 48Kb SRAM1 on AHB bus Matrix */
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# define STM32L4_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */
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#elif defined(CONFIG_STM32L4_STM32L433XX)
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#elif defined(CONFIG_STM32L4_STM32L432XX) || defined(CONFIG_STM32L4_STM32L433XX)
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# define STM32L4_SRAM1_SIZE (48*1024) /* 48Kb SRAM1 on AHB bus Matrix */
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# define STM32L4_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */
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#elif defined(CONFIG_STM32L4_STM32L412XX) || defined(CONFIG_STM32L4_STM32L422XX)
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# define STM32L4_SRAM1_SIZE (32*1024) /* 32Kb SRAM1 on AHB bus Matrix */
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# define STM32L4_SRAM2_SIZE (8*1024) /* 8Kb SRAM2 on AHB bus Matrix */
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#else
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# error "Unsupported STM32L4 chip"
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#endif
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@ -303,7 +303,37 @@
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# define STM32L4_NCRC 1 /* CRC */
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# define STM32L4_NCOMP 2 /* Comparators */
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# define STM32L4_NOPAMP 1 /* Operational Amplifiers */
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#endif /* CONFIG_STM32L4_STM32L432XX */
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#endif /* CONFIG_STM32L4_STM32L433XX */
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#if defined(CONFIG_STM32L4_STM32L412XX) || defined(CONFIG_STM32L4_STM32L422XX)
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# define STM32L4_NFSMC 0 /* No FSMC memory controller */
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# define STM32L4_NATIM 1 /* One advanced timer TIM1 */
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# define STM32L4_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */
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# define STM32L4_NGTIM16 2 /* 16-bit general timers TIM15-16 with DMA */
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# define STM32L4_NGTIMNDMA 0 /* No 16-bit general timers without DMA */
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# define STM32L4_NBTIM 1 /* One basic timer, TIM6 */
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# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */
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# define STM32L4_NRNG 1 /* Random number generator (RNG) */
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# define STM32L4_NUART 0 /* No UART */
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# define STM32L4_NUSART 3 /* USART 1-3 */
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# define STM32L4_NLPUART 1 /* LPUART 1 */
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# define STM32L4_QSPI 1 /* QuadSPI1 */
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# define STM32L4_NSPI 3 /* SPI1-SPI3 */
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# define STM32L4_NI2C 3 /* I2C1-I2C3 */
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# define STM32L4_NSWPMI 0 /* No SWPMI */
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# define STM32L4_NUSBOTGFS 0 /* No USB OTG FS */
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# define STM32L4_NUSBFS 1 /* USB FS */
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# define STM32L4_NCAN 0 /* No CAN */
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# define STM32L4_NSAI 0 /* No SAI */
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# define STM32L4_NSDMMC 0 /* No SDMMC interface */
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# define STM32L4_NDMA 2 /* DMA1-2 */
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# define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */
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# define STM32L4_NADC 2 /* 12-bit ADC1-2, 10 channels */
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# define STM32L4_NDAC 0 /* No DAC */
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# define STM32L4_NCRC 1 /* CRC */
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# define STM32L4_NCOMP 2 /* Comparators */
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# define STM32L4_NOPAMP 1 /* Operational Amplifiers */
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#endif /* CONFIG_STM32L4_STM32L412XX || CONFIG_STM32L4_STM32L422XX */
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/* NVIC priority levels *************************************************************/
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/* 16 Programmable interrupt levels */
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@ -12,6 +12,14 @@ choice
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default ARCH_CHIP_STM32L476RG
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depends on ARCH_CHIP_STM32L4
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config ARCH_CHIP_STM32L412KB
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bool "STM32L412KB"
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select STM32L4_STM32L412XX
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select STM32L4_FLASH_CONFIG_B
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select STM32L4_IO_CONFIG_K
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---help---
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STM32 L4 Cortex M4, 128 Kb FLASH, 40 Kb SRAM
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config ARCH_CHIP_STM32L432KB
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bool "STM32L432KB"
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select STM32L4_STM32L432XX
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@ -558,6 +566,19 @@ config STM32L4_STM32L4XR
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# Chip subfamilies:
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config STM32L4_STM32L412XX
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bool
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default n
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select STM32L4_STM32L4X2
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select STM32L4_HAVE_ADC2
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config STM32L4_STM32L422XX
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bool
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default n
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select STM32L4_STM32L4X2
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select STM32L4_HAVE_ADC2
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select STM32L4_HAVE_AES
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config STM32L4_STM32L431XX
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bool
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default n
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@ -717,6 +738,7 @@ choice
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that designates the FLASH size.
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Designator Size in KiB
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8 64
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B 128
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C 256
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E 512
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@ -738,6 +760,9 @@ choice
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config STM32L4_FLASH_OVERRIDE_DEFAULT
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bool "Default"
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config STM32L4_FLASH_OVERRIDE_8
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bool "8 64 KB"
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config STM32L4_FLASH_OVERRIDE_B
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bool "B 128 KB"
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@ -757,6 +782,11 @@ endchoice # "Override Flash Size Designator"
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# Flash configurations
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config STM32L4_FLASH_CONFIG_8
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bool
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default n
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depends on STM32L4_STM32L412XX
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config STM32L4_FLASH_CONFIG_B
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bool
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default n
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@ -787,6 +817,10 @@ config STM32L4_IO_CONFIG_K
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bool
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default n
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config STM32L4_IO_CONFIG_T
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bool
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default n
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config STM32L4_IO_CONFIG_C
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bool
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default n
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@ -63,11 +63,13 @@
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#define _K(x) ((x)*1024)
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#if !defined(CONFIG_STM32L4_FLASH_OVERRIDE_DEFAULT) && \
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!defined(CONFIG_STM32L4_FLASH_OVERRIDE_8) && \
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!defined(CONFIG_STM32L4_FLASH_OVERRIDE_B) && \
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!defined(CONFIG_STM32L4_FLASH_OVERRIDE_C) && \
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!defined(CONFIG_STM32L4_FLASH_OVERRIDE_E) && \
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!defined(CONFIG_STM32L4_FLASH_OVERRIDE_G) && \
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!defined(CONFIG_STM32L4_FLASH_OVERRIDE_I) && \
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!defined(CONFIG_STM32L4_FLASH_CONFIG_8) && \
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!defined(CONFIG_STM32L4_FLASH_CONFIG_B) && \
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!defined(CONFIG_STM32L4_FLASH_CONFIG_C) && \
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!defined(CONFIG_STM32L4_FLASH_CONFIG_E) && \
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@ -80,12 +82,15 @@
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/* Override of the Flash has been chosen */
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#if !defined(CONFIG_STM32L4_FLASH_OVERRIDE_DEFAULT)
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# undef CONFIG_STM32L4_FLASH_CONFIG_8
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# undef CONFIG_STM32L4_FLASH_CONFIG_B
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# undef CONFIG_STM32L4_FLASH_CONFIG_C
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# undef CONFIG_STM32L4_FLASH_CONFIG_E
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# undef CONFIG_STM32L4_FLASH_CONFIG_G
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# undef CONFIG_STM32L4_FLASH_CONFIG_I
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# if defined(CONFIG_STM32L4_FLASH_OVERRIDE_B)
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# if defined(CONFIG_STM32L4_FLASH_OVERRIDE_8)
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# define CONFIG_STM32L4_FLASH_CONFIG_8
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# elif defined(CONFIG_STM32L4_FLASH_OVERRIDE_B)
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# define CONFIG_STM32L4_FLASH_CONFIG_B
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# elif defined(CONFIG_STM32L4_FLASH_OVERRIDE_C)
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# define CONFIG_STM32L4_FLASH_CONFIG_C
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@ -100,7 +105,10 @@
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/* Define the valid configuration */
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#if defined(CONFIG_STM32L4_FLASH_CONFIG_B) /* 128 kB */
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#if defined(CONFIG_STM32L4_FLASH_CONFIG_8) /* 64 kB */
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# define STM32L4_FLASH_NPAGES 32
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# define STM32L4_FLASH_PAGESIZE 2048
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#elif defined(CONFIG_STM32L4_FLASH_CONFIG_B) /* 128 kB */
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# define STM32L4_FLASH_NPAGES 64
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# define STM32L4_FLASH_PAGESIZE 2048
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#elif defined(CONFIG_STM32L4_FLASH_CONFIG_C) /* 256 kB */
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@ -365,7 +365,7 @@ void up_addregion(void)
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up_heap_color((FAR void *)SRAM3_START, SRAM3_END-SRAM3_START);
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/* Add the SRAM2 user heap region. */
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/* Add the SRAM3 user heap region. */
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kumm_addregion((FAR void *)SRAM3_START, SRAM3_END-SRAM3_START);
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