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risc-v: Replace all inline assembly with macro

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Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
This commit is contained in:
Huang Qi 2022-03-03 16:47:01 +08:00 committed by Xiang Xiao
parent 35330a798b
commit e383439dda
9 changed files with 60 additions and 80 deletions
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19
arch/risc-v/src/bl602/bl602_irq.c
View File

@ -33,6 +33,7 @@
#include <nuttx/board.h>
#include <arch/irq.h>
#include <arch/board/board.h>
#include <arch/csr.h>
#include "riscv_internal.h"
#include "riscv_arch.h"
@ -112,13 +113,11 @@ void up_irqinitialize(void)
void up_disable_irq(int irq)
{
uint32_t oldstat;
if (irq == RISCV_IRQ_MSOFT)
{
/* Read mstatus & clear machine software interrupt enable in mie */
asm volatile("csrrc %0, mie, %1" : "=r"(oldstat) : "r"(MIE_MSIE));
CLEAR_CSR(mie, MIE_MSIE);
}
else if (irq == RISCV_IRQ_MTIMER)
{
@ -126,7 +125,7 @@ void up_disable_irq(int irq)
/* Read mstatus & clear machine timer interrupt enable in mie */
asm volatile("csrrc %0, mie, %1" : "=r"(oldstat) : "r"(MIE_MTIE));
CLEAR_CSR(mie, MIE_MTIE);
}
else
{
@ -145,13 +144,11 @@ void up_disable_irq(int irq)
void up_enable_irq(int irq)
{
uint32_t oldstat;
if (irq == RISCV_IRQ_MSOFT)
{
/* Read mstatus & set machine software interrupt enable in mie */
asm volatile("csrrs %0, mie, %1" : "=r"(oldstat) : "r"(MIE_MSIE));
SET_CSR(mie, MIE_MSIE);
}
else if (irq == RISCV_IRQ_MTIMER)
{
@ -159,9 +156,7 @@ void up_enable_irq(int irq)
/* Read mstatus & set machine timer interrupt enable in mie */
asm volatile("csrrs %0, mie, %1"
: "=r"(oldstat)
: "r"(MIE_MTIE | 0x1 << 11));
SET_CSR(mie, MIE_MTIE | 0x1 << 11);
}
else
{
@ -217,10 +212,10 @@ irqstate_t up_irq_enable(void)
/* Enable MEIE (machine external interrupt enable) */
asm volatile("csrrs %0, mie, %1" : "=r"(oldstat) : "r"(MIE_MEIE));
SET_CSR(mie, MIE_MEIE);
/* Read mstatus & set machine interrupt enable (MIE) in mstatus */
asm volatile("csrrs %0, mstatus, %1" : "=r"(oldstat) : "r"(MSTATUS_MIE));
oldstat = READ_AND_SET_CSR(mstatus, MSTATUS_MIE);
return oldstat;
}

17
arch/risc-v/src/c906/c906_irq.c
View File

@ -34,6 +34,7 @@
#include "riscv_internal.h"
#include "riscv_arch.h"
#include <arch/csr.h>
#include "c906.h"
@ -122,19 +123,18 @@ void up_irqinitialize(void)
void up_disable_irq(int irq)
{
int extirq = 0;
uint64_t oldstat = 0;
if (irq == RISCV_IRQ_MSOFT)
{
/* Read mstatus & clear machine software interrupt enable in mie */
asm volatile ("csrrc %0, mie, %1": "=r" (oldstat) : "r"(MIE_MSIE));
CLEAR_CSR(mie, MIE_MSIE);
}
else if (irq == RISCV_IRQ_MTIMER)
{
/* Read mstatus & clear machine timer interrupt enable in mie */
asm volatile ("csrrc %0, mie, %1": "=r" (oldstat) : "r"(MIE_MTIE));
CLEAR_CSR(mie, MIE_MTIE);
}
else if (irq >= C906_IRQ_PERI_START)
{
@ -165,19 +165,18 @@ void up_disable_irq(int irq)
void up_enable_irq(int irq)
{
int extirq;
uint64_t oldstat;
if (irq == RISCV_IRQ_MSOFT)
{
/* Read mstatus & set machine software interrupt enable in mie */
asm volatile ("csrrs %0, mie, %1": "=r" (oldstat) : "r"(MIE_MSIE));
SET_CSR(mie, MIE_MSIE);
}
else if (irq == RISCV_IRQ_MTIMER)
{
/* Read mstatus & set machine timer interrupt enable in mie */
asm volatile ("csrrs %0, mie, %1": "=r" (oldstat) : "r"(MIE_MTIE));
SET_CSR(mie, MIE_MTIE);
}
else if (irq >= C906_IRQ_PERI_START)
{
@ -244,16 +243,16 @@ void riscv_ack_irq(int irq)
irqstate_t up_irq_enable(void)
{
uint64_t oldstat;
irqstate_t oldstat;
/* Enable MEIE (machine external interrupt enable) */
/* TODO: should move to up_enable_irq() */
asm volatile ("csrrs %0, mie, %1": "=r" (oldstat) : "r"(MIE_MEIE));
SET_CSR(mie, MIE_MEIE);
/* Read mstatus & set machine interrupt enable (MIE) in mstatus */
asm volatile ("csrrs %0, mstatus, %1": "=r" (oldstat) : "r"(MSTATUS_MIE));
oldstat = READ_AND_SET_CSR(mstatus, MSTATUS_MIE);
return oldstat;
}

12
arch/risc-v/src/esp32c3/esp32c3_irq.c
View File

@ -34,6 +34,7 @@
#include <arch/board/board.h>
#include <arch/irq.h>
#include <arch/csr.h>
#include "riscv_internal.h"
#include "hardware/esp32c3_interrupt.h"
@ -461,17 +462,10 @@ IRAM_ATTR uintptr_t *esp32c3_dispatch_irq(uintptr_t mcause, uintptr_t *regs)
irqstate_t up_irq_enable(void)
{
uint32_t flags;
irqstate_t flags;
/* Read mstatus & set machine interrupt enable (MIE) in mstatus */
__asm__ __volatile__
(
"csrrs %0, mstatus, %1\n"
: "=r" (flags)
: "r"(MSTATUS_MIE)
: "memory"
);
flags = READ_AND_SET_CSR(mstatus, MSTATUS_MIE);
return flags;
}

13
arch/risc-v/src/fe310/fe310_irq.c
View File

@ -33,6 +33,7 @@
#include <nuttx/board.h>
#include <arch/irq.h>
#include <arch/board/board.h>
#include <arch/csr.h>
#include "riscv_internal.h"
#include "riscv_arch.h"
@ -105,13 +106,12 @@ void up_irqinitialize(void)
void up_disable_irq(int irq)
{
int extirq;
uint32_t oldstat;
if (irq == RISCV_IRQ_MTIMER)
{
/* Read mstatus & clear machine timer interrupt enable in mie */
asm volatile ("csrrc %0, mie, %1": "=r" (oldstat) : "r"(MIE_MTIE));
CLEAR_CSR(mie, MIE_MTIE);
}
else if (irq > RISCV_IRQ_MEXT)
{
@ -142,13 +142,12 @@ void up_disable_irq(int irq)
void up_enable_irq(int irq)
{
int extirq;
uint32_t oldstat;
if (irq == RISCV_IRQ_MTIMER)
{
/* Read mstatus & set machine timer interrupt enable in mie */
asm volatile ("csrrs %0, mie, %1": "=r" (oldstat) : "r"(MIE_MTIE));
SET_CSR(mie, MIE_MTIE);
}
else if (irq > RISCV_IRQ_MEXT)
{
@ -208,18 +207,18 @@ void riscv_ack_irq(int irq)
irqstate_t up_irq_enable(void)
{
uint32_t oldstat;
irqstate_t oldstat;
#if 1
/* Enable MEIE (machine external interrupt enable) */
/* TODO: should move to up_enable_irq() */
asm volatile ("csrrs %0, mie, %1": "=r" (oldstat) : "r"(MIE_MEIE));
SET_CSR(mie, MIE_MEIE);
#endif
/* Read mstatus & set machine interrupt enable (MIE) in mstatus */
asm volatile ("csrrs %0, mstatus, %1": "=r" (oldstat) : "r"(MSTATUS_MIE));
oldstat = READ_AND_SET_CSR(mstatus, MSTATUS_MIE);
return oldstat;
}

17
arch/risc-v/src/k210/k210_irq.c
View File

@ -31,6 +31,7 @@
#include <nuttx/arch.h>
#include <arch/irq.h>
#include <arch/csr.h>
#include "riscv_internal.h"
#include "riscv_arch.h"
@ -138,19 +139,18 @@ void up_irqinitialize(void)
void up_disable_irq(int irq)
{
int extirq;
uint64_t oldstat;
if (irq == RISCV_IRQ_MSOFT)
{
/* Read mstatus & clear machine software interrupt enable in mie */
asm volatile ("csrrc %0, mie, %1": "=r" (oldstat) : "r"(MIE_MSIE));
CLEAR_CSR(mie, MIE_MSIE);
}
else if (irq == RISCV_IRQ_MTIMER)
{
/* Read mstatus & clear machine timer interrupt enable in mie */
asm volatile ("csrrc %0, mie, %1": "=r" (oldstat) : "r"(MIE_MTIE));
CLEAR_CSR(mie, MIE_MTIE);
}
else if (irq > RISCV_IRQ_MEXT)
{
@ -181,19 +181,18 @@ void up_disable_irq(int irq)
void up_enable_irq(int irq)
{
int extirq;
uint64_t oldstat;
if (irq == RISCV_IRQ_MSOFT)
{
/* Read mstatus & set machine software interrupt enable in mie */
asm volatile ("csrrs %0, mie, %1": "=r" (oldstat) : "r"(MIE_MSIE));
SET_CSR(mie, MIE_MSIE);
}
else if (irq == RISCV_IRQ_MTIMER)
{
/* Read mstatus & set machine timer interrupt enable in mie */
asm volatile ("csrrs %0, mie, %1": "=r" (oldstat) : "r"(MIE_MTIE));
SET_CSR(mie, MIE_MTIE);
}
else if (irq > RISCV_IRQ_MEXT)
{
@ -256,18 +255,18 @@ void riscv_ack_irq(int irq)
irqstate_t up_irq_enable(void)
{
uint64_t oldstat;
irqstate_t oldstat;
#if 1
/* Enable MEIE (machine external interrupt enable) */
/* TODO: should move to up_enable_irq() */
asm volatile ("csrrs %0, mie, %1": "=r" (oldstat) : "r"(MIE_MEIE));
SET_CSR(mie, MIE_MEIE);
#endif
/* Read mstatus & set machine interrupt enable (MIE) in mstatus */
asm volatile ("csrrs %0, mstatus, %1": "=r" (oldstat) : "r"(MSTATUS_MIE));
oldstat = READ_AND_SET_CSR(mstatus, MSTATUS_MIE);
return oldstat;
}

17
arch/risc-v/src/litex/litex_irq.c
View File

@ -33,6 +33,7 @@
#include <nuttx/board.h>
#include <arch/irq.h>
#include <arch/board/board.h>
#include <arch/csr.h>
#include "riscv_internal.h"
#include "riscv_arch.h"
@ -94,19 +95,18 @@ void up_disable_irq(int irq)
{
int extirq;
int mask;
uint32_t oldstat;
if (irq == RISCV_IRQ_MSOFT)
{
/* Read mstatus & clear machine software interrupt enable in mie */
asm volatile ("csrrc %0, mie, %1": "=r" (oldstat) : "r"(MIE_MSIE));
CLEAR_CSR(mie, MIE_MSIE);
}
else if (irq == RISCV_IRQ_MTIMER)
{
/* Read mstatus & clear machine timer interrupt enable in mie */
asm volatile ("csrrc %0, mie, %1": "=r" (oldstat) : "r"(MIE_MTIE));
CLEAR_CSR(mie, MIE_MTIE);
}
else if (irq > RISCV_IRQ_MEXT)
{
@ -140,19 +140,18 @@ void up_enable_irq(int irq)
{
int extirq;
int mask;
uint32_t oldstat;
if (irq == RISCV_IRQ_MSOFT)
{
/* Read mstatus & set machine software interrupt enable in mie */
asm volatile ("csrrs %0, mie, %1": "=r" (oldstat) : "r"(MIE_MSIE));
SET_CSR(mie, MIE_MSIE);
}
else if (irq == RISCV_IRQ_MTIMER)
{
/* Read mstatus & set machine timer interrupt enable in mie */
asm volatile ("csrrs %0, mie, %1": "=r" (oldstat) : "r"(MIE_MTIE));
SET_CSR(mie, MIE_MTIE);
}
else if (irq > RISCV_IRQ_MEXT)
{
@ -213,18 +212,18 @@ void riscv_ack_irq(int irq)
irqstate_t up_irq_enable(void)
{
uint32_t oldstat;
irqstate_t oldstat;
#if 1
/* Enable MEIE (machine external interrupt enable) */
/* TODO: should move to up_enable_irq() */
asm volatile ("csrrs %0, mie, %1": "=r" (oldstat) : "r"(MIE_MEIE));
SET_CSR(mie, MIE_MEIE);
#endif
/* Read mstatus & set machine interrupt enable (MIE) in mstatus */
asm volatile ("csrrs %0, mstatus, %1": "=r" (oldstat) : "r"(MSTATUS_MIE));
oldstat = READ_AND_SET_CSR(mstatus, MSTATUS_MIE);
return oldstat;
}

17
arch/risc-v/src/mpfs/mpfs_irq.c
View File

@ -31,6 +31,7 @@
#include <nuttx/arch.h>
#include <arch/irq.h>
#include <arch/csr.h>
#include "riscv_internal.h"
#include "riscv_arch.h"
@ -166,19 +167,18 @@ void up_irqinitialize(void)
void up_disable_irq(int irq)
{
int extirq = 0;
uint64_t oldstat = 0;
if (irq == RISCV_IRQ_MSOFT)
{
/* Read mstatus & clear machine software interrupt enable in mie */
asm volatile ("csrrc %0, mie, %1": "=r" (oldstat) : "r"(MIE_MSIE));
CLEAR_CSR(mie, MIE_MSIE);
}
else if (irq == RISCV_IRQ_MTIMER)
{
/* Read mstatus & clear machine timer interrupt enable in mie */
asm volatile ("csrrc %0, mie, %1": "=r" (oldstat) : "r"(MIE_MTIE));
CLEAR_CSR(mie, MIE_MTIE);
}
else if (irq >= MPFS_IRQ_EXT_START)
{
@ -221,19 +221,18 @@ void up_disable_irq(int irq)
void up_enable_irq(int irq)
{
int extirq;
uint64_t oldstat;
if (irq == RISCV_IRQ_MSOFT)
{
/* Read mstatus & set machine software interrupt enable in mie */
asm volatile ("csrrs %0, mie, %1": "=r" (oldstat) : "r"(MIE_MSIE));
SET_CSR(mie, MIE_MSIE);
}
else if (irq == RISCV_IRQ_MTIMER)
{
/* Read mstatus & set machine timer interrupt enable in mie */
asm volatile ("csrrs %0, mie, %1": "=r" (oldstat) : "r"(MIE_MTIE));
SET_CSR(mie, MIE_MTIE);
}
else if (irq >= MPFS_IRQ_EXT_START)
{
@ -312,14 +311,14 @@ void riscv_ack_irq(int irq)
irqstate_t up_irq_enable(void)
{
uint64_t oldstat;
irqstate_t oldstat;
/* Enable MEIE (machine external interrupt enable) */
asm volatile ("csrrs %0, mie, %1": "=r" (oldstat) : "r"(MIE_MEIE));
SET_CSR(mie, MIE_MEIE);
/* Read mstatus & set machine interrupt enable (MIE) in mstatus */
asm volatile ("csrrs %0, mstatus, %1": "=r" (oldstat) : "r"(MSTATUS_MIE));
oldstat = READ_AND_SET_CSR(mstatus, MSTATUS_MIE);
return oldstat;
}

21
arch/risc-v/src/qemu-rv/qemu_rv_irq.c
View File

@ -33,6 +33,7 @@
#include <nuttx/board.h>
#include <arch/irq.h>
#include <arch/board/board.h>
#include <arch/csr.h>
#include "riscv_internal.h"
#include "riscv_arch.h"
@ -116,21 +117,18 @@ void up_irqinitialize(void)
void up_disable_irq(int irq)
{
int extirq;
uint32_t oldstat;
if (irq == RISCV_IRQ_MSOFT)
{
/* Read mstatus & clear machine software interrupt enable in mie */
asm volatile ("csrrc %0, mie, %1": "=r" (oldstat) : "r"(MIE_MSIE));
CLEAR_CSR(mie, MIE_MSIE);
}
else if (irq == RISCV_IRQ_MTIMER)
{
/* Read mstatus & clear machine timer interrupt enable in mie */
asm volatile("csrrc %0, mie, %1"
: "=r"(oldstat)
: "r"(MIE_MTIE));
CLEAR_CSR(mie, MIE_MTIE);
}
else if (irq > RISCV_IRQ_MEXT)
{
@ -161,21 +159,18 @@ void up_disable_irq(int irq)
void up_enable_irq(int irq)
{
int extirq;
uint32_t oldstat;
if (irq == RISCV_IRQ_MSOFT)
{
/* Read mstatus & set machine software interrupt enable in mie */
asm volatile ("csrrs %0, mie, %1": "=r" (oldstat) : "r"(MIE_MSIE));
SET_CSR(mie, MIE_MSIE);
}
else if (irq == RISCV_IRQ_MTIMER)
{
/* Read mstatus & set machine timer interrupt enable in mie */
asm volatile("csrrs %0, mie, %1"
: "=r"(oldstat)
: "r"(MIE_MTIE));
SET_CSR(mie, MIE_MTIE);
}
else if (irq > RISCV_IRQ_MEXT)
{
@ -197,19 +192,19 @@ void up_enable_irq(int irq)
irqstate_t up_irq_enable(void)
{
uint64_t oldstat;
irqstate_t oldstat;
#if 1
/* Enable MEIE (machine external interrupt enable) */
/* TODO: should move to up_enable_irq() */
asm volatile ("csrrs %0, mie, %1": "=r" (oldstat) : "r"(MIE_MEIE));
SET_CSR(mie, MIE_MEIE);
#endif
/* Read mstatus & set machine interrupt enable (MIE) in mstatus */
asm volatile ("csrrs %0, mstatus, %1": "=r" (oldstat) : "r"(MSTATUS_MIE));
oldstat = READ_AND_SET_CSR(mstatus, MSTATUS_MIE);
return oldstat;
}

7
arch/risc-v/src/rv32m1/rv32m1_irq.c
View File

@ -32,6 +32,7 @@
#include <nuttx/board.h>
#include <arch/irq.h>
#include <arch/board/board.h>
#include <arch/csr.h>
#include "riscv_internal.h"
#include "riscv_arch.h"
@ -254,18 +255,18 @@ void riscv_ack_irq(int irq)
irqstate_t up_irq_enable(void)
{
uint32_t oldstat;
irqstate_t oldstat;
#if 1
/* Enable MEIE (machine external interrupt enable) */
/* TODO: should move to up_enable_irq() */
asm volatile ("csrrs %0, mie, %1": "=r" (oldstat) : "r"(MIE_MEIE));
SET_CSR(mie, MIE_MEIE);
#endif
/* Read mstatus & set machine interrupt enable (MIE) in mstatus */
asm volatile ("csrrs %0, mstatus, %1": "=r" (oldstat) : "r"(MSTATUS_MIE));
oldstat = READ_AND_SET_CSR(mstatus, MSTATUS_MIE);
return oldstat;
}