Cortex-M7: Add cache operations
This commit is contained in:
Gregory Nutt
parent
d3033efa9c
commit
e39077775d
429
arch/arm/src/armv7-m/up_dcache.c
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429
arch/arm/src/armv7-m/up_dcache.c
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/****************************************************************************
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* arch/arm/src/armv7-m/up_dcache.c
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Some logic in this header file derives from the ARM CMSIS core_cm7.h
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* header file which has a compatible 3-clause BSD license:
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*
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* Copyright (c) 2009 - 2014 ARM LIMITED. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name ARM, NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "cache.h"
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#ifdef CONFIG_ARMV7M_DCACHE
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: arch_enable_dcache
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*
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* Description:
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* Enable the D-Cache
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void arch_enable_dcache(void)
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{
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uint32_t ccsidr;
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uint32_t ccr;
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uint32_t sshift;
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uint32_t wshift;
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uint32_t sw;
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uint32_t sets;
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uint32_t ways;
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/* Get the characteristics of the D-Cache */
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ccsidr = getreg32(NVIC_CCSIDR);
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sets = CCSIDR_SETS(ccsidr);
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sshift = CCSIDR_LSSHIFT(ccsidr) + 4;
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ways = CCSIDR_WAYS(ccsidr);
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wshift = arm_clz(ways) & 0x1f;
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/* Invalidate the D-Cache */
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ARM_DSB();
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do
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{
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int32_t tmpways = ways;
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do
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{
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sw = ((tmpways << wshift) | (sets << sshift));
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putreg32(sw, NVIC_DCISW);
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}
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while (tmpways--);
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}
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while(sets--);
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ARM_DSB();
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/* Enable the D-Cache */
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ccr = getreg32(NVIC_CFGCON);
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ccr |= NVIC_CFGCON_DC;
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putreg32(ccr, NVIC_CFGCON);
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ARM_DSB();
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ARM_ISB();
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}
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/****************************************************************************
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* Name: arch_disable_dcache
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*
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* Description:
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* Disable the D-Cache
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void arch_disable_dcache(void)
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{
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uint32_t ccsidr;
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uint32_t ccr;
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uint32_t sshift;
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uint32_t wshift;
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uint32_t sw;
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uint32_t sets;
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uint32_t ways;
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/* Get the characteristics of the D-Cache */
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ccsidr = getreg32(NVIC_CCSIDR);
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sets = CCSIDR_SETS(ccsidr);
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sshift = CCSIDR_LSSHIFT(ccsidr) + 4;
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ways = CCSIDR_WAYS(ccsidr);
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wshift = arm_clz(ways) & 0x1f;
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ARM_DSB();
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/* Disable the D-Cache */
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ccr = getreg32(NVIC_CFGCON);
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ccr &= ~NVIC_CFGCON_DC;
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putreg32(ccr, NVIC_CFGCON);
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/* Clean and invalidate the D-Cache */
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do
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{
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int32_t tmpways = ways;
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do
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{
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sw = ((tmpways << wshift) | (sets << sshift));
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putreg32(sw, NVIC_DCCISW);
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}
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while (tmpways--);
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}
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while (sets--);
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ARM_DSB();
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ARM_ISB();
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}
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/****************************************************************************
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* Name: arch_invalidate_dcache
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*
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* Description:
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* Invalidate the data cache within the specified region; we will be
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* performing a DMA operation in this region and we want to purge old data
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* in the cache.
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*
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* Input Parameters:
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* start - virtual start address of region
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* end - virtual end address of region + 1
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*
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* Returned Value:
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* None
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*
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* Assumptions:
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* This operation is not atomic. This function assumes that the caller
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* has exclusive access to the address range so that no harm is done if
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* the operation is pre-empted.
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*
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****************************************************************************/
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#if 0 /* Not implemented */
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void arch_invalidate_dcache(uintptr_t start, uintptr_t end)
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{
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#warning Missing logic
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}
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#endif
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/****************************************************************************
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* Name: arch_invalidate_dcache_all
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*
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* Description:
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* Invalidate the entire contents of D cache.
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void arch_invalidate_dcache_all(void)
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{
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uint32_t ccsidr;
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uint32_t sshift;
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uint32_t wshift;
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uint32_t sw;
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uint32_t sets;
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uint32_t ways;
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/* Get the characteristics of the D-Cache */
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ccsidr = getreg32(NVIC_CCSIDR);
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sets = CCSIDR_SETS(ccsidr);
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sshift = CCSIDR_LSSHIFT(ccsidr) + 4;
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ways = CCSIDR_WAYS(ccsidr);
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wshift = arm_clz(ways) & 0x1f;
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ARM_DSB();
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/* Invalidate D-Cache */
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do
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{
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int32_t tmpways = ways;
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do
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{
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sw = ((tmpways << wshift) | (sets << sshift));
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putreg32(sw, NVIC_DCISW);
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}
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while (tmpways--);
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}
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while (sets--);
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ARM_DSB();
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ARM_ISB();
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}
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/****************************************************************************
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* Name: arch_clean_dcache
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*
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* Description:
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* Clean the data cache within the specified region by flushing the
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* contents of the data cache to memory.
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*
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* Input Parameters:
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* start - virtual start address of region
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* end - virtual end address of region + 1
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*
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* Returned Value:
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* None
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*
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* Assumptions:
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* This operation is not atomic. This function assumes that the caller
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* has exclusive access to the address range so that no harm is done if
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* the operation is pre-empted.
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*
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****************************************************************************/
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#if 0 /* Not implemented */
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void arch_clean_dcache(uintptr_t start, uintptr_t end)
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{
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#warning Missing logic
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}
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#endif
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/****************************************************************************
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* Name: arch_clean_dcache_all
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*
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* Description:
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* Clean the entire data cache within the specified region by flushing the
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* contents of the data cache to memory.
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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* Assumptions:
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* This operation is not atomic. This function assumes that the caller
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* has exclusive access to the address range so that no harm is done if
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* the operation is pre-empted.
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*
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****************************************************************************/
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void arch_clean_dcache_all(void)
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{
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uint32_t ccsidr;
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uint32_t sshift;
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uint32_t wshift;
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uint32_t sw;
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uint32_t sets;
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uint32_t ways;
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/* Get the characteristics of the D-Cache */
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ccsidr = getreg32(NVIC_CCSIDR);
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sets = CCSIDR_SETS(ccsidr);
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sshift = CCSIDR_LSSHIFT(ccsidr) + 4;
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ways = CCSIDR_WAYS(ccsidr);
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wshift = arm_clz(ways) & 0x1f;
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ARM_DSB();
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/* Clean D-Cache */
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do
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{
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int32_t tmpways = ways;
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do
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{
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sw = ((tmpways << wshift) | (sets << sshift));
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putreg32(sw, NVIC_DCCSW);
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}
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while (tmpways--);
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}
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while(sets--);
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ARM_DSB();
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ARM_ISB();
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}
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/****************************************************************************
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* Name: arch_flush_dcache
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*
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* Description:
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* Flush the data cache within the specified region by cleaning and
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* invalidating the D cache.
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*
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* Input Parameters:
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* start - virtual start address of region
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* end - virtual end address of region + 1
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*
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* Returned Value:
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* None
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*
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* Assumptions:
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* This operation is not atomic. This function assumes that the caller
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* has exclusive access to the address range so that no harm is done if
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* the operation is pre-empted.
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*
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****************************************************************************/
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#if 0 /* Not implemented */
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void arch_flush_dcache(uintptr_t start, uintptr_t end)
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{
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#warning Missing logic
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}
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#endif
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/****************************************************************************
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* Name: arch_flush_dcache_all
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*
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* Description:
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* Flush the entire data cache by cleaning and invalidating the D cache.
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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* Assumptions:
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* This operation is not atomic. This function assumes that the caller
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* has exclusive access to the address range so that no harm is done if
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* the operation is pre-empted.
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*
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****************************************************************************/
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void arch_flush_dcache_all(void)
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{
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uint32_t ccsidr;
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uint32_t sshift;
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uint32_t wshift;
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uint32_t sw;
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uint32_t sets;
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uint32_t ways;
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/* Get the characteristics of the D-Cache */
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ccsidr = getreg32(NVIC_CCSIDR);
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sets = CCSIDR_SETS(ccsidr);
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sshift = CCSIDR_LSSHIFT(ccsidr) + 4;
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ways = CCSIDR_WAYS(ccsidr);
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wshift = arm_clz(ways) & 0x1f;
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ARM_DSB();
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/* Clean and invalidate D-Cache */
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do
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{
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int32_t tmpways = ways;
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do
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{
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sw = ((tmpways << wshift) | (sets << sshift));
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putreg32(sw, NVIC_DCCISW);
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}
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while (tmpways--);
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}
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while (sets--);
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ARM_DSB();
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ARM_ISB();
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}
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#endif /* CONFIG_ARMV7M_DCACHE */
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