imx9_clockconfig: Add way to query / calculate PLL frequencies
The frequency LUT idea is not necessary as the PLL output can be calculated by the CPU. It is better to do this as the clocks are set by the SPL (2nd stage program loader) which means the NuttX payload would not have access to such a LUT anyhow. The mask PLL_DIV_RDIV_MASK is also fixed, as that was simply wrong. Also add call to imx9_clockconfig (although it does not do anything yet).
This commit is contained in:
Ville Juven
Alan Carvalho de Assis
parent
b934555fd1
commit
e3f4749a3c
@ -311,7 +311,7 @@ config IMX9_LPSPI
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default n
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config IMX9_PLL
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bool "PLL setup support (WIP)"
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bool "PLL setup support"
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default n
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menu "LPI2C Peripherals"
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@ -155,7 +155,7 @@
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#define PLL_DIV_ODIV_MASK (0xff << PLL_DIV_ODIV_SHIFT)
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#define PLL_DIV_ODIV(n) (((n) << PLL_DIV_ODIV_SHIFT) & PLL_DIV_ODIV_MASK)
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#define PLL_DIV_RDIV_SHIFT (13) /* Bits 13-15: Input Clock Predivider */
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#define PLL_DIV_RDIV_MASK (0xe << PLL_DIV_RDIV_SHIFT)
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#define PLL_DIV_RDIV_MASK (0x7 << PLL_DIV_RDIV_SHIFT)
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#define PLL_DIV_RDIV(n) (((n) << PLL_DIV_RDIV_SHIFT) & PLL_DIV_RDIV_MASK)
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#define PLL_DIV_MFI_SHIFT (16) /* Bits 16-24: Integer Portion of Loop Divider */
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#define PLL_DIV_MFI_MASK (0x1ff << PLL_DIV_MFI_SHIFT)
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@ -99,6 +99,10 @@ void arm64_chip_boot(void)
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arm64_mmu_init(true);
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/* Initialize system clocks to some sensible state */
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imx9_clockconfig();
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/* Do UART early initialization & pin muxing */
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#ifdef CONFIG_IMX9_LPUART
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@ -50,46 +50,15 @@
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} \
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while (0)
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/****************************************************************************
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* Private Types
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****************************************************************************/
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/* The base oscillator frequency is 24MHz */
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/****************************************************************************
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* Private Data
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****************************************************************************/
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static uint32_t g_pll_freqs[] =
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{
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[OSC_24M] = 24000000U, /* 24MHZ OSCILLATOR. */
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[ARM_PLL] = 2000000000U, /* ARM PLL */
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[ARM_PLLOUT] = 2000000000U, /* ARM PLL OUT */
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[SYS_PLL1_IN] = 4000000000U, /* SYSTEM PLL1 IN */
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[SYS_PLL1PFD0_IN] = 1000000000U, /* SYSTEM PLL1 PFD0 IN */
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[SYS_PLL1PFD0] = 1000000000U, /* SYSTEM PLL1 PFD0 */
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[SYS_PLL1PFD0DIV2] = 500000000U, /* SYSTEM PLL1 PFD0 DIV2 */
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[SYS_PLL1PFD1_IN] = 800000000U, /* SYSTEM PLL1 PFD1 IN */
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[SYS_PLL1PFD1] = 800000000U, /* SYSTEM PLL1 PFD1 */
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[SYS_PLL1PFD1DIV2] = 400000000U, /* SYSTEM PLL1 PFD1 DIV2 */
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[SYS_PLL1PFD2_IN] = 625000000U, /* SYSTEM PLL1 PFD2 IN */
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[SYS_PLL1PFD2] = 625000000U, /* SYSTEM PLL1 PFD2 */
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[SYS_PLL1PFD2DIV2] = 312500000U, /* SYSTEM PLL1 PFD2 DIV2 */
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[AUDIO_PLL1] = 0U, /* AUDIO PLL1 */
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[AUDIO_PLL1OUT] = 0U, /* AUDIO PLL1 OUT */
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[DRAM_PLL] = 1000000000U, /* DRAM PLL */
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[DRAM_PLLOUT] = 1000000000U, /* DRAM PLL OUT */
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[VIDEO_PLL1] = 0U, /* VIDEO PLL1 */
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[VIDEO_PLL1OUT] = 0U, /* VIDEO PLL1 OUT */
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[EXT] = 0U /* EXT */
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};
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#define XTAL_FREQ 24000000u
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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#ifdef CONFIG_IMX9_PLL
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# error "Missing logic"
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static int pll_init(uintptr_t reg, bool frac, struct pll_parms *parm)
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{
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uint32_t val;
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@ -137,9 +106,9 @@ static int pll_init(uintptr_t reg, bool frac, struct pll_parms *parm)
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static int pll_pfd_init(uintptr_t reg, int pfd, struct pfd_parms *pfdparm)
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{
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uintptr_t ctrl;
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uintptr_t div;
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uint32_t val;
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uint32_t ctrl;
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uint32_t div;
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uint32_t val;
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/* Determine the PFD register set */
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@ -196,6 +165,185 @@ static int pll_pfd_init(uintptr_t reg, int pfd, struct pfd_parms *pfdparm)
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return OK;
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}
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static uint32_t calculate_vco_freq(const struct pll_parms *parm, bool frac)
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{
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/* Base clock is common for all VCO:s */
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if (frac)
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{
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return (uint64_t)XTAL_FREQ * (parm->mfi * parm->mfd + parm->mfn) /
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parm->mfd / parm->rdiv;
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}
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else
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{
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return (uint64_t)XTAL_FREQ * parm->mfi / parm->rdiv;
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}
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}
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static uint32_t vco_freq_out(uintptr_t reg, bool frac)
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{
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struct pll_parms parm;
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uint32_t ctrl;
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uint32_t status;
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uint32_t div;
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/* Check if the PLL on or off */
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ctrl = getreg32(PLL_CTRL(reg));
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if ((ctrl & PLL_CTRL_POWERUP) == 0)
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{
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return 0;
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}
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/* Check if the PLL is stable */
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status = getreg32(PLL_PLL_STATUS(reg));
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if ((status & PLL_PLL_STATUS_PLL_LOCK) == 0)
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{
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return 0;
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}
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/* Populate the integer and fractional PLL parameters */
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div = getreg32(PLL_DIV(reg));
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parm.rdiv = (div & PLL_DIV_RDIV_MASK) >> PLL_DIV_RDIV_SHIFT;
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parm.mfi = (div & PLL_DIV_MFI_MASK) >> PLL_DIV_MFI_SHIFT;
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/* RDIV values 0 and 1 both mean a divisor of 1 */
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if (parm.rdiv == 0)
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{
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parm.rdiv = 1;
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}
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if (frac)
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{
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/* Fill the fractional parameters */
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parm.mfn = getreg32(PLL_NUMERATOR(reg)) & PLL_NUMERATOR_MFN_MASK;
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parm.mfn >>= PLL_NUMERATOR_MFN_SHIFT;
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parm.mfd = getreg32(PLL_DENOMINATOR(reg)) & PLL_DENOMINATOR_MFD_MASK;
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parm.mfd >>= PLL_DENOMINATOR_MFD_SHIFT;
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}
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return calculate_vco_freq(&parm, frac);
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}
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static uint32_t pll_freq_out(uintptr_t reg, bool frac)
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{
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uint32_t ctrl;
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uint32_t div;
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uint32_t vco;
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/* Read the MUX control register and check if bypass mode is enabled */
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ctrl = getreg32(PLL_CTRL(reg));
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if (ctrl & PLL_CTRL_CLKMUX_BYPASS)
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{
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return XTAL_FREQ;
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}
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/* If the mux is disabled output frequency is 0 */
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if ((ctrl & PLL_CTRL_CLKMUX_EN) == 0)
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{
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return 0;
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}
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/* Get input VCO frequency */
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vco = vco_freq_out(reg, frac);
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if (vco == 0)
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{
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/* The VCO is off or unstable */
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return 0;
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}
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/* Calculate the output clock divider */
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div = (getreg32(PLL_DIV(reg)) & PLL_DIV_ODIV_MASK) >> PLL_DIV_ODIV_SHIFT;
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/* According to spec, div0 = 2 and div1 = 3 */
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if (div == 0)
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{
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div = 2;
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}
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else if (div == 1)
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{
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div = 3;
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}
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return vco / div;
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}
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static uint32_t pll_pfd_freq_out(uintptr_t reg, int pfd, int div2)
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{
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struct pfd_parms parm;
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uint32_t ctrl;
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uint32_t div;
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uint32_t vco;
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/* Read the correct PFD register set */
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switch (pfd)
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{
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case 0:
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ctrl = getreg32(PLL_DFS_CTRL_0(reg));
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div = getreg32(PLL_DFS_DIV_0(reg));
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break;
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case 1:
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ctrl = getreg32(PLL_DFS_CTRL_1(reg));
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div = getreg32(PLL_DFS_DIV_1(reg));
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break;
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case 2:
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ctrl = getreg32(PLL_DFS_CTRL_2(reg));
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div = getreg32(PLL_DFS_DIV_2(reg));
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break;
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default:
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return 0;
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}
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/* Get input VCO frequency */
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vco = vco_freq_out(reg, true);
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if (vco == 0)
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{
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/* The VCO is off or unstable */
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return 0;
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}
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/* If the DFS part is bypassed, the output is the VCO directly */
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if (ctrl & PLL_DFS_BYPASS_EN)
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{
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return vco;
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}
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/* Check if the DFS part is disabled */
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if ((ctrl & PLL_DFS_ENABLE) == 0)
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{
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return 0;
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}
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/* Populate the DFS parameters */
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parm.mfi = (div & PLL_DFS_MFI_MASK) >> PLL_DFS_MFI_SHIFT;
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parm.mfn = (div & PLL_DFS_MFN_MASK) >> PLL_DFS_MFN_SHIFT;
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return ((uint64_t)vco * 5) / (parm.mfi * 5 + parm.mfn) / div2;
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}
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#endif
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/****************************************************************************
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@ -260,13 +408,60 @@ void imx9_clockconfig(void)
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int imx9_get_clock(int clkname, uint32_t *frequency)
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{
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if (clkname >= EXT)
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switch (clkname)
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{
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*frequency = 0;
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return -ENODEV;
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case OSC_24M:
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*frequency = XTAL_FREQ;
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break;
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case ARM_PLL:
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*frequency = pll_freq_out(IMX9_ARMPLL_BASE, false);
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break;
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case SYS_PLL1_IN:
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*frequency = pll_freq_out(IMX9_SYSPLL_BASE, false);
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break;
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case SYS_PLL1PFD0:
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*frequency = pll_pfd_freq_out(IMX9_SYSPLL_BASE, 0, 1);
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break;
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case SYS_PLL1PFD0DIV2:
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*frequency = pll_pfd_freq_out(IMX9_SYSPLL_BASE, 0, 2);
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break;
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case SYS_PLL1PFD1:
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*frequency = pll_pfd_freq_out(IMX9_SYSPLL_BASE, 1, 1);
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break;
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case SYS_PLL1PFD1DIV2:
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*frequency = pll_pfd_freq_out(IMX9_SYSPLL_BASE, 1, 2);
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break;
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case SYS_PLL1PFD2:
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*frequency = pll_pfd_freq_out(IMX9_SYSPLL_BASE, 2, 1);
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break;
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case SYS_PLL1PFD2DIV2:
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*frequency = pll_pfd_freq_out(IMX9_SYSPLL_BASE, 2, 2);
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break;
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case AUDIO_PLL1OUT:
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*frequency = pll_freq_out(IMX9_AUDIOPLL_BASE, true);
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break;
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case DRAM_PLLOUT:
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*frequency = pll_freq_out(IMX9_DRAMPLL_BASE, true);
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break;
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case VIDEO_PLL1OUT:
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*frequency = pll_freq_out(IMX9_VIDEOPLL_BASE, true);
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break;
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default:
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return -ENODEV;
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}
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*frequency = g_pll_freqs[clkname];
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return OK;
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}
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