Merged nuttx/nuttx into master

Documentation/README.html

@@ -8,7 +8,7 @@
   <tr align="center" bgcolor="#e4e4e4">
     <td>
       <h1><big><font color="#3c34ec"><i>NuttX README Files</i></font></big></h1>
-      <p>Last Updated: November 1, 2016</p>
+      <p>Last Updated: November 14, 2016</p>
     </td>
   </tr>
 </table>
@@ -150,6 +150,8 @@ nuttx/
  |   |   `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/mikroe-stm32f4/README.txt" target="_blank"><b><i>README.txt</i></b></a>
  |   |- mirtoo/
  |   |   `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/mirtoo/README.txt" target="_blank"><b><i>README.txt</i></b></a>
+ |   |- misoc/
+ |   |   `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/misoc/README.txt" target="_blank"><b><i>README.txt</i></b></a>
  |   |- moteino-mega/
  |   |   `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/moteino-mega/README.txt" target="_blank"><b><i>README.txt</i></b></a>
  |   |- mx1ads/
@@ -382,7 +384,8 @@ apps/
  |- gpsutils/
  |   `- <a href="https://bitbucket.org/nuttx/apps/src/master/gpsutils/minmea/README.txt" target="_blank">"<b><i>minmea/README.txt</i></b></a>
  |- graphics/
- |   `- <a href="https://bitbucket.org/nuttx/apps/src/master/graphics/tiff/README.txt" target="_blank">"<b><i>tiff/README.txt</i></b></a>
+ |   |- <a href="https://bitbucket.org/nuttx/apps/src/master/graphics/tiff/README.txt" target="_blank">"<b><i>tiff/README.txt</i></b></a>
+ |   `- <a href="https://bitbucket.org/nuttx/apps/src/master/graphics/traveler/tools/tcledit/README.txt" target="_blank">"<b><i>traveler/tools/tcledit/README.txt</i></b></a>
  |- interpreters/
  |   |- <a href="https://bitbucket.org/nuttx/apps/src/master/interpreters/bas/README.txt" target="_blank"><b><i>bas/README.txt</i></b></a>
  |   |- <a href="https://bitbucket.org/nuttx/apps/src/master/interpreters/ficl/README.txt" target="_blank"><b><i>ficl/README.txt</i></b></a>

README.txt

@@ -1366,6 +1366,8 @@ nuttx/
  |   |   `- README.txt
  |   |- mirtoo/
  |   |   `- README.txt
+ |   |- misoc/
+ |   |   `- README.txt
  |   |- moteino-mega/
  |   |   `- README.txt
  |   |- mx1ads/
@@ -1595,7 +1597,8 @@ apps/
  |- gpsutils/
  |   `- minmea/README.txt
  |- graphics/
- |   `- tiff/README.txt
+ |   |- tiff/README.txt
+ |   `- traveler/tools/tcledit/README.txt
  |- interpreters/
  |   |- bas
  |   |  `- README.txt

TODO

@@ -1,4 +1,4 @@
-NuttX TODO List (Last updated October 9, 2016)
+NuttX TODO List (Last updated November 2, 2016)
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 This file summarizes known NuttX bugs, limitations, inconsistencies with
@@ -9,7 +9,7 @@ issues related to each board port.
 
 nuttx/:
 
- (13)  Task/Scheduler (sched/)
+ (14)  Task/Scheduler (sched/)
   (1)  Memory Management (mm/)
   (1)  Power Management (drivers/pm)
   (3)  Signals (sched/signal, arch/)
@@ -216,6 +216,74 @@ o Task/Scheduler (sched/)
   Status:      Open
   Priority:    Medium-ish
 
+  Title:       ISSUES WITH PRIORITY INHERITANCE WHEN SEMAPHORE/MUTX IS USED AS IPC
+  Description: Semaphores have multiple uses.  The typical usage is where
+               the semaphore is used as lock on one or more resources.  In
+               this typical case, priority inheritance works perfectly:  The
+               holder of a semaphore count must be remembered so that its
+               priority can be boosted if a higher priority task requires a
+               count from the semaphore.  It remains the holder until the
+               same task calls sem_post() to release the count on the
+               semaphore.
+
+               But a different usage model for semaphores is for signalling
+               events.  In this case, the semaphore count is initialized to
+               zero and the receiving task calls sem_wait() to wait for the
+               next event of interest.  When an event of interest is
+               detected by another task (or even an interrupt handler),
+               sem_post() is called which increments the count to 1 and
+               wakes up the receiving task.
+
+               For example, in the following TASK A waits for events and
+               TASK B (or perhaps an interrupt handler) signals task A of
+               the occurence of the events by posting the semaphore:
+
+                 ---------------------- ---------------
+                 TASK A                 TASK B
+                 ---------------------- ---------------
+                 sem_init(sem, 0, 0);
+                 sem_wait(sem);
+                                        sem_post(sem);
+                 Awakens as holder
+                 ---------------------- ---------------
+
+               These two usage models are really very different and priority
+               inheritance simply does not apply when the semaphore is used for
+               signalling rather than locking.  In this signalling case
+               priority inheritance can interfere with the operation of the
+               semaphore.  The problem is that when TASK A is awakened it is
+               a holder of the semaphore.  Normally, a task is removed from
+               the holder list when it finally releases the semaphore via
+               sem_post().
+              
+               However, TASK A never calls sem_post(sem) so it becomes
+               *permanently* a holder of the semaphore and may have its
+               priority boosted at any time when any other task tries to
+               acquire the semaphore.
+
+               The fix is to call sem_setprotocol(SEM_PRIO_NONE) immediately
+               after the sem_init() call so that there will be no priority
+               inheritance operations on this semaphore used for signalling.
+
+               NOTE also that in NuttX, pthread mutexes are build on top of
+               binary semaphores.  As a result, the above recommendation also
+               applies when pthread mutexes are used for inter-thread
+               signaling.  That is, a mutex that is used for signaling should
+               be initialize like this (simplified, no error checking here):
+
+                  pthread_mutexattr_t attr;
+                  pthread_mutex_t mutex;
+
+                  pthread_mutexattr_init(&attr);
+                  pthread_mutexattr_settype(&attr, PTHREAD_PRIO_NONE);
+                  pthread_mutex_init(&mutex, &attr);
+
+  Status:      Closed.  If you have priority inheritance enabled and you use
+               semaphores for signalling events, then you *must* call
+               sem_setprotocol(SEM_PRIO_NONE) immediately after initializing
+               the semaphore.
+  Priority:    High.
+
   Title:       SCALABILITY
   Description: Task control information is retained in simple lists.  This
                is completely appropriate for small embedded systems where
@@ -398,22 +466,24 @@ o pthreads (sched/pthreads)
   Priority:    Low, probably not that useful
 
   Title:       PTHREAD_PRIO_PROTECT
-  Description: Extended pthread_mutexattr_setprotocol() support PTHREAD_PRIO_PROTECT:
+  Description: Extend pthread_mutexattr_setprotocol() support PTHREAD_PRIO_PROTECT:
+
                "When a thread owns one or more mutexes initialized with the
                PTHREAD_PRIO_PROTECT protocol, it shall execute at the higher of its
                priority  or  the  highest  of the priority ceilings of all the mutexes
                owned by this thread and initialized with this attribute, regardless of
                whether other threads are blocked on any of these mutexes or not.
 
-               "While  a  thread is holding a mutex which has been initialized with
+               "While a thread is holding a mutex which has been initialized with
                the PTHREAD_PRIO_INHERIT or PTHREAD_PRIO_PROTECT protocol attributes,
                it shall not be subject to being moved to the tail of the scheduling queue
                at its priority in the event that its original priority is changed,
                such as by a call to sched_setparam(). Likewise, when a thread unlocks
                a mutex that has been initialized with the PTHREAD_PRIO_INHERIT or
                PTHREAD_PRIO_PROTECT protocol attributes, it shall not be subject to
-               being moved to the tail of the scheduling queue at its priority in  the
+               being moved to the tail of the scheduling queue at its priority in the
                event that its original priority is changed."
+
   Status:      Open.  No changes planned.
   Priority:    Low -- about zero, probably not that useful. Priority inheritance is
                already supported and is a much better solution.  And it turns out
@@ -421,39 +491,39 @@ o pthreads (sched/pthreads)
                Excerpted from my post in a Linked-In discussion:
 
                "I started to implement this HLS/"PCP" semaphore in an RTOS that I
-               work with (http://www.nuttx.org) and I discovered after doing the
+                work with (http://www.nuttx.org) and I discovered after doing the
-               analysis and basic code framework that a complete solution for the
+                analysis and basic code framework that a complete solution for the
-               case of a counting semaphore is still quite complex -- essentially
+                case of a counting semaphore is still quite complex -- essentially
-               as complex as is priority inheritance.
+                as complex as is priority inheritance.
 
                "For example, suppose that a thread takes 3 different HLS semaphores
-               A, B, and C. Suppose that they are prioritized in that order with
+                A, B, and C. Suppose that they are prioritized in that order with
-               A the lowest and C the highest. Suppose the thread takes 5 counts
+                A the lowest and C the highest. Suppose the thread takes 5 counts
-               from A, 3 counts from B, and 2 counts from C. What priority should
+                from A, 3 counts from B, and 2 counts from C. What priority should
-               it run at? It would have to run at the priority of the highest
+                it run at? It would have to run at the priority of the highest
-               priority semaphore C. This means that the RTOS must maintain
+                priority semaphore C. This means that the RTOS must maintain
-               internal information of the priority of every semaphore held by
+                internal information of the priority of every semaphore held by
-               the thread.
+                the thread.
 
                "Now suppose it releases one count on semaphore B. How does the
-               RTOS know that it still holds 2 counts on B? With some complex
+                RTOS know that it still holds 2 counts on B? With some complex
-               internal data structure. The RTOS would have to maintain internal
+                internal data structure. The RTOS would have to maintain internal
-               information about how many counts from each semaphore are held
+                information about how many counts from each semaphore are held
-               by each thread.
+                by each thread.
 
                "How does the RTOS know that it should not decrement the priority
-               from the priority of C? Again, only with internal complexity. It
+                from the priority of C? Again, only with internal complexity. It
-               would have to know the priority of every semaphore held by
+                would have to know the priority of every semaphore held by
-               every thread.
+                every thread.
 
                "Providing the HLS capability on a simple pthread mutex would not
-               be such quite such a complex job if you allow only one mutex per
+                be such quite such a complex job if you allow only one mutex per
-               thread. However, the more general case seems almost as complex
+                thread. However, the more general case seems almost as complex
-               as priority inheritance. I decided that the implementation does
+                as priority inheritance. I decided that the implementation does
-               not have value to me. I only wanted it for its reduced
+                not have value to me. I only wanted it for its reduced
-               complexity; in all other ways I believe that it is the inferior
+                complexity; in all other ways I believe that it is the inferior
-               solution. So I discarded a few hours of programming. Not a
+                solution. So I discarded a few hours of programming. Not a
-               big loss from the experience I gained."
+                big loss from the experience I gained."
 
 o Message Queues (sched/mqueue)
   ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

arch/Kconfig

@@ -39,6 +39,13 @@ config ARCH_MIPS
 	---help---
 		MIPS architectures (PIC32)
 
+config ARCH_MISOC
+	bool "MISOC"
+	select ARCH_HAVE_INTERRUPTSTACK
+	select ARCH_HAVE_CUSTOMOPT
+	---help---
+		MISOC
+
 config ARCH_RGMP
 	bool "RGMP"
 	---help---
@@ -99,6 +106,7 @@ config ARCH
 	default "avr"     if ARCH_AVR
 	default "hc"      if ARCH_HC
 	default "mips"    if ARCH_MIPS
+	default "misoc"   if ARCH_MISOC
 	default "rgmp"    if ARCH_RGMP
 	default "renesas" if ARCH_RENESAS
 	default "risc-v"  if ARCH_RISCV
@@ -112,6 +120,7 @@ source arch/arm/Kconfig
 source arch/avr/Kconfig
 source arch/hc/Kconfig
 source arch/mips/Kconfig
+source arch/misoc/Kconfig
 source arch/rgmp/Kconfig
 source arch/renesas/Kconfig
 source arch/risc-v/Kconfig

arch/arm/src/armv7-r/Kconfig

@@ -3,7 +3,7 @@
 # see the file kconfig-language.txt in the NuttX tools repository.
 #
 
-comment "ARMv7-A Configuration Options"
+comment "ARMv7-R Configuration Options"
 
 config ARMV7R_MEMINIT
 	bool
@@ -19,6 +19,29 @@ config ARMV7R_MEMINIT
 		the memory initialization first, then explicitly call
 		arm_data_initialize().
 
+config ARMV7R_HAVE_ICACHE
+	bool
+	default n
+
+config ARMV7R_HAVE_DCACHE
+	bool
+	default n
+
+config ARMV7R_ICACHE
+	bool "Use I-Cache"
+	default n
+	depends on ARMV7R_HAVE_ICACHE
+
+config ARMV7R_DCACHE
+	bool "Use D-Cache"
+	default n
+	depends on ARMV7R_HAVE_DCACHE
+
+config ARMV7R_DCACHE_WRITETHROUGH
+	bool "D-Cache Write-Through"
+	default n
+	depends on ARMV7R_DCACHE
+
 config ARMV7R_HAVE_L2CC
 	bool
 	default n
@@ -162,7 +185,7 @@ config ARMV7R_TOOLCHAIN_GNU_OABI
 	---help---
 		This option should work for any GNU toolchain configured for arm-elf-.
 
-endchoice # ARMV7R_HAVE_L2CC
+endchoice # Toolchain Selection
 
 config ARMV7R_OABI_TOOLCHAIN
 	bool "OABI (vs EABI)"

arch/arm/src/armv7-r/arm_fullcontextrestore.S

@@ -60,7 +60,6 @@
 	.cpu	cortex-r4f
 #endif
 	.syntax	unified
-	.file	"arm_fullcontextrestore.S"
 
 /****************************************************************************
  * Public Functions
@@ -157,20 +156,11 @@ up_fullcontextrestore:
 	 */
 
 	ldr		r1, [r0, #(4*REG_CPSR)]	/* Fetch the stored CPSR value */
-	msr		cpsr, r1				/* Set the CPSR */
+	msr		spsr_cxsf, r1				/* Set the SPSR */
 
-	/* Now recover r0 and r1 */
+	/* Now recover r0-r1, pc and cpsr, destroying the stack frame */
-
-	ldr		r0, [sp]
-	ldr		r1, [sp, #4]
-	add		sp, sp, #(2*4)
-
-	/* Then return to the address at the stop of the stack,
-	 * destroying the stack frame
-	 */
-
-	ldr		pc, [sp], #4
 
+	ldmia		sp!, {r0-r1, pc}^
 #endif
 
 	.size up_fullcontextrestore, . - up_fullcontextrestore

arch/arm/src/armv7-r/arm_vectors.S

@@ -202,7 +202,7 @@ arm_vectorirq:
 	/* Restore the CPSR, SVC mode registers and return */
 
 	ldr		r1, [r0, #(4*REG_CPSR)]	/* Fetch the return SPSR */
-	msr		spsr, r1				/* Set the return mode SPSR */
+	msr		spsr_cxsf, r1			/* Set the return mode SPSR */
 
 #ifdef CONFIG_BUILD_PROTECTED
 	/* Are we leaving in user mode?  If so then we need to restore the
@@ -331,7 +331,7 @@ arm_vectorsvc:
 	/* Restore the CPSR, SVC mode registers and return */
 
 	ldr		r1, [r0, #(4*REG_CPSR)]	/* Fetch the return SPSR */
-	msr		spsr, r1				/* Set the return mode SPSR */
+	msr		spsr_cxsf, r1			/* Set the return mode SPSR */
 
 #ifdef CONFIG_BUILD_PROTECTED
 	/* Are we leaving in user mode?  If so then we need to restore the
@@ -913,7 +913,7 @@ arm_vectorfiq:
 	/* Restore the CPSR, SVC mode registers and return */
 
 	ldr		r1, [r0, #(4*REG_CPSR)]	/* Fetch the return SPSR */
-	msr		spsr, r1				/* Set the return mode SPSR */
+	msr		spsr_cxsf, r1			/* Set the return mode SPSR */
 
 #ifdef CONFIG_BUILD_PROTECTED
 	/* Are we leaving in user mode?  If so then we need to restore the

arch/arm/src/armv7-r/cache.h

@@ -43,6 +43,7 @@
 #include <nuttx/config.h>
 #include <nuttx/irq.h>
 
+#include "sctlr.h"
 #include "cp15_cacheops.h"
 #include "l2cc.h"
 
@@ -50,6 +51,16 @@
  * Pre-processor Definitions
  ************************************************************************************/
 
+/* intrinsics are used in these inline functions */
+
+#define arm_isb(n) __asm__ __volatile__ ("isb " #n : : : "memory")
+#define arm_dsb(n) __asm__ __volatile__ ("dsb " #n : : : "memory")
+#define arm_dmb(n) __asm__ __volatile__ ("dmb " #n : : : "memory")
+
+#define ARM_DSB()  arm_dsb(15)
+#define ARM_ISB()  arm_isb(15)
+#define ARM_DMB()  arm_dmb(15)
+
  /************************************************************************************
  * Inline Functions
  ************************************************************************************/
@@ -183,6 +194,70 @@ static inline void arch_flush_dcache(uintptr_t start, uintptr_t end)
   l2cc_flush(start, end);
 }
 
+/****************************************************************************
+ * Name: arch_enable_icache
+ *
+ * Description:
+ *   Enable the I-Cache
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static inline void arch_enable_icache(void)
+{
+#ifdef CONFIG_ARMV7R_ICACHE
+  uint32_t regval;
+
+  ARM_DSB();
+  ARM_ISB();
+
+  /* Enable the I-Cache */
+
+  regval = cp15_rdsctlr();
+  if ((regval & SCTLR_I) == 0)
+    {
+      cp15_wrsctlr(regval | SCTLR_I);
+    }
+
+  ARM_DSB();
+  ARM_ISB();
+#endif
+}
+
+/****************************************************************************
+* Name: arch_enable_dcache
+*
+* Description:
+*   Enable the D-Cache
+*
+* Input Parameters:
+*   None
+*
+* Returned Value:
+*   None
+*
+****************************************************************************/
+
+static inline void arch_enable_dcache(void)
+{
+#ifdef CONFIG_ARMV7R_DCACHE
+  uint32_t regval;
+
+  /* Enable the D-Cache */
+
+  regval = cp15_rdsctlr();
+  if ((regval & SCTLR_C) == 0)
+    {
+      cp15_wrsctlr(regval | SCTLR_C);
+    }
+#endif
+}
+
 /****************************************************************************
  * Public Data
  ****************************************************************************/

arch/arm/src/armv7-r/mpu.h

@@ -49,6 +49,8 @@
 #  include <debug.h>
 
 #  include "up_arch.h"
+#  include "cache.h"
+#  include "sctlr.h"
 #  include "cp15.h"
 #endif
 
@@ -66,7 +68,7 @@
 
 /* Region Base Address Register Definitions */
 
-#define MPU_RBAR_MASK            0xfffffffc
+#define MPU_RBAR_ADDR_MASK       0xfffffffc
 
 /* Region Size and Enable Register */
 
@@ -201,7 +203,7 @@ static inline unsigned int mpu_get_mpuir(void)
   unsigned int mpuir;
   __asm__ __volatile__
     (
-      "\tmrc " CP15_MPUIR(%0)
+      "\tmrc p15, 0, %0, c0, c0, 4"
       : "=r" (mpuir)
       :
       : "memory"
@@ -222,7 +224,7 @@ static inline void mpu_set_drbar(unsigned int drbar)
 {
   __asm__ __volatile__
     (
-      "\tmcr " CP15_DRBAR(%0)
+      "\tmcr p15, 0, %0, c6, c1, 0"
       :
       : "r" (drbar)
       : "memory"
@@ -241,7 +243,7 @@ static inline void mpu_set_drsr(unsigned int drsr)
 {
   __asm__ __volatile__
     (
-      "\tmcr " CP15_DRSR(%0)
+      "\tmcr p15, 0, %0, c6, c1, 2"
       :
       : "r" (drsr)
       : "memory"
@@ -260,7 +262,7 @@ static inline void mpu_set_dracr(unsigned int dracr)
 {
   __asm__ __volatile__
     (
-      "\tmcr " CP15_DRACR(%0)
+      "\tmcr p15, 0, %0, c6, c1, 4"
       :
       : "r" (dracr)
       : "memory"
@@ -280,7 +282,7 @@ static inline void mpu_set_irbar(unsigned int irbar)
 {
   __asm__ __volatile__
     (
-      "\tmcr " CP15_IRBAR(%0)
+      "\tmcr p15, 0, %0, c6, c1, 1"
       :
       : "r" (irbar)
       : "memory"
@@ -301,7 +303,7 @@ static inline void mpu_set_irsr(unsigned int irsr)
 {
   __asm__ __volatile__
     (
-      "\tmcr " CP15_IRSR(%0)
+      "\tmcr p15, 0, %0, c6, c1, 3"
       :
       : "r" (irsr)
       : "memory"
@@ -322,7 +324,7 @@ static inline void mpu_set_iracr(unsigned int iracr)
 {
   __asm__ __volatile__
     (
-      "\tmcr " CP15_IRACR(%0)
+      "\tmcr p15, 0, %0, c6, c1, 5"
       :
       : "r" (iracr)
       : "memory"
@@ -342,7 +344,7 @@ static inline void mpu_set_rgnr(unsigned int rgnr)
 {
   __asm__ __volatile__
     (
-      "\tmcr " CP15_RGNR(%0)
+      "\tmcr p15, 0, %0, c6, c2, 0"
       :
       : "r" (rgnr)
       : "memory"
@@ -390,7 +392,6 @@ static inline void mpu_control(bool enable)
   if (enable)
     {
       regval |= (SCTLR_M | SCTLR_BR);
-      cp15_wrsctlr(regval);
     }
   else
     {
@@ -408,7 +409,7 @@ static inline void mpu_control(bool enable)
  *
  ****************************************************************************/
 
-#if defined(CONFIG_ARMV7M_HAVE_ICACHE) || defined(CONFIG_ARMV7M_DCACHE)
+#if defined(CONFIG_ARMV7R_HAVE_ICACHE) || defined(CONFIG_ARMV7R_DCACHE)
 static inline void mpu_priv_stronglyordered(uintptr_t base, size_t size)
 {
   unsigned int region = mpu_allocregion();
@@ -422,7 +423,7 @@ static inline void mpu_priv_stronglyordered(uintptr_t base, size_t size)
 
   /* Select the region base address */
 
-  mpu_set_drbar(base & MPU_RBAR_ADDR_MASK) | region | MPU_RBAR_VALID);
+  mpu_set_drbar(base & MPU_RBAR_ADDR_MASK);
 
   /* Select the region size and the sub-region map */
 
@@ -465,7 +466,7 @@ static inline void mpu_user_flash(uintptr_t base, size_t size)
 
   /* Select the region base address */
 
-  mpu_set_drbar((base & MPU_RBAR_ADDR_MASK) | region);
+  mpu_set_drbar(base & MPU_RBAR_ADDR_MASK);
 
   /* Select the region size and the sub-region map */
 
@@ -506,7 +507,7 @@ static inline void mpu_priv_flash(uintptr_t base, size_t size)
 
   /* Select the region base address */
 
-  mpu_set_drbar((base & MPU_RBAR_ADDR_MASK) | region);
+  mpu_set_drbar(base & MPU_RBAR_ADDR_MASK);
 
   /* Select the region size and the sub-region map */
 
@@ -546,7 +547,7 @@ static inline void mpu_user_intsram(uintptr_t base, size_t size)
 
   /* Select the region base address */
 
-  mpu_set_drbar((base & MPU_RBAR_ADDR_MASK) | region);
+  mpu_set_drbar(base & MPU_RBAR_ADDR_MASK);
 
   /* Select the region size and the sub-region map */
 
@@ -587,7 +588,7 @@ static inline void mpu_priv_intsram(uintptr_t base, size_t size)
 
   /* Select the region base address */
 
-  mpu_set_drbar((base & MPU_RBAR_ADDR_MASK) | region);
+  mpu_set_drbar(base & MPU_RBAR_ADDR_MASK);
 
   /* Select the region size and the sub-region map */
 
@@ -628,7 +629,7 @@ static inline void mpu_user_extsram(uintptr_t base, size_t size)
 
   /* Select the region base address */
 
-  mpu_set_drbar((base & MPU_RBAR_ADDR_MASK) | region);
+  mpu_set_drbar(base & MPU_RBAR_ADDR_MASK);
 
   /* Select the region size and the sub-region map */
 
@@ -670,7 +671,7 @@ static inline void mpu_priv_extsram(uintptr_t base, size_t size)
 
   /* Select the region base address */
 
-  mpu_set_drbar((base & MPU_RBAR_ADDR_MASK) | region);
+  mpu_set_drbar(base & MPU_RBAR_ADDR_MASK);
 
   /* Select the region size and the sub-region map */
 
@@ -712,7 +713,7 @@ static inline void mpu_peripheral(uintptr_t base, size_t size)
 
   /* Select the region base address */
 
-  mpu_set_drbar((base & MPU_RBAR_ADDR_MASK) | region);
+  mpu_set_drbar(base & MPU_RBAR_ADDR_MASK);
 
   /* Select the region size and the sub-region map */
 

arch/arm/src/calypso/calypso_keypad.c

@@ -36,6 +36,7 @@
 #include <nuttx/config.h>
 
 #include <nuttx/arch.h>
+#include <nuttx/semaphore.h>
 #include <nuttx/irq.h>
 #include <nuttx/fs/fs.h>
 
@@ -360,9 +361,13 @@ int calypso_kbd_irq(int irq, uint32_t * regs)
 
 void up_keypad(void)
 {
-  /* Semaphore; helps leaving IRQ ctx as soon as possible */
+  /* kbssem semaphore helps leaving IRQ ctx as soon as possible.  This
+   * semaphore is used for signaling and, hence, should not have priority
+   * inheritance enabled.
+   */
 
   sem_init(&kbdsem, 0, 0);
+  sem_setprotocol(&kbdsem, SEM_PRIO_NONE);
 
   /* Drive cols low in idle state such that all buttons cause events */
 

arch/arm/src/efm32/efm32_i2c.c

@@ -71,8 +71,9 @@
 
 #include <nuttx/arch.h>
 #include <nuttx/irq.h>
-#include <nuttx/i2c/i2c_master.h>
 #include <nuttx/clock.h>
+#include <nuttx/semaphore.h>
+#include <nuttx/i2c/i2c_master.h>
 
 #include <arch/board/board.h>
 
@@ -681,8 +682,14 @@ static inline void efm32_i2c_sem_post(FAR struct efm32_i2c_priv_s *priv)
 static inline void efm32_i2c_sem_init(FAR struct efm32_i2c_priv_s *priv)
 {
   sem_init(&priv->sem_excl, 0, 1);
+
 #ifndef CONFIG_I2C_POLLED
+  /* This semaphore is used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
   sem_init(&priv->sem_isr, 0, 0);
+  sem_setprotocol(&priv->sem_isr, SEM_PRIO_NONE);
 #endif
 }
 

arch/arm/src/efm32/efm32_spi.c

@@ -53,6 +53,7 @@
 #include <nuttx/arch.h>
 #include <nuttx/wdog.h>
 #include <nuttx/clock.h>
+#include <nuttx/semaphore.h>
 #include <nuttx/spi/spi.h>
 
 #include <arch/board/board.h>
@@ -1640,6 +1641,13 @@ static int spi_portinitialize(struct efm32_spidev_s *priv)
 
   (void)sem_init(&priv->rxdmasem, 0, 0);
   (void)sem_init(&priv->txdmasem, 0, 0);
+
+  /* These semaphores are used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
+   sem_setprotocol(&priv->rxdmasem, SEM_PRIO_NONE);
+   sem_setprotocol(&priv->txdmasem, SEM_PRIO_NONE);
 #endif
 
   /* Enable SPI */

arch/arm/src/efm32/efm32_usbhost.c

@@ -52,6 +52,7 @@
 #include <nuttx/arch.h>
 #include <nuttx/kmalloc.h>
 #include <nuttx/clock.h>
+#include <nuttx/semaphore.h>
 #include <nuttx/usb/usb.h>
 #include <nuttx/usb/usbhost.h>
 #include <nuttx/usb/usbhost_devaddr.h>
@@ -5157,6 +5158,12 @@ static inline void efm32_sw_initialize(FAR struct efm32_usbhost_s *priv)
   sem_init(&priv->pscsem,  0, 0);
   sem_init(&priv->exclsem, 0, 1);
 
+  /* The pscsem semaphore is used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
+  sem_setprotocol(&priv->pscsem, SEM_PRIO_NONE);
+
   /* Initialize the driver state data */
 
   priv->smstate   = SMSTATE_DETACHED;
@@ -5172,8 +5179,15 @@ static inline void efm32_sw_initialize(FAR struct efm32_usbhost_s *priv)
   for (i = 0; i < EFM32_MAX_TX_FIFOS; i++)
     {
       FAR struct efm32_chan_s *chan = &priv->chan[i];
+
       chan->chidx = i;
+
+      /* The waitsem semaphore is used for signaling and, hence, should not
+       * have priority inheritance enabled.
+       */
+
       sem_init(&chan->waitsem,  0, 0);
+      sem_setprotocol(&chan->waitsem, SEM_PRIO_NONE);
     }
 }
 

arch/arm/src/imx1/imx_spi.c

@@ -50,6 +50,7 @@
 #include <nuttx/spi/spi.h>
 
 #include <nuttx/irq.h>
+#include <nuttx/semaphore.h>
 #include <arch/board/board.h>
 
 #include "up_internal.h"
@@ -1116,7 +1117,13 @@ FAR struct spi_dev_s *imx_spibus_initialize(int port)
   /* Initialize the state structure */
 
 #ifndef CONFIG_SPI_POLLWAIT
+  /* Initialize the semaphore that is used to wake up the waiting
+   * thread when the DMA transfer completes.  This semaphore is used for
+   * signaling and, hence, should not have priority inheritance enabled.
+   */
+
    sem_init(&priv->waitsem, 0, 0);
+   sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
 #endif
    sem_init(&priv->exclsem, 0, 1);
 

arch/arm/src/kinetis/kinetis_i2c.c

@@ -49,6 +49,7 @@
 
 #include <nuttx/arch.h>
 #include <nuttx/wdog.h>
+#include <nuttx/semaphore.h>
 #include <nuttx/i2c/i2c_master.h>
 
 #include <nuttx/irq.h>
@@ -1105,9 +1106,17 @@ struct i2c_master_s *kinetis_i2cbus_initialize(int port)
 
   leave_critical_section(flags);
 
+  /* Initialize semaphores */
+
   sem_init(&priv->mutex, 0, 1);
   sem_init(&priv->wait, 0, 0);
 
+  /* The wait semaphore is used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
+  sem_setprotocol(&priv->wait, SEM_PRIO_NONE);
+
   /* Allocate a watchdog timer */
 
   priv->timeout = wd_create();

arch/arm/src/kinetis/kinetis_sdhc.c

@@ -52,6 +52,7 @@
 #include <nuttx/arch.h>
 #include <nuttx/sdio.h>
 #include <nuttx/wqueue.h>
+#include <nuttx/semaphore.h>
 #include <nuttx/mmcsd.h>
 
 #include <nuttx/irq.h>
@@ -2774,8 +2775,18 @@ FAR struct sdio_dev_s *sdhc_initialize(int slotno)
   DEBUGASSERT(slotno == 0);
 
   /* Initialize the SDHC slot structure data structure */
+  /* Initialize semaphores */
 
   sem_init(&priv->waitsem, 0, 0);
+
+  /* The waitsem semaphore is used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
+  sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
+
+  /* Create a watchdog timer */
+
   priv->waitwdog = wd_create();
   DEBUGASSERT(priv->waitwdog);
 

arch/arm/src/kl/kl_spi.h

@@ -126,6 +126,11 @@ int kl_spi1cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
 #endif
 #endif
 
+#if defined(__cplusplus)
+}
+#endif
+#undef EXTERN
+
 #endif /* __ASSEMBLY__ */
 #endif /* CONFIG_KL_SPI0 || CONFIG_KL_SPI1 */
 #endif /* __ARCH_ARM_SRC_KL_KL_SPI_H */

arch/arm/src/lpc11xx/lpc11_i2c.c

@@ -59,6 +59,7 @@
 
 #include <nuttx/arch.h>
 #include <nuttx/wdog.h>
+#include <nuttx/semaphore.h>
 #include <nuttx/i2c/i2c_master.h>
 
 #include <nuttx/irq.h>
@@ -584,9 +585,17 @@ struct i2c_master_s *lpc11_i2cbus_initialize(int port)
 
   putreg32(I2C_CONSET_I2EN, priv->base + LPC11_I2C_CONSET_OFFSET);
 
+  /* Initialize semaphores */
+
   sem_init(&priv->mutex, 0, 1);
   sem_init(&priv->wait, 0, 0);
 
+  /* The wait semaphore is used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
+  sem_setprotocol(&priv->wait, SEM_PRIO_NONE);
+
   /* Allocate a watchdog timer */
 
   priv->timeout = wd_create();

arch/arm/src/lpc17xx/lpc17_i2c.c

@@ -59,6 +59,7 @@
 
 #include <nuttx/arch.h>
 #include <nuttx/wdog.h>
+#include <nuttx/semaphore.h>
 #include <nuttx/i2c/i2c_master.h>
 
 #include <nuttx/irq.h>
@@ -589,9 +590,17 @@ struct i2c_master_s *lpc17_i2cbus_initialize(int port)
 
   putreg32(I2C_CONSET_I2EN, priv->base + LPC17_I2C_CONSET_OFFSET);
 
+  /* Initialize semaphores */
+
   sem_init(&priv->mutex, 0, 1);
   sem_init(&priv->wait, 0, 0);
 
+  /* The wait semaphore is used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
+  sem_setprotocol(&priv->wait, SEM_PRIO_NONE);
+
   /* Allocate a watchdog timer */
 
   priv->timeout = wd_create();

arch/arm/src/lpc17xx/lpc17_sdcard.c

@@ -1,7 +1,7 @@
 /****************************************************************************
  * arch/arm/src/lpc17xx/lpc17_sdcard.c
  *
- *   Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2013-2014, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -52,6 +52,7 @@
 #include <nuttx/arch.h>
 #include <nuttx/sdio.h>
 #include <nuttx/wqueue.h>
+#include <nuttx/semaphore.h>
 #include <nuttx/mmcsd.h>
 
 #include <nuttx/irq.h>
@@ -2699,8 +2700,18 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
   putreg32(regval, LPC17_SYSCON_PCONP);
 
   /* Initialize the SD card slot structure */
+  /* Initialize semaphores */
 
   sem_init(&priv->waitsem, 0, 0);
+
+  /* The waitsem semaphore is used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
+  sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
+
+  /* Create a watchdog timer */
+
   priv->waitwdog = wd_create();
   DEBUGASSERT(priv->waitwdog);
 

arch/arm/src/lpc17xx/lpc17_usbhost.c

@@ -1,7 +1,7 @@
 /****************************************************************************
  * arch/arm/src/lpc17xx/lpc17_usbhost.c
  *
- *   Copyright (C) 2010-2012, 2014-2015 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2010-2012, 2014-2016 Gregory Nutt. All rights reserved.
  *   Authors: Rafael Noronha <rafael@pdsolucoes.com.br>
  *            Gregory Nutt <gnutt@nuttx.org>
  *
@@ -51,6 +51,7 @@
 #include <debug.h>
 
 #include <nuttx/arch.h>
+#include <nuttx/semaphore.h>
 #include <nuttx/usb/usb.h>
 #include <nuttx/usb/ohci.h>
 #include <nuttx/usb/usbhost.h>
@@ -2262,10 +2263,12 @@ static int lpc17_epalloc(struct usbhost_driver_s *drvr,
       uinfo("EP%d CTRL:%08x\n", epdesc->addr, ed->hw.ctrl);
 
       /* Initialize the semaphore that is used to wait for the endpoint
-       * WDH event.
+       * WDH event. The wdhsem semaphore is used for signaling and, hence,
+       * should not have priority inheritance enabled.
        */
 
       sem_init(&ed->wdhsem, 0, 0);
+      sem_setprotocol(&ed->wdhsem, SEM_PRIO_NONE);
 
       /* Link the common tail TD to the ED's TD list */
 
@@ -3305,7 +3308,9 @@ errout_with_sem:
 
 static int lpc17_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep)
 {
+#ifdef CONFIG_USBHOST_ASYNCH
   struct lpc17_usbhost_s *priv = (struct lpc17_usbhost_s *)drvr;
+#endif
   struct lpc17_ed_s *ed = (struct lpc17_ed_s *)ep;
   struct lpc17_gtd_s *td;
   struct lpc17_gtd_s *next;
@@ -3313,7 +3318,7 @@ static int lpc17_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep)
   uint32_t ctrl;
   irqstate_t flags;
 
-  DEBUGASSERT(priv != NULL && ed != NULL);
+  DEBUGASSERT(drvr != NULL && ed != NULL);
 
   /* These first steps must be atomic as possible */
 
@@ -3639,6 +3644,12 @@ struct usbhost_connection_s *lpc17_usbhost_initialize(int controller)
   sem_init(&priv->pscsem,  0, 0);
   sem_init(&priv->exclsem, 0, 1);
 
+  /* The pscsem semaphore is used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
+  sem_setprotocol(&priv->pscsem, SEM_PRIO_NONE);
+
 #ifndef CONFIG_USBHOST_INT_DISABLE
   priv->ininterval  = MAX_PERINTERVAL;
   priv->outinterval = MAX_PERINTERVAL;
@@ -3719,7 +3730,13 @@ struct usbhost_connection_s *lpc17_usbhost_initialize(int controller)
   memset((void *)HCCA,   0, sizeof(struct ohci_hcca_s));
   memset((void *)TDTAIL, 0, sizeof(struct ohci_gtd_s));
   memset((void *)EDCTRL, 0, sizeof(struct lpc17_ed_s));
+
+  /* The EDCTRL wdhsem semaphore is used for signaling and, hence, should
+   * not have priority inheritance enabled.
+   */
+
   sem_init(&EDCTRL->wdhsem, 0, 0);
+  sem_setprotocol(&EDCTRL->wdhsem, SEM_PRIO_NONE);
 
   /* Initialize user-configurable EDs */
 

arch/arm/src/lpc2378/lpc23xx_i2c.c

@@ -64,6 +64,7 @@
 
 #include <nuttx/arch.h>
 #include <nuttx/wdog.h>
+#include <nuttx/semaphore.h>
 #include <nuttx/i2c/i2c_master.h>
 
 #include <nuttx/irq.h>
@@ -600,9 +601,17 @@ struct i2c_master_s *lpc2378_i2cbus_initialize(int port)
 
   putreg32(I2C_CONSET_I2EN, priv->base + I2C_CONSET_OFFSET);
 
+  /* Initialize semaphores */
+
   sem_init(&priv->mutex, 0, 1);
   sem_init(&priv->wait, 0, 0);
 
+  /* The wait semaphore is used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
+  sem_setprotocol(&priv->wait, SEM_PRIO_NONE);
+
   /* Allocate a watchdog timer */
 
   priv->timeout = wd_create();

arch/arm/src/lpc31xx/lpc31_ehci.c

@@ -52,6 +52,7 @@
 #include <nuttx/arch.h>
 #include <nuttx/kmalloc.h>
 #include <nuttx/wqueue.h>
+#include <nuttx/semaphore.h>
 #include <nuttx/usb/usb.h>
 #include <nuttx/usb/usbhost.h>
 #include <nuttx/usb/ehci.h>
@@ -3931,7 +3932,13 @@ static int lpc31_epalloc(FAR struct usbhost_driver_s *drvr,
   epinfo->maxpacket = epdesc->mxpacketsize;
   epinfo->xfrtype   = epdesc->xfrtype;
   epinfo->speed     = hport->speed;
+
+  /* The iocsem semaphore is used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
   sem_init(&epinfo->iocsem, 0, 0);
+  sem_setprotocol(&epinfo->iocsem, SEM_PRIO_NONE);
 
   /* Success.. return an opaque reference to the endpoint information structure
    * instance
@@ -4916,6 +4923,12 @@ FAR struct usbhost_connection_s *lpc31_ehci_initialize(int controller)
   sem_init(&g_ehci.exclsem, 0, 1);
   sem_init(&g_ehci.pscsem,  0, 0);
 
+  /* The pscsem semaphore is used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
+  sem_setprotocol(&g_ehci.pscsem, SEM_PRIO_NONE);
+
   /* Initialize EP0 */
 
   sem_init(&g_ehci.ep0.iocsem, 0, 1);
@@ -4952,7 +4965,13 @@ FAR struct usbhost_connection_s *lpc31_ehci_initialize(int controller)
       rhport->ep0.xfrtype         = USB_EP_ATTR_XFER_CONTROL;
       rhport->ep0.speed           = USB_SPEED_FULL;
       rhport->ep0.maxpacket       = 8;
+
+      /* The port iocsem semaphore is used for signaling and, hence,
+       * should not have priority inheritance enabled.
+       */
+
       sem_init(&rhport->ep0.iocsem, 0, 0);
+      sem_setprotocol(&rhport->iocsem, SEM_PRIO_NONE);
 
       /* Initialize the public port representation */
 

arch/arm/src/lpc31xx/lpc31_i2c.c

@@ -51,6 +51,7 @@
 
 #include <nuttx/arch.h>
 #include <nuttx/wdog.h>
+#include <nuttx/semaphore.h>
 #include <nuttx/i2c/i2c_master.h>
 
 #include <nuttx/irq.h>
@@ -554,9 +555,17 @@ struct i2c_master_s *lpc31_i2cbus_initialize(int port)
   priv->rstid = (port == 0) ? RESETID_I2C0RST  : RESETID_I2C1RST;
   priv->irqid = (port == 0) ? LPC31_IRQ_I2C0   : LPC31_IRQ_I2C1;
 
+  /* Initialize semaphores */
+
   sem_init(&priv->mutex, 0, 1);
   sem_init(&priv->wait, 0, 0);
 
+  /* The wait semaphore is used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
+  sem_setprotocol(&priv->wait, SEM_PRIO_NONE);
+
   /* Enable I2C system clocks */
 
   lpc31_enableclock(priv->clkid);

arch/arm/src/lpc43xx/chip/lpc43_ethernet.h

@@ -653,15 +653,5 @@ struct eth_rxdesc_s
  * Public Functions
  ****************************************************************************************************/
 
-#undef EXTERN
-#if defined(__cplusplus)
-#define EXTERN extern "C"
-extern "C"
-{
-#else
-#define EXTERN extern
-#endif
-
 #endif /* __ASSEMBLY__ */
 #endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_ETHERNET_H */
-

arch/arm/src/lpc43xx/lpc43_ehci.c

@@ -51,6 +51,7 @@
 #include <nuttx/arch.h>
 #include <nuttx/kmalloc.h>
 #include <nuttx/wqueue.h>
+#include <nuttx/semaphore.h>
 #include <nuttx/usb/usb.h>
 #include <nuttx/usb/usbhost.h>
 #include <nuttx/usb/ehci.h>
@@ -3768,7 +3769,13 @@ static int lpc43_epalloc(FAR struct usbhost_driver_s *drvr,
   epinfo->maxpacket = epdesc->mxpacketsize;
   epinfo->xfrtype   = epdesc->xfrtype;
   epinfo->speed     = hport->speed;
+
+  /* The endpoint iocsem semaphore is used for signaling and, hence,
+   * should not have priority inheritance enabled.
+   */
+
   sem_init(&epinfo->iocsem, 0, 0);
+  sem_setprotocol(&epinfo->iocsem, SEM_PRIO_NONE);
 
   /* Success.. return an opaque reference to the endpoint information structure
    * instance
@@ -4747,6 +4754,12 @@ FAR struct usbhost_connection_s *lpc43_ehci_initialize(int controller)
   sem_init(&g_ehci.exclsem, 0, 1);
   sem_init(&g_ehci.pscsem,  0, 0);
 
+  /* The pscsem semaphore is used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
+  sem_setprotocol(&g_ehci.pscsem, SEM_PRIO_NONE);
+
   /* Initialize EP0 */
 
   sem_init(&g_ehci.ep0.iocsem, 0, 1);
@@ -4783,7 +4796,13 @@ FAR struct usbhost_connection_s *lpc43_ehci_initialize(int controller)
       rhport->ep0.xfrtype         = USB_EP_ATTR_XFER_CONTROL;
       rhport->ep0.speed           = USB_SPEED_FULL;
       rhport->ep0.maxpacket       = 8;
+
+      /* The EP0 iocsem semaphore is used for signaling and, hence, should
+       * not have priority inheritance enabled.
+       */
+
       sem_init(&rhport->ep0.iocsem, 0, 0);
+      sem_setprotocol(&rhport->ep0.iocsem, SEM_PRIO_NONE);
 
       /* Initialize the public port representation */
 

arch/arm/src/lpc43xx/lpc43_ethernet.h

@@ -55,7 +55,8 @@
 #undef EXTERN
 #if defined(__cplusplus)
 #define EXTERN extern "C"
-extern "C" {
+extern "C"
+{
 #else
 #define EXTERN extern
 #endif

arch/arm/src/lpc43xx/lpc43_i2c.c

@@ -62,6 +62,7 @@
 
 #include <nuttx/arch.h>
 #include <nuttx/wdog.h>
+#include <nuttx/semaphore.h>
 #include <nuttx/i2c/i2c_master.h>
 
 #include <nuttx/irq.h>
@@ -539,9 +540,17 @@ struct i2c_master_s *lpc43_i2cbus_initialize(int port)
 
   putreg32(I2C_CONSET_I2EN, priv->base + LPC43_I2C_CONSET_OFFSET);
 
+  /* Initialize semaphores */
+
   sem_init(&priv->mutex, 0, 1);
   sem_init(&priv->wait, 0, 0);
 
+  /* The wait semaphore is used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
+  sem_setprotocol(&priv->wait, SEM_PRIO_NONE);
+
   /* Allocate a watchdog timer */
 
   priv->timeout = wd_create();

arch/arm/src/sam34/sam_hsmci.c

@@ -1,7 +1,7 @@
 /****************************************************************************
  * arch/arm/src/sam34/sam_hsmci.c
  *
- *   Copyright (C) 2010, 2012-2014 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2010, 2012-2014, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -52,6 +52,7 @@
 #include <nuttx/clock.h>
 #include <nuttx/sdio.h>
 #include <nuttx/wqueue.h>
+#include <nuttx/semaphore.h>
 #include <nuttx/mmcsd.h>
 
 #include <nuttx/irq.h>
@@ -2668,8 +2669,18 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
   mcinfo("slotno: %d\n", slotno);
 
   /* Initialize the HSMCI slot structure */
+  /* Initialize semaphores */
 
   sem_init(&priv->waitsem, 0, 0);
+
+  /* The waitsem semaphore is used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
+  sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
+
+  /* Create a watchdog timer */
+
   priv->waitwdog = wd_create();
   DEBUGASSERT(priv->waitwdog);
 

arch/arm/src/sam34/sam_spi.c

@@ -56,6 +56,7 @@
 #include <nuttx/arch.h>
 #include <nuttx/wdog.h>
 #include <nuttx/clock.h>
+#include <nuttx/semaphore.h>
 #include <nuttx/spi/spi.h>
 
 #include "up_internal.h"
@@ -1882,10 +1883,12 @@ struct spi_dev_s *sam_spibus_initialize(int port)
 
 #ifdef CONFIG_SAM34_SPI_DMA
       /* Initialize the SPI semaphore that is used to wake up the waiting
-       * thread when the DMA transfer completes.
+       * thread when the DMA transfer completes.  This semaphore is used for
+       * signaling and, hence, should not have priority inheritance enabled.
        */
 
       sem_init(&spics->dmawait, 0, 0);
+      sem_setprotocol(&spics->dmawait, SEM_PRIO_NONE);
 
       /* Create a watchdog time to catch DMA timeouts */
 

arch/arm/src/sam34/sam_twi.c

@@ -56,6 +56,7 @@
 
 #include <nuttx/wdog.h>
 #include <nuttx/arch.h>
+#include <nuttx/semaphore.h>
 #include <nuttx/i2c/i2c_master.h>
 
 #include <nuttx/irq.h>
@@ -982,9 +983,17 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
 
   priv->dev.ops = &g_twiops;
 
+  /* Initialize semaphores */
+
   sem_init(&priv->exclsem, 0, 1);
   sem_init(&priv->waitsem, 0, 0);
 
+  /* The waitsem semaphore is used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
+  sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
+
   /* Allocate a watchdog timer */
 
   priv->timeout = wd_create();

arch/arm/src/sama5/sam_ehci.c

@@ -51,6 +51,7 @@
 #include <nuttx/arch.h>
 #include <nuttx/kmalloc.h>
 #include <nuttx/wqueue.h>
+#include <nuttx/semaphore.h>
 #include <nuttx/usb/usb.h>
 #include <nuttx/usb/usbhost.h>
 #include <nuttx/usb/ehci.h>
@@ -3752,7 +3753,13 @@ static int sam_epalloc(FAR struct usbhost_driver_s *drvr,
   epinfo->maxpacket = epdesc->mxpacketsize;
   epinfo->xfrtype   = epdesc->xfrtype;
   epinfo->speed     = hport->speed;
+
+  /* The endpoint iocsem semaphore is used for signaling and, hence,
+   * should not have priority inheritance enabled.
+   */
+
   sem_init(&epinfo->iocsem, 0, 0);
+  sem_setprotocol(&epinfo->iocsem, SEM_PRIO_NONE);
 
   /* Success.. return an opaque reference to the endpoint information structure
    * instance
@@ -4787,6 +4794,12 @@ FAR struct usbhost_connection_s *sam_ehci_initialize(int controller)
   sem_init(&g_ehci.exclsem, 0, 1);
   sem_init(&g_ehci.pscsem,  0, 0);
 
+  /* The pscsem semaphore is used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
+  sem_setprotocol(&g_ehci.pscsem, SEM_PRIO_NONE);
+
   /* Initialize EP0 */
 
   sem_init(&g_ehci.ep0.iocsem, 0, 1);
@@ -4823,7 +4836,13 @@ FAR struct usbhost_connection_s *sam_ehci_initialize(int controller)
       rhport->ep0.xfrtype         = USB_EP_ATTR_XFER_CONTROL;
       rhport->ep0.speed           = USB_SPEED_FULL;
       rhport->ep0.maxpacket       = 8;
+
+      /* The endpoint 0 iocsem semaphore is used for signaling and, hence,
+       * should not have priority inheritance enabled.
+       */
+
       sem_init(&rhport->ep0.iocsem, 0, 0);
+      sem_setprotocol(&rhport->ep0.iocsem, SEM_PRIO_NONE);
 
       /* Initialize the public port representation */
 

arch/arm/src/sama5/sam_hsmci.c

@@ -1,7 +1,7 @@
 /****************************************************************************
  * arch/arm/src/sama5/sam_hsmci.c
  *
- *   Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2013-2014, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -52,6 +52,7 @@
 #include <nuttx/wdog.h>
 #include <nuttx/sdio.h>
 #include <nuttx/wqueue.h>
+#include <nuttx/semaphore.h>
 #include <nuttx/mmcsd.h>
 
 #include <nuttx/irq.h>
@@ -3331,8 +3332,18 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
          priv, priv->base, priv->hsmci, dmac, pid);
 
   /* Initialize the HSMCI slot structure */
+  /* Initialize semaphores */
 
   sem_init(&priv->waitsem, 0, 0);
+
+  /* The waitsem semaphore is used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
+  sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
+
+  /* Create a watchdog timer */
+
   priv->waitwdog = wd_create();
   DEBUGASSERT(priv->waitwdog);
 

arch/arm/src/sama5/sam_nand.c

@@ -1,7 +1,7 @@
 /****************************************************************************
  * arch/arm/src/sama5/sam_nand.c
  *
- *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * References:
@@ -58,6 +58,7 @@
 #include <debug.h>
 
 #include <nuttx/arch.h>
+#include <nuttx/semaphore.h>
 #include <nuttx/fs/ioctl.h>
 #include <nuttx/mtd/mtd.h>
 #include <nuttx/mtd/nand.h>
@@ -2944,7 +2945,12 @@ struct mtd_dev_s *sam_nand_initialize(int cs)
   priv->cs             = cs;
 
 #ifdef CONFIG_SAMA5_NAND_DMA
+  /* The waitsem semaphore is used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
   sem_init(&priv->waitsem, 0, 0);
+  sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
 #endif
 
   /* Perform one-time, global NFC/PMECC initialization */
@@ -2956,8 +2962,14 @@ struct mtd_dev_s *sam_nand_initialize(int cs)
 #if NAND_NBANKS > 1
       sem_init(&g_nand.exclsem, 0, 1);
 #endif
+
 #ifdef CONFIG_SAMA5_NAND_HSMCINTERRUPTS
+      /* The waitsem semaphore is used for signaling and, hence, should not
+       * have priority inheritance enabled.
+       */
+
       sem_init(&g_nand.waitsem, 0, 0);
+      sem_setprotocol(&g_nand.waitsem, SEM_PRIO_NONE);
 #endif
 
       /* Enable the NAND FLASH Controller (The NFC is always used) */

arch/arm/src/sama5/sam_ohci.c

@@ -1,7 +1,7 @@
 /****************************************************************************
  * arch/arm/src/sama5/sam_ohci.c
  *
- *   Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2013, 2015-2016 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -51,6 +51,7 @@
 #include <nuttx/arch.h>
 #include <nuttx/kmalloc.h>
 #include <nuttx/wqueue.h>
+#include <nuttx/semaphore.h>
 #include <nuttx/usb/usb.h>
 #include <nuttx/usb/ohci.h>
 #include <nuttx/usb/usbhost.h>
@@ -2664,6 +2665,12 @@ static int sam_epalloc(struct usbhost_driver_s *drvr,
 
   sem_init(&eplist->wdhsem, 0, 0);
 
+  /* The wdhsem semaphore is used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
+  sem_setprotocol(&eplist->wdhsem, SEM_PRIO_NONE);
+
   /* We must have exclusive access to the ED pool, the bulk list, the periodic list
    * and the interrupt table.
    */
@@ -3903,6 +3910,12 @@ struct usbhost_connection_s *sam_ohci_initialize(int controller)
   sem_init(&g_ohci.pscsem,  0, 0);
   sem_init(&g_ohci.exclsem, 0, 1);
 
+  /* The pscsem semaphore is used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
+  sem_setprotocol(&g_ohci.pscsem, SEM_PRIO_NONE);
+
 #ifndef CONFIG_USBHOST_INT_DISABLE
   g_ohci.ininterval  = MAX_PERINTERVAL;
   g_ohci.outinterval = MAX_PERINTERVAL;

arch/arm/src/sama5/sam_spi.c

@@ -60,6 +60,7 @@
 #include <nuttx/arch.h>
 #include <nuttx/wdog.h>
 #include <nuttx/clock.h>
+#include <nuttx/semaphore.h>
 #include <nuttx/spi/spi.h>
 
 #include "up_internal.h"
@@ -1810,10 +1811,12 @@ struct spi_dev_s *sam_spibus_initialize(int port)
 
 #ifdef CONFIG_SAMA5_SPI_DMA
       /* Initialize the SPI semaphore that is used to wake up the waiting
-       * thread when the DMA transfer completes.
+       * thread when the DMA transfer completes.  This semaphore is used for
+       * signaling and, hence, should not have priority inheritance enabled.
        */
 
       sem_init(&spics->dmawait, 0, 0);
+      sem_setprotocol(&spics->dmawait, SEM_PRIO_NONE);
 
       /* Create a watchdog time to catch DMA timeouts */
 

arch/arm/src/sama5/sam_trng.c

@@ -52,6 +52,7 @@
 
 #include <nuttx/irq.h>
 #include <nuttx/arch.h>
+#include <nuttx/semaphore.h>
 #include <nuttx/fs/fs.h>
 #include <nuttx/drivers/drivers.h>
 
@@ -352,9 +353,18 @@ static int sam_rng_initialize(void)
   /* Initialize the device structure */
 
   memset(&g_trngdev, 0, sizeof(struct trng_dev_s));
+
+  /* Initialize semphores */
+
   sem_init(&g_trngdev.exclsem, 0, 1);
   sem_init(&g_trngdev.waitsem, 0, 0);
 
+  /* The waitsem semaphore is used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
+  sem_setprotocol(&g_trngdev.waitsem, SEM_PRIO_NONE);
+
   /* Enable clocking to the TRNG */
 
   sam_trng_enableclk();

arch/arm/src/sama5/sam_tsd.c

@@ -66,6 +66,7 @@
 #include <nuttx/wdog.h>
 #include <nuttx/wqueue.h>
 #include <nuttx/clock.h>
+#include <nuttx/semaphore.h>
 #include <nuttx/input/touchscreen.h>
 
 #include <arch/board/board.h>
@@ -1669,7 +1670,12 @@ int sam_tsd_register(struct sam_adc_s *adc, int minor)
   priv->threshx = INVALID_THRESHOLD; /* Initialize thresholding logic */
   priv->threshy = INVALID_THRESHOLD; /* Initialize thresholding logic */
 
-  sem_init(&priv->waitsem, 0, 0);    /* Initialize pen event wait semaphore */
+  /* Initialize pen event wait semaphore.  This semaphore is used for
+   * signaling and, hence, should not have priority inheritance enabled.
+   */
+
+  sem_init(&priv->waitsem, 0, 0);
+  sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
 
   /* Register the device as an input device */
 

arch/arm/src/sama5/sam_twi.c

@@ -57,6 +57,7 @@
 #include <nuttx/arch.h>
 #include <nuttx/wdog.h>
 #include <nuttx/clock.h>
+#include <nuttx/semaphore.h>
 #include <nuttx/i2c/i2c_master.h>
 
 #include <nuttx/irq.h>
@@ -1306,9 +1307,17 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
 
   priv->dev.ops = &g_twiops;
 
+  /* Initialize semaphores */
+
   (void)sem_init(&priv->exclsem, 0, 1);
   (void)sem_init(&priv->waitsem, 0, 0);
 
+  /* The waitsem semaphore is used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
+  sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
+
   /* Perform repeatable TWI hardware initialization */
 
   twi_hw_initialize(priv, frequency);

arch/arm/src/samv7/sam_hsmci.c

@@ -1,7 +1,7 @@
 /****************************************************************************
  * arch/arm/src/samv7/sam_hsmci.c
  *
- *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -52,6 +52,7 @@
 #include <nuttx/wdog.h>
 #include <nuttx/sdio.h>
 #include <nuttx/wqueue.h>
+#include <nuttx/semaphore.h>
 #include <nuttx/mmcsd.h>
 
 #include <nuttx/irq.h>
@@ -3352,8 +3353,18 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
         priv, priv->base, priv->hsmci, pid);
 
   /* Initialize the HSMCI slot structure */
+  /* Initialize semaphores */
 
   sem_init(&priv->waitsem, 0, 0);
+
+  /* The waitsem semaphore is used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
+  sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
+
+  /* Create a watchdog timer */
+
   priv->waitwdog = wd_create();
   DEBUGASSERT(priv->waitwdog);
 

arch/arm/src/samv7/sam_qspi.c

@@ -55,6 +55,7 @@
 #include <nuttx/wdog.h>
 #include <nuttx/clock.h>
 #include <nuttx/kmalloc.h>
+#include <nuttx/semaphore.h>
 #include <nuttx/spi/qspi.h>
 
 #include "up_internal.h"
@@ -1790,10 +1791,12 @@ struct qspi_dev_s *sam_qspi_initialize(int intf)
         }
 
       /* Initialize the QSPI semaphore that is used to wake up the waiting
-       * thread when the DMA transfer completes.
+       * thread when the DMA transfer completes.  This semaphore is used for
+       * signaling and, hence, should not have priority inheritance enabled.
        */
 
       sem_init(&priv->dmawait, 0, 0);
+      sem_setprotocol(&priv->dmawait, SEM_PRIO_NONE);
 
       /* Create a watchdog time to catch DMA timeouts */
 

arch/arm/src/samv7/sam_spi.c

@@ -56,6 +56,7 @@
 #include <nuttx/arch.h>
 #include <nuttx/wdog.h>
 #include <nuttx/clock.h>
+#include <nuttx/semaphore.h>
 #include <nuttx/spi/spi.h>
 
 #include "up_internal.h"
@@ -626,7 +627,7 @@ static inline uint32_t spi_cs2pcs(struct sam_spics_s *spics)
 #ifndef CONFIG_SAMV7_SPI_CS_DECODING
   return ((uint32_t)1 << (spics->cs)) - 1;
 #else
-  return spics->cs;
+  return spics->cs - 1;
 #endif
 }
 
@@ -2164,10 +2165,12 @@ FAR struct spi_dev_s *sam_spibus_initialize(int port)
 
 #ifdef CONFIG_SAMV7_SPI_DMA
       /* Initialize the SPI semaphore that is used to wake up the waiting
-       * thread when the DMA transfer completes.
+       * thread when the DMA transfer completes.  This semaphore is used for
+       * signaling and, hence, should not have priority inheritance enabled.
        */
 
       sem_init(&spics->dmawait, 0, 0);
+      sem_setprotocol(&spics->dmawait, SEM_PRIO_NONE);
 
       /* Create a watchdog time to catch DMA timeouts */
 

arch/arm/src/samv7/sam_trng.c

@@ -53,6 +53,7 @@
 
 #include <nuttx/irq.h>
 #include <nuttx/arch.h>
+#include <nuttx/semaphore.h>
 #include <nuttx/fs/fs.h>
 #include <nuttx/drivers/drivers.h>
 
@@ -353,9 +354,18 @@ static int sam_rng_initialize(void)
   /* Initialize the device structure */
 
   memset(&g_trngdev, 0, sizeof(struct trng_dev_s));
+
+  /* Initialize semaphores */
+
   sem_init(&g_trngdev.exclsem, 0, 1);
   sem_init(&g_trngdev.waitsem, 0, 0);
 
+  /* The waitsem semaphore is used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
+  sem_setprotocol(&g_trngdev.waitsem, SEM_PRIO_NONE);
+
   /* Enable clocking to the TRNG */
 
   sam_trng_enableclk();

arch/arm/src/samv7/sam_twihs.c

@@ -57,6 +57,7 @@
 #include <nuttx/arch.h>
 #include <nuttx/wdog.h>
 #include <nuttx/clock.h>
+#include <nuttx/semaphore.h>
 #include <nuttx/i2c/i2c_master.h>
 
 #include <nuttx/irq.h>
@@ -1454,9 +1455,17 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
 
       priv->dev.ops = &g_twiops;
 
+      /* Initialize semaphores */
+
       (void)sem_init(&priv->exclsem, 0, 1);
       (void)sem_init(&priv->waitsem, 0, 0);
 
+      /* The waitsem semaphore is used for signaling and, hence, should not
+       * have priority inheritance enabled.
+       */
+
+      sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
+
       /* Perform repeatable TWIHS hardware initialization */
 
       twi_hw_initialize(priv, frequency);

arch/arm/src/samv7/sam_usbdevhs.c

@@ -3333,6 +3333,17 @@ static void sam_ep_reset(struct sam_usbdev_s *priv, uint8_t epno)
 
   sam_putreg(USBHS_DEVINT_PEP(epno), SAM_USBHS_DEVIDR);
 
+  /* Clear all pending interrupts */
+
+  sam_putreg(USBHS_DEVEPTICR_ALLINTS, SAM_USBHS_DEVEPTICR(epno));
+
+  /* Set DMA control register to a defined state */
+
+  if ((SAM_EPSET_DMA & SAM_EP_BIT(epno)) != 0)
+    {
+      sam_putreg(0, SAM_USBHS_DEVDMACTRL(epno));
+    }
+
   /* Cancel any queued requests.  Since they are cancelled with status
    * -ESHUTDOWN, then will not be requeued until the configuration is reset.
    * NOTE:  This should not be necessary... the CLASS_DISCONNECT above

arch/arm/src/stm32/chip/stm32_tim.h

@@ -31,6 +31,10 @@
  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  *
+ * This the lower half driver for PWM and the STM32 F1 to F4 family MCUs
+ * Athough this driver does make the difference between 16/32-bit timers,
+ * it does manage all of them as 16-bit. This will have to be improved.
+ *
  ****************************************************************************************************/
 
 #ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_TIM_H
@@ -824,7 +828,9 @@
 #define ATIM_CCER_CC4E            (1 << 12) /* Bit 12: Capture/Compare 4 output enable */
 #define ATIM_CCER_CC4P            (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity */
 
-#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX)
+#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
+    defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX) || \
+    defined(CONFIG_STM32_STM32L15XX)
 #  define ATIM_CCER_CC4NP         (1 << 15) /* Bit 15: Capture/Compare 4 Complementary output polarity */
 #elif defined(CONFIG_STM32_STM32F30XX)
 #  define ATIM_CCER_CC4NP         (1 << 15) /* Bit 15: Capture/Compare 4 Complementary output polarity */

arch/arm/src/stm32/stm32_1wire.c

@@ -56,6 +56,7 @@
 #include <nuttx/irq.h>
 #include <nuttx/kmalloc.h>
 #include <nuttx/clock.h>
+#include <nuttx/semaphore.h>
 #include <nuttx/drivers/1wire.h>
 
 #include <arch/board/board.h>
@@ -744,6 +745,12 @@ static inline void stm32_1wire_sem_init(FAR struct stm32_1wire_priv_s *priv)
 {
   sem_init(&priv->sem_excl, 0, 1);
   sem_init(&priv->sem_isr, 0, 0);
+
+  /* The sem_isr semaphore is used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
+  sem_setprotocol(&priv->sem_isr, SEM_PRIO_NONE);
 }
 
 /****************************************************************************

arch/arm/src/stm32/stm32_adc.c

@@ -226,7 +226,7 @@
                                (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP8_SHIFT) | \
                                (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP9_SHIFT))
 #elif defined(CONFIG_STM32_STM32F30XX)
-#  ifdef ADC_HAVE_DMA || (ADC_MAX_SAMPLES == 1)
+#  if defined(ADC_HAVE_DMA) || (ADC_MAX_SAMPLES == 1)
 #    define ADC_SMPR_DEFAULT    ADC_SMPR_61p5
 #  else /* Slow down sampling frequency */
 #    define ADC_SMPR_DEFAULT    ADC_SMPR_601p5
@@ -2203,6 +2203,7 @@ static void adc_shutdown(FAR struct adc_dev_s *dev)
 static void adc_rxint(FAR struct adc_dev_s *dev, bool enable)
 {
   FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
+  uint32_t regval;
 
   ainfo("intf: %d enable: %d\n", priv->intf, enable ? 1 : 0);
 
@@ -2212,8 +2213,15 @@ static void adc_rxint(FAR struct adc_dev_s *dev, bool enable)
        * end-of-conversion ADC.
        */
 
-      adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0,
+      regval = ADC_IER_ALLINTS;
-                    priv->hasdma ? ADC_IER_AWD | ADC_ISR_OVR : ADC_IER_ALLINTS);
+#ifdef ADC_HAVE_DMA
+      if (priv->hasdma)
+        {
+          regval &= ~(ADC_IER_EOC | ADC_IER_JEOC);
+        }
+#endif
+
+      adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, regval);
     }
   else
     {
@@ -2803,7 +2811,7 @@ static int adc_interrupt(FAR struct adc_dev_s *dev)
 
   /* by MR regval &= ~pending; */
   /* by MR adc_putreg(priv, STM32_ADC_ISR_OFFSET, regval);
- 
+
   adc_putreg(priv, STM32_ADC_ISR_OFFSET, pending); */
   return OK;
 }

arch/arm/src/stm32/stm32_dma2d.c

@@ -49,8 +49,9 @@
 #include <semaphore.h>
 
 #include <nuttx/irq.h>
-#include <nuttx/video/fb.h>
 #include <nuttx/kmalloc.h>
+#include <nuttx/semaphore.h>
+#include <nuttx/video/fb.h>
 
 #include <arch/chip/dma2d.h>
 #include <arch/board/board.h>
@@ -2167,9 +2168,13 @@ int up_dma2dinitialize(void)
 
       sem_init(&g_lock, 0, 1);
 
-      /* Initialize the semaphore for interrupt handling */
+      /* Initialize the semaphore for interrupt handling.  This waitsem
+       * semaphore is used for signaling and, hence, should not have
+       * priority inheritance enabled.
+       */
 
       sem_init(g_interrupt.sem, 0, 0);
+      sem_setprotocol(g_interrupt.sem, SEM_PRIO_NONE);
 
 #ifdef CONFIG_STM32_DMA2D_L8
       /* Enable dma2d transfer and clut loading interrupts only */

arch/arm/src/stm32/stm32_i2c.c

@@ -84,8 +84,9 @@
 
 #include <nuttx/arch.h>
 #include <nuttx/irq.h>
-#include <nuttx/i2c/i2c_master.h>
 #include <nuttx/clock.h>
+#include <nuttx/semaphore.h>
+#include <nuttx/i2c/i2c_master.h>
 
 #include <arch/board/board.h>
 
@@ -784,8 +785,14 @@ static inline void stm32_i2c_sem_post(struct stm32_i2c_priv_s *priv)
 static inline void stm32_i2c_sem_init(FAR struct stm32_i2c_priv_s *priv)
 {
   sem_init(&priv->sem_excl, 0, 1);
+
 #ifndef CONFIG_I2C_POLLED
+  /* This semaphore is used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
   sem_init(&priv->sem_isr, 0, 0);
+  sem_setprotocol(&priv->sem_isr, SEM_PRIO_NONE);
 #endif
 }
 

arch/arm/src/stm32/stm32_i2c_alt.c

@@ -91,8 +91,9 @@
 
 #include <nuttx/arch.h>
 #include <nuttx/irq.h>
-#include <nuttx/i2c/i2c_master.h>
 #include <nuttx/clock.h>
+#include <nuttx/semaphore.h>
+#include <nuttx/i2c/i2c_master.h>
 
 #include <arch/board/board.h>
 
@@ -792,8 +793,14 @@ static inline void stm32_i2c_sem_post(FAR struct stm32_i2c_priv_s *priv)
 static inline void stm32_i2c_sem_init(FAR struct stm32_i2c_priv_s *priv)
 {
   sem_init(&priv->sem_excl, 0, 1);
+
 #ifndef CONFIG_I2C_POLLED
+  /* This semaphore is used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
   sem_init(&priv->sem_isr, 0, 0);
+  sem_setprotocol(&priv->sem_isr, SEM_PRIO_NONE);
 #endif
 }
 

arch/arm/src/stm32/stm32_ltdc.c

@@ -49,8 +49,9 @@
 #include <debug.h>
 
 #include <nuttx/irq.h>
-#include <nuttx/video/fb.h>
 #include <nuttx/kmalloc.h>
+#include <nuttx/semaphore.h>
+#include <nuttx/video/fb.h>
 
 #include <arch/chip/ltdc.h>
 #include <arch/chip/dma2d.h>
@@ -1287,9 +1288,13 @@ static void stm32_global_configure(void)
 
   sem_init(&g_lock, 0, 1);
 
-  /* Initialize the semaphore for interrupt handling */
+  /* Initialize the semaphore for interrupt handling.  This waitsem
+   * semaphore is used for signaling and, hence, should not have priority
+   * inheritance enabled.
+   */
 
   sem_init(g_interrupt.sem, 0, 0);
+  sem_setprotocol(g_interrupt.sem, SEM_PRIO_NONE);
 
   /* Attach LTDC interrupt vector */
 

arch/arm/src/stm32/stm32_otgfshost.c

@@ -52,6 +52,7 @@
 #include <nuttx/arch.h>
 #include <nuttx/kmalloc.h>
 #include <nuttx/clock.h>
+#include <nuttx/semaphore.h>
 #include <nuttx/usb/usb.h>
 #include <nuttx/usb/usbhost.h>
 #include <nuttx/usb/usbhost_devaddr.h>
@@ -5091,6 +5092,12 @@ static inline void stm32_sw_initialize(FAR struct stm32_usbhost_s *priv)
   sem_init(&priv->pscsem,  0, 0);
   sem_init(&priv->exclsem, 0, 1);
 
+  /* The pscsem semaphore is used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
+  sem_setprotocol(&priv->pscsem, SEM_PRIO_NONE);
+
   /* Initialize the driver state data */
 
   priv->smstate   = SMSTATE_DETACHED;
@@ -5106,8 +5113,15 @@ static inline void stm32_sw_initialize(FAR struct stm32_usbhost_s *priv)
   for (i = 0; i < STM32_MAX_TX_FIFOS; i++)
     {
       FAR struct stm32_chan_s *chan = &priv->chan[i];
+
       chan->chidx = i;
+
+      /* The waitsem semaphore is used for signaling and, hence, should not
+       * have priority inheritance enabled.
+       */
+
       sem_init(&chan->waitsem,  0, 0);
+      sem_setprotocol(&chan->waitsem, SEM_PRIO_NONE);
     }
 }
 

arch/arm/src/stm32/stm32_otghshost.c

@@ -52,6 +52,7 @@
 #include <nuttx/arch.h>
 #include <nuttx/kmalloc.h>
 #include <nuttx/clock.h>
+#include <nuttx/semaphore.h>
 #include <nuttx/usb/usb.h>
 #include <nuttx/usb/usbhost.h>
 #include <nuttx/usb/usbhost_devaddr.h>
@@ -5091,6 +5092,12 @@ static inline void stm32_sw_initialize(FAR struct stm32_usbhost_s *priv)
   sem_init(&priv->pscsem,  0, 0);
   sem_init(&priv->exclsem, 0, 1);
 
+  /* The pscsem semaphore is used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
+ sem_setprotocol(&priv->pscsem, SEM_PRIO_NONE);
+
   /* Initialize the driver state data */
 
   priv->smstate   = SMSTATE_DETACHED;
@@ -5106,8 +5113,15 @@ static inline void stm32_sw_initialize(FAR struct stm32_usbhost_s *priv)
   for (i = 0; i < STM32_MAX_TX_FIFOS; i++)
     {
       FAR struct stm32_chan_s *chan = &priv->chan[i];
+
       chan->chidx = i;
+
+      /* The waitsem semaphore is used for signaling and, hence, should not
+       * have priority inheritance enabled.
+       */
+
       sem_init(&chan->waitsem,  0, 0);
+      sem_setprotocol(&chan->waitsem, SEM_PRIO_NONE);
     }
 }
 

arch/arm/src/stm32/stm32_pwm.c

@@ -114,6 +114,159 @@
 #define TIMTYPE_TIM16      TIMTYPE_COUNTUP16
 #define TIMTYPE_TIM17      TIMTYPE_COUNTUP16
 
+/* Timer clock source, RCC EN offset, enable bit,
+ * RCC RST offset, reset bit to use
+ */
+
+#if defined(CONFIG_STM32_STM32F37XX)
+#  define TIMCLK_TIM2      STM32_APB1_TIM2_CLKIN
+#  define TIMRCCEN_TIM2    STM32_RCC_APB1ENR
+#  define TIMEN_TIM2       RCC_APB1ENR_TIM2EN
+#  define TIMRCCRST_TIM2   STM32_RCC_APB1RSTR
+#  define TIMRST_TIM2      RCC_APB1RSTR_TIM2RST
+#  define TIMCLK_TIM3      STM32_APB1_TIM3_CLKIN
+#  define TIMRCCEN_TIM3    STM32_RCC_APB1ENR
+#  define TIMEN_TIM3       RCC_APB1ENR_TIM3EN
+#  define TIMRCCRST_TIM3   STM32_RCC_APB1RSTR
+#  define TIMRST_TIM3      RCC_APB1RSTR_TIM3RST
+#  define TIMCLK_TIM4      STM32_APB1_TIM4_CLKIN
+#  define TIMRCCEN_TIM4    STM32_RCC_APB1ENR
+#  define TIMEN_TIM4       RCC_APB1ENR_TIM4EN
+#  define TIMRCCRST_TIM4   STM32_RCC_APB1RSTR
+#  define TIMRST_TIM4      RCC_APB1RSTR_TIM4RST
+#  define TIMCLK_TIM5      STM32_APB1_TIM5_CLKIN
+#  define TIMRCCEN_TIM5    STM32_RCC_APB1ENR
+#  define TIMEN_TIM5       RCC_APB1ENR_TIM5EN
+#  define TIMRCCRST_TIM5   STM32_RCC_APB1RSTR
+#  define TIMRST_TIM5      RCC_APB1RSTR_TIM5RST
+#  define TIMCLK_TIM6      STM32_APB1_TIM6_CLKIN
+#  define TIMRCCEN_TIM6    STM32_RCC_APB1ENR
+#  define TIMEN_TIM6       RCC_APB1ENR_TIM6EN
+#  define TIMRCCRST_TIM6   STM32_RCC_APB1RSTR
+#  define TIMRST_TIM6      RCC_APB1RSTR_TIM6RST
+#  define TIMCLK_TIM7      STM32_APB1_TIM7_CLKIN
+#  define TIMRCCEN_TIM7    STM32_RCC_APB1ENR
+#  define TIMEN_TIM7       RCC_APB1ENR_TIM7EN
+#  define TIMRCCRST_TIM7   STM32_RCC_APB1RSTR
+#  define TIMRST_TIM7      RCC_APB1RSTR_TIM7RST
+#  define TIMCLK_TIM12     STM32_APB1_TIM12_CLKIN
+#  define TIMRCCEN_TIM12   STM32_RCC_APB1ENR
+#  define TIMEN_TIM12      RCC_APB1ENR_TIM12EN
+#  define TIMRCCRST_TIM12  STM32_RCC_APB1RSTR
+#  define TIMRST_TIM12     RCC_APB1RSTR_TIM12RST
+#  define TIMCLK_TIM13     STM32_APB1_TIM13_CLKIN
+#  define TIMRCCEN_TIM13   STM32_RCC_APB1ENR
+#  define TIMEN_TIM13      RCC_APB1ENR_TIM13EN
+#  define TIMRCCRST_TIM13  STM32_RCC_APB1RSTR
+#  define TIMRST_TIM13     RCC_APB1RSTR_TIM13RST
+#  define TIMCLK_TIM14     STM32_APB1_TIM14_CLKIN
+#  define TIMRCCEN_TIM14   STM32_RCC_APB1ENR
+#  define TIMEN_TIM14      RCC_APB1ENR_TIM14EN
+#  define TIMRCCRST_TIM14  STM32_RCC_APB1RSTR
+#  define TIMRST_TIM14     RCC_APB1RSTR_TIM14RST
+#  define TIMCLK_TIM15     STM32_APB2_TIM15_CLKIN
+#  define TIMRCCEN_TIM15   STM32_RCC_APB2ENR
+#  define TIMEN_TIM15      RCC_APB2ENR_TIM15EN
+#  define TIMRCCRST_TIM15  STM32_RCC_APB2RSTR
+#  define TIMRST_TIM15     RCC_APB2RSTR_TIM15RST
+#  define TIMCLK_TIM16     STM32_APB2_TIM16_CLKIN
+#  define TIMRCCEN_TIM16   STM32_RCC_APB2ENR
+#  define TIMEN_TIM16      RCC_APB2ENR_TIM16EN
+#  define TIMRCCRST_TIM16  STM32_RCC_APB2RSTR
+#  define TIMRST_TIM16     RCC_APB2RSTR_TIM16RST
+#  define TIMCLK_TIM17     STM32_APB2_TIM17_CLKIN
+#  define TIMRCCEN_TIM17   STM32_RCC_APB2ENR
+#  define TIMEN_TIM17      RCC_APB2ENR_TIM17EN
+#  define TIMRCCRST_TIM17  STM32_RCC_APB2RSTR
+#  define TIMRST_TIM17     RCC_APB2RSTR_TIM17RST
+#  define TIMCLK_TIM18     STM32_APB1_TIM18_CLKIN
+#  define TIMRCCEN_TIM18   STM32_RCC_APB1ENR
+#  define TIMEN_TIM18      RCC_APB1ENR_TIM18EN
+#  define TIMRCCRST_TIM18  STM32_RCC_APB1RSTR
+#  define TIMRST_TIM18     RCC_APB1RSTR_TIM18RST
+#  define TIMCLK_TIM19     STM32_APB2_TIM19_CLKIN
+#  define TIMRCCEN_TIM19   STM32_RCC_APB2ENR
+#  define TIMEN_TIM19      RCC_APB2ENR_TIM19EN
+#  define TIMRCCRST_TIM19  STM32_RCC_APB2RSTR
+#  define TIMRST_TIM19     RCC_APB2RSTR_TIM19RST
+#else
+#  define TIMCLK_TIM1      STM32_APB2_TIM1_CLKIN
+#  define TIMRCCEN_TIM1    STM32_RCC_APB2ENR
+#  define TIMEN_TIM1       RCC_APB2ENR_TIM1EN
+#  define TIMRCCRST_TIM1   STM32_RCC_APB2RSTR
+#  define TIMRST_TIM1      RCC_APB2RSTR_TIM1RST
+#  define TIMCLK_TIM2      STM32_APB1_TIM2_CLKIN
+#  define TIMRCCEN_TIM2    STM32_RCC_APB1ENR
+#  define TIMEN_TIM2       RCC_APB1ENR_TIM2EN
+#  define TIMRCCRST_TIM2   STM32_RCC_APB1RSTR
+#  define TIMRST_TIM2      RCC_APB1RSTR_TIM2RST
+#  define TIMCLK_TIM3      STM32_APB1_TIM3_CLKIN
+#  define TIMRCCEN_TIM3    STM32_RCC_APB1ENR
+#  define TIMEN_TIM3       RCC_APB1ENR_TIM3EN
+#  define TIMRCCRST_TIM3   STM32_RCC_APB1RSTR
+#  define TIMRST_TIM3      RCC_APB1RSTR_TIM3RST
+#  define TIMCLK_TIM4      STM32_APB1_TIM4_CLKIN
+#  define TIMRCCEN_TIM4    STM32_RCC_APB1ENR
+#  define TIMEN_TIM4       RCC_APB1ENR_TIM4EN
+#  define TIMRCCRST_TIM4   STM32_RCC_APB1RSTR
+#  define TIMRST_TIM4      RCC_APB1RSTR_TIM4RST
+#  define TIMCLK_TIM5      STM32_APB1_TIM5_CLKIN
+#  define TIMRCCEN_TIM5    STM32_RCC_APB1ENR
+#  define TIMEN_TIM5       RCC_APB1ENR_TIM5EN
+#  define TIMRCCRST_TIM5   STM32_RCC_APB1RSTR
+#  define TIMRST_TIM5      RCC_APB1RSTR_TIM5RST
+#  define TIMCLK_TIM8      STM32_APB2_TIM8_CLKIN
+#  define TIMRCCEN_TIM8    STM32_RCC_APB2ENR
+#  define TIMEN_TIM8       RCC_APB2ENR_TIM8EN
+#  define TIMRCCRST_TIM8   STM32_RCC_APB2RSTR
+#  define TIMRST_TIM8      RCC_APB2RSTR_TIM8RST
+#  define TIMCLK_TIM9      STM32_APB2_TIM9_CLKIN
+#  define TIMRCCEN_TIM9    STM32_RCC_APB2ENR
+#  define TIMEN_TIM9       RCC_APB2ENR_TIM9EN
+#  define TIMRCCRST_TIM9   STM32_RCC_APB2RSTR
+#  define TIMRST_TIM9      RCC_APB2RSTR_TIM9RST
+#  define TIMCLK_TIM10     STM32_APB2_TIM10_CLKIN
+#  define TIMRCCEN_TIM10   STM32_RCC_APB2ENR
+#  define TIMEN_TIM10      RCC_APB2ENR_TIM10EN
+#  define TIMRCCRST_TIM10  STM32_RCC_APB2RSTR
+#  define TIMRST_TIM10     RCC_APB2RSTR_TIM10RST
+#  define TIMCLK_TIM11     STM32_APB2_TIM11_CLKIN
+#  define TIMRCCEN_TIM11   STM32_RCC_APB2ENR
+#  define TIMEN_TIM11      RCC_APB2ENR_TIM11EN
+#  define TIMRCCRST_TIM11  STM32_RCC_APB2RSTR
+#  define TIMRST_TIM11     RCC_APB2RSTR_TIM11RST
+#  define TIMCLK_TIM12     STM32_APB1_TIM12_CLKIN
+#  define TIMRCCEN_TIM12   STM32_RCC_APB1ENR
+#  define TIMEN_TIM12      RCC_APB1ENR_TIM12EN
+#  define TIMRCCRST_TIM12  STM32_RCC_APB1RSTR
+#  define TIMRST_TIM12     RCC_APB1RSTR_TIM12RST
+#  define TIMCLK_TIM13     STM32_APB1_TIM13_CLKIN
+#  define TIMRCCEN_TIM13   STM32_RCC_APB1ENR
+#  define TIMEN_TIM13      RCC_APB1ENR_TIM13EN
+#  define TIMRCCRST_TIM13  STM32_RCC_APB1RSTR
+#  define TIMRST_TIM13     RCC_APB1RSTR_TIM13RST
+#  define TIMCLK_TIM14     STM32_APB1_TIM14_CLKIN
+#  define TIMRCCEN_TIM14   STM32_RCC_APB1ENR
+#  define TIMEN_TIM14      RCC_APB1ENR_TIM14EN
+#  define TIMRCCRST_TIM14  STM32_RCC_APB1RSTR
+#  define TIMRST_TIM14     RCC_APB1RSTR_TIM14RST
+#  define TIMCLK_TIM15     STM32_APB1_TIM15_CLKIN
+#  define TIMRCCEN_TIM15   STM32_RCC_APB1ENR
+#  define TIMEN_TIM15      RCC_APB1ENR_TIM15EN
+#  define TIMRCCRST_TIM15  STM32_RCC_APB1RSTR
+#  define TIMRST_TIM15     RCC_APB1RSTR_TIM15RST
+#  define TIMCLK_TIM16     STM32_APB1_TIM16_CLKIN
+#  define TIMRCCEN_TIM16   STM32_RCC_APB1ENR
+#  define TIMEN_TIM16      RCC_APB1ENR_TIM16EN
+#  define TIMRCCRST_TIM16  STM32_RCC_APB1RSTR
+#  define TIMRST_TIM16     RCC_APB1RSTR_TIM16RST
+#  define TIMCLK_TIM17     STM32_APB1_TIM17_CLKIN
+#  define TIMRCCEN_TIM17   STM32_RCC_APB1ENR
+#  define TIMEN_TIM17      RCC_APB1ENR_TIM71EN
+#  define TIMRCCRST_TIM17  STM32_RCC_APB1RSTR
+#  define TIMRST_TIM17     RCC_APB1RSTR_TIM17RST
+#endif
+
 /* Debug ********************************************************************/
 
 #ifdef CONFIG_DEBUG_PWM_INFO
@@ -281,7 +434,7 @@ static struct stm32_pwmtimer_s g_pwm1dev =
   .irq         = STM32_IRQ_TIM1UP,
 #endif
   .base        = STM32_TIM1_BASE,
-  .pclk        = STM32_APB2_TIM1_CLKIN,
+  .pclk        = TIMCLK_TIM1,
 };
 #endif
 
@@ -327,7 +480,7 @@ static struct stm32_pwmtimer_s g_pwm2dev =
   .irq         = STM32_IRQ_TIM2,
 #endif
   .base        = STM32_TIM2_BASE,
-  .pclk        = STM32_APB1_TIM2_CLKIN,
+  .pclk        = TIMCLK_TIM2,
 };
 #endif
 
@@ -373,7 +526,7 @@ static struct stm32_pwmtimer_s g_pwm3dev =
   .irq         = STM32_IRQ_TIM3,
 #endif
   .base        = STM32_TIM3_BASE,
-  .pclk        = STM32_APB1_TIM3_CLKIN,
+  .pclk        = TIMCLK_TIM3,
 };
 #endif
 
@@ -419,7 +572,7 @@ static struct stm32_pwmtimer_s g_pwm4dev =
   .irq         = STM32_IRQ_TIM4,
 #endif
   .base        = STM32_TIM4_BASE,
-  .pclk        = STM32_APB1_TIM4_CLKIN,
+  .pclk        = TIMCLK_TIM4,
 };
 #endif
 
@@ -465,7 +618,7 @@ static struct stm32_pwmtimer_s g_pwm5dev =
   .irq         = STM32_IRQ_TIM5,
 #endif
   .base        = STM32_TIM5_BASE,
-  .pclk        = STM32_APB1_TIM5_CLKIN,
+  .pclk        = TIMCLK_TIM5,
 };
 #endif
 
@@ -511,7 +664,7 @@ static struct stm32_pwmtimer_s g_pwm8dev =
   .irq         = STM32_IRQ_TIM8UP,
 #endif
   .base        = STM32_TIM8_BASE,
-  .pclk        = STM32_APB2_TIM8_CLKIN,
+  .pclk        = TIMCLK_TIM8,
 };
 #endif
 
@@ -557,7 +710,7 @@ static struct stm32_pwmtimer_s g_pwm9dev =
   .irq         = STM32_IRQ_TIM9,
 #endif
   .base        = STM32_TIM9_BASE,
-  .pclk        = STM32_APB2_TIM9_CLKIN,
+  .pclk        = TIMCLK_TIM9,
 };
 #endif
 
@@ -603,7 +756,7 @@ static struct stm32_pwmtimer_s g_pwm10dev =
   .irq         = STM32_IRQ_TIM10,
 #endif
   .base        = STM32_TIM10_BASE,
-  .pclk        = STM32_APB2_TIM10_CLKIN,
+  .pclk        = TIMCLK_TIM10,
 };
 #endif
 
@@ -649,7 +802,7 @@ static struct stm32_pwmtimer_s g_pwm11dev =
   .irq         = STM32_IRQ_TIM11,
 #endif
   .base        = STM32_TIM11_BASE,
-  .pclk        = STM32_APB2_TIM11_CLKIN,
+  .pclk        = TIMCLK_TIM11,
 };
 #endif
 
@@ -695,7 +848,7 @@ static struct stm32_pwmtimer_s g_pwm12dev =
   .irq         = STM32_IRQ_TIM12,
 #endif
   .base        = STM32_TIM12_BASE,
-  .pclk        = STM32_APB1_TIM12_CLKIN,
+  .pclk        = TIMCLK_TIM12,
 };
 #endif
 
@@ -741,7 +894,7 @@ static struct stm32_pwmtimer_s g_pwm13dev =
   .irq         = STM32_IRQ_TIM13,
 #endif
   .base        = STM32_TIM13_BASE,
-  .pclk        = STM32_APB1_TIM13_CLKIN,
+  .pclk        = TIMCLK_TIM13,
 };
 #endif
 
@@ -787,7 +940,7 @@ static struct stm32_pwmtimer_s g_pwm14dev =
   .irq         = STM32_IRQ_TIM14,
 #endif
   .base        = STM32_TIM14_BASE,
-  .pclk        = STM32_APB1_TIM14_CLKIN,
+  .pclk        = TIMCLK_TIM14,
 };
 #endif
 
@@ -819,7 +972,7 @@ static struct stm32_pwmtimer_s g_pwm15dev =
   .irq         = STM32_IRQ_TIM15,
 #endif
   .base        = STM32_TIM15_BASE,
-  .pclk        = STM32_APB1_TIM15_CLKIN,
+  .pclk        = TIMCLK_TIM15,
 };
 #endif
 
@@ -844,7 +997,7 @@ static struct stm32_pwmtimer_s g_pwm16dev =
   .irq         = STM32_IRQ_TIM16,
 #endif
   .base        = STM32_TIM16_BASE,
-  .pclk        = STM32_APB1_TIM16_CLKIN,
+  .pclk        = TIMCLK_TIM16,
 };
 #endif
 
@@ -869,7 +1022,7 @@ static struct stm32_pwmtimer_s g_pwm17dev =
   .irq         = STM32_IRQ_TIM17,
 #endif
   .base        = STM32_TIM17_BASE,
-  .pclk        = STM32_APB1_TIM17_CLKIN,
+  .pclk        = TIMCLK_TIM17,
 };
 #endif
 
@@ -954,42 +1107,68 @@ static void pwm_putreg(struct stm32_pwmtimer_s *priv, int offset, uint16_t value
 static void pwm_dumpregs(struct stm32_pwmtimer_s *priv, FAR const char *msg)
 {
   pwminfo("%s:\n", msg);
-  pwminfo("  CR1: %04x CR2:  %04x SMCR:  %04x DIER:  %04x\n",
+  if (priv->timid == 16 || priv->timid == 17)
-          pwm_getreg(priv, STM32_GTIM_CR1_OFFSET),
+    {
-          pwm_getreg(priv, STM32_GTIM_CR2_OFFSET),
+      pwminfo("  CR1: %04x CR2:  %04x DIER:  %04x\n",
-          pwm_getreg(priv, STM32_GTIM_SMCR_OFFSET),
+              pwm_getreg(priv, STM32_GTIM_CR1_OFFSET),
-          pwm_getreg(priv, STM32_GTIM_DIER_OFFSET));
+              pwm_getreg(priv, STM32_GTIM_CR2_OFFSET),
-  pwminfo("   SR: %04x EGR:  %04x CCMR1: %04x CCMR2: %04x\n",
+              pwm_getreg(priv, STM32_GTIM_DIER_OFFSET));
-          pwm_getreg(priv, STM32_GTIM_SR_OFFSET),
+    }
-          pwm_getreg(priv, STM32_GTIM_EGR_OFFSET),
+  else
-          pwm_getreg(priv, STM32_GTIM_CCMR1_OFFSET),
+    {
-          pwm_getreg(priv, STM32_GTIM_CCMR2_OFFSET));
+      pwminfo("  CR1: %04x CR2:  %04x SMCR:  %04x DIER:  %04x\n",
+              pwm_getreg(priv, STM32_GTIM_CR1_OFFSET),
+              pwm_getreg(priv, STM32_GTIM_CR2_OFFSET),
+              pwm_getreg(priv, STM32_GTIM_SMCR_OFFSET),
+              pwm_getreg(priv, STM32_GTIM_DIER_OFFSET));
+    }
+
+  if (priv->timid >= 15 || priv->timid <= 17)
+    {
+      pwminfo("   SR: %04x EGR:  %04x CCMR1: %04x\n",
+              pwm_getreg(priv, STM32_GTIM_SR_OFFSET),
+              pwm_getreg(priv, STM32_GTIM_EGR_OFFSET),
+              pwm_getreg(priv, STM32_GTIM_CCMR1_OFFSET));
+    }
+   else
+    {
+      pwminfo("   SR: %04x EGR:  %04x CCMR1: %04x CCMR2: %04x\n",
+              pwm_getreg(priv, STM32_GTIM_SR_OFFSET),
+              pwm_getreg(priv, STM32_GTIM_EGR_OFFSET),
+              pwm_getreg(priv, STM32_GTIM_CCMR1_OFFSET),
+              pwm_getreg(priv, STM32_GTIM_CCMR2_OFFSET));
+    }
+
   pwminfo(" CCER: %04x CNT:  %04x PSC:   %04x ARR:   %04x\n",
           pwm_getreg(priv, STM32_GTIM_CCER_OFFSET),
           pwm_getreg(priv, STM32_GTIM_CNT_OFFSET),
           pwm_getreg(priv, STM32_GTIM_PSC_OFFSET),
           pwm_getreg(priv, STM32_GTIM_ARR_OFFSET));
-  pwminfo(" CCR1: %04x CCR2: %04x CCR3:  %04x CCR4:  %04x\n",
+
-          pwm_getreg(priv, STM32_GTIM_CCR1_OFFSET),
+  if (priv->timid >= 15 || priv->timid <= 17)
-          pwm_getreg(priv, STM32_GTIM_CCR2_OFFSET),
-          pwm_getreg(priv, STM32_GTIM_CCR3_OFFSET),
-          pwm_getreg(priv, STM32_GTIM_CCR4_OFFSET));
-#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM8_PWM)
-  if (priv->timtype == TIMTYPE_ADVANCED)
     {
-      pwminfo("  RCR: %04x BDTR: %04x DCR:   %04x DMAR:  %04x\n",
+      pwminfo("  RCR: %04x BDTR: %04x\n",
           pwm_getreg(priv, STM32_ATIM_RCR_OFFSET),
-          pwm_getreg(priv, STM32_ATIM_BDTR_OFFSET),
+          pwm_getreg(priv, STM32_ATIM_BDTR_OFFSET));
-          pwm_getreg(priv, STM32_ATIM_DCR_OFFSET),
+    }
-          pwm_getreg(priv, STM32_ATIM_DMAR_OFFSET));
+
+  if (priv->timid == 16 || priv->timid == 17)
+    {
+      pwminfo(" CCR1: %04x\n",
+              pwm_getreg(priv, STM32_GTIM_CCR1_OFFSET));
     }
   else
-#endif
     {
-      pwminfo("  DCR: %04x DMAR: %04x\n",
+      pwminfo(" CCR1: %04x CCR2: %04x CCR3:  %04x CCR4:  %04x\n",
-          pwm_getreg(priv, STM32_GTIM_DCR_OFFSET),
+              pwm_getreg(priv, STM32_GTIM_CCR1_OFFSET),
-          pwm_getreg(priv, STM32_GTIM_DMAR_OFFSET));
+              pwm_getreg(priv, STM32_GTIM_CCR2_OFFSET),
+              pwm_getreg(priv, STM32_GTIM_CCR3_OFFSET),
+              pwm_getreg(priv, STM32_GTIM_CCR4_OFFSET));
     }
+
+  pwminfo("  DCR: %04x DMAR: %04x\n",
+      pwm_getreg(priv, STM32_GTIM_DCR_OFFSET),
+      pwm_getreg(priv, STM32_GTIM_DMAR_OFFSET));
 }
 #endif
 
@@ -1520,8 +1699,10 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
 
   /* Some special setup for advanced timers */
 
-#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM8_PWM)
+#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM8_PWM) || \
-  if (priv->timtype == TIMTYPE_ADVANCED)
+    defined(CONFIG_STM32_TIM15_PWM) || defined(CONFIG_STM32_TIM16_PWM) || \
+    defined(CONFIG_STM32_TIM17_PWM)
+  if (priv->timtype == TIMTYPE_ADVANCED || priv->timtype == TIMTYPE_COUNTUP16)
     {
       uint16_t bdtr;
 
@@ -1530,7 +1711,7 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
        */
 
 #if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
-    defined(CONFIG_STM32_STM32F40XX)
+    defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX)
       ccer &= ~(ATIM_CCER_CC1NE | ATIM_CCER_CC1NP | ATIM_CCER_CC2NE | ATIM_CCER_CC2NP |
                 ATIM_CCER_CC3NE | ATIM_CCER_CC3NP | ATIM_CCER_CC4NP);
 #else
@@ -1553,14 +1734,16 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
       pwm_putreg(priv, STM32_ATIM_BDTR_OFFSET, bdtr);
     }
 #if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
-    defined(CONFIG_STM32_STM32F40XX)
+    defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX)
   else
 #endif
 #endif
 #if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
-    defined(CONFIG_STM32_STM32F40XX)
+    defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX)
     {
-      ccer &= ~(GTIM_CCER_CC1NP | GTIM_CCER_CC2NP | GTIM_CCER_CC3NP);
+      /* CCxNP must be cleared in any case */
+
+      ccer &= ~(GTIM_CCER_CC1NP | GTIM_CCER_CC2NP | GTIM_CCER_CC3NP | GTIM_CCER_CC4NP);
     }
 #endif
 
@@ -1875,98 +2058,100 @@ static void pwm_set_apb_clock(FAR struct stm32_pwmtimer_s *priv, bool on)
   uint32_t en_bit;
   uint32_t regaddr;
 
+  pwminfo("timer %d clock enable: %d\n", priv->timid, on ? 1 : 0);
+
   /* Determine which timer to configure */
 
   switch (priv->timid)
     {
 #ifdef CONFIG_STM32_TIM1_PWM
       case 1:
-        regaddr  = STM32_RCC_APB2ENR;
+        regaddr  = TIMRCCEN_TIM1;
-        en_bit   = RCC_APB2ENR_TIM1EN;
+        en_bit   = TIMEN_TIM1;
         break;
 #endif
 #ifdef CONFIG_STM32_TIM2_PWM
       case 2:
-        regaddr  = STM32_RCC_APB1ENR;
+        regaddr  = TIMRCCEN_TIM2;
-        en_bit   = RCC_APB1ENR_TIM2EN;
+        en_bit   = TIMEN_TIM2;
         break;
 #endif
 #ifdef CONFIG_STM32_TIM3_PWM
       case 3:
-        regaddr  = STM32_RCC_APB1ENR;
+        regaddr  = TIMRCCEN_TIM3;
-        en_bit   = RCC_APB1ENR_TIM3EN;
+        en_bit   = TIMEN_TIM3;
         break;
 #endif
 #ifdef CONFIG_STM32_TIM4_PWM
       case 4:
-        regaddr  = STM32_RCC_APB1ENR;
+        regaddr  = TIMRCCEN_TIM4;
-        en_bit   = RCC_APB1ENR_TIM4EN;
+        en_bit   = TIMEN_TIM4;
         break;
 #endif
 #ifdef CONFIG_STM32_TIM5_PWM
       case 5:
-        regaddr  = STM32_RCC_APB1ENR;
+        regaddr  = TIMRCCEN_TIM5;
-        en_bit   = RCC_APB1ENR_TIM5EN;
+        en_bit   = TIMEN_TIM5;
         break;
 #endif
 #ifdef CONFIG_STM32_TIM8_PWM
       case 8:
-        regaddr  = STM32_RCC_APB2ENR;
+        regaddr  = TIMRCCEN_TIM8;
-        en_bit   = RCC_APB2ENR_TIM8EN;
+        en_bit   = TIMEN_TIM8;
         break;
 #endif
 #ifdef CONFIG_STM32_TIM9_PWM
       case 9:
-        regaddr  = STM32_RCC_APB2ENR;
+        regaddr  = TIMRCCEN_TIM9;
-        en_bit   = RCC_APB2ENR_TIM9EN;
+        en_bit   = TIMEN_TIM9;
         break;
 #endif
 #ifdef CONFIG_STM32_TIM10_PWM
       case 10:
-        regaddr  = STM32_RCC_APB2ENR;
+        regaddr  = TIMRCCEN_TIM10;
-        en_bit   = RCC_APB2ENR_TIM10EN;
+        en_bit   = TIMEN_TIM10;
         break;
 #endif
 #ifdef CONFIG_STM32_TIM11_PWM
       case 11:
-        regaddr  = STM32_RCC_APB2ENR;
+        regaddr  = TIMRCCEN_TIM11;
-        en_bit   = RCC_APB2ENR_TIM11EN;
+        en_bit   = TIMEN_TIM11;
         break;
 #endif
 #ifdef CONFIG_STM32_TIM12_PWM
       case 12:
-        regaddr  = STM32_RCC_APB1ENR;
+        regaddr  = TIMRCCEN_TIM12;
-        en_bit   = RCC_APB1ENR_TIM12EN;
+        en_bit   = TIMEN_TIM12;
         break;
 #endif
 #ifdef CONFIG_STM32_TIM13_PWM
       case 13:
-        regaddr  = STM32_RCC_APB1ENR;
+        regaddr  = TIMRCCEN_TIM13;
-        en_bit   = RCC_APB1ENR_TIM13EN;
+        en_bit   = TIMEN_TIM13;
         break;
 #endif
 #ifdef CONFIG_STM32_TIM14_PWM
       case 14:
-        regaddr  = STM32_RCC_APB1ENR;
+        regaddr  = TIMRCCEN_TIM14;
-        en_bit   = RCC_APB1ENR_TIM14EN;
+        en_bit   = TIMEN_TIM14;
         break;
 #endif
 #ifdef CONFIG_STM32_TIM15_PWM
       case 15:
-        regaddr  = STM32_RCC_APB2ENR;
+        regaddr  = TIMRCCEN_TIM15;
-        en_bit   = RCC_APB2ENR_TIM15EN;
+        en_bit   = TIMEN_TIM15;
         break;
 #endif
 #ifdef CONFIG_STM32_TIM16_PWM
       case 16:
-        regaddr  = STM32_RCC_APB2ENR;
+        regaddr  = TIMRCCEN_TIM16;
-        en_bit   = RCC_APB2ENR_TIM16EN;
+        en_bit   = TIMEN_TIM16;
         break;
 #endif
 #ifdef CONFIG_STM32_TIM17_PWM
       case 17:
-        regaddr  = STM32_RCC_APB2ENR;
+        regaddr  = TIMRCCEN_TIM17;
-        en_bit   = RCC_APB2ENR_TIM17EN;
+        en_bit   = TIMEN_TIM17;
         break;
 #endif
       default:
@@ -1975,6 +2160,8 @@ static void pwm_set_apb_clock(FAR struct stm32_pwmtimer_s *priv, bool on)
 
   /* Enable/disable APB 1/2 clock for timer */
 
+  pwminfo("RCC_APBxENR base: %08x  bits: %04x\n", regaddr, en_bit);
+
   if (on)
     {
       modifyreg32(regaddr, 0, en_bit);
@@ -2012,12 +2199,13 @@ static int pwm_setup(FAR struct pwm_lowerhalf_s *dev)
   int i;
 
   pwminfo("TIM%u\n", priv->timid);
-  pwm_dumpregs(priv, "Initially");
 
   /* Enable APB1/2 clocking for timer. */
 
   pwm_set_apb_clock(priv, true);
 
+  pwm_dumpregs(priv, "Initially");
+
   /* Configure the PWM output pins, but do not start the timer yet */
 
   for (i = 0; i < PWM_NCHANNELS; i++)
@@ -2087,6 +2275,7 @@ static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev)
       pincfg |= GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT;
 #elif defined(CONFIG_STM32_STM32F20XX) || \
       defined(CONFIG_STM32_STM32F30XX) || \
+      defined(CONFIG_STM32_STM32F37XX) || \
       defined(CONFIG_STM32_STM32F40XX) || \
       defined(CONFIG_STM32_STM32L15XX)
       pincfg |= GPIO_INPUT | GPIO_FLOAT;
@@ -2216,6 +2405,104 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
 
   pwminfo("TIM%u\n", priv->timid);
 
+  /* Determine which timer to reset */
+
+  switch (priv->timid)
+    {
+#ifdef CONFIG_STM32_TIM1_PWM
+      case 1:
+        regaddr  = TIMRCCRST_TIM1;
+        resetbit = TIMRST_TIM1;
+        break;
+#endif
+#ifdef CONFIG_STM32_TIM2_PWM
+      case 2:
+        regaddr  = TIMRCCRST_TIM2;
+        resetbit = TIMRST_TIM2;
+        break;
+#endif
+#ifdef CONFIG_STM32_TIM3_PWM
+      case 3:
+        regaddr  = TIMRCCRST_TIM3;
+        resetbit = TIMRST_TIM3;
+        break;
+#endif
+#ifdef CONFIG_STM32_TIM4_PWM
+      case 4:
+        regaddr  = TIMRCCRST_TIM4;
+        resetbit = TIMRST_TIM4;
+        break;
+#endif
+#ifdef CONFIG_STM32_TIM5_PWM
+      case 5:
+        regaddr  = TIMRCCRST_TIM5;
+        resetbit = TIMRST_TIM5;
+        break;
+#endif
+#ifdef CONFIG_STM32_TIM8_PWM
+      case 8:
+        regaddr  = TIMRCCRST_TIM8;
+        resetbit = TIMRST_TIM8;
+        break;
+#endif
+#ifdef CONFIG_STM32_TIM9_PWM
+      case 9:
+        regaddr  = TIMRCCRST_TIM9;
+        resetbit = TIMRST_TIM9;
+        break;
+#endif
+#ifdef CONFIG_STM32_TIM10_PWM
+      case 10:
+        regaddr  = TIMRCCRST_TIM10;
+        resetbit = TIMRST_TIM10;
+        break;
+#endif
+#ifdef CONFIG_STM32_TIM11_PWM
+      case 11:
+        regaddr  = TIMRCCRST_TIM11;
+        resetbit = TIMRST_TIM11;
+        break;
+#endif
+#ifdef CONFIG_STM32_TIM12_PWM
+      case 12:
+        regaddr  = TIMRCCRST_TIM12;
+        resetbit = TIMRST_TIM12;
+        break;
+#endif
+#ifdef CONFIG_STM32_TIM13_PWM
+      case 13:
+        regaddr  = TIMRCCRST_TIM13;
+        resetbit = TIMRST_TIM13;
+        break;
+#endif
+#ifdef CONFIG_STM32_TIM14_PWM
+      case 14:
+        regaddr  = TIMRCCRST_TIM14;
+        resetbit = TIMRST_TIM14;
+        break;
+#endif
+#ifdef CONFIG_STM32_TIM15_PWM
+      case 15:
+        regaddr  = TIMRCCRST_TIM15;
+        resetbit = TIMRST_TIM15;
+        break;
+#endif
+#ifdef CONFIG_STM32_TIM16_PWM
+      case 16:
+        regaddr  = TIMRCCRST_TIM16;
+        resetbit = TIMRST_TIM16;
+        break;
+#endif
+#ifdef CONFIG_STM32_TIM17_PWM
+      case 17:
+        regaddr  = TIMRCCRST_TIM17;
+        resetbit = TIMRST_TIM17;
+        break;
+#endif
+      default:
+        return -EINVAL;
+    }
+
   /* Disable interrupts momentary to stop any ongoing timer processing and
    * to prevent any concurrent access to the reset register.
    */
@@ -2231,104 +2518,6 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
   pwm_putreg(priv, STM32_GTIM_DIER_OFFSET, 0);
   pwm_putreg(priv, STM32_GTIM_SR_OFFSET, 0);
 
-  /* Determine which timer to reset */
-
-  switch (priv->timid)
-    {
-#ifdef CONFIG_STM32_TIM1_PWM
-      case 1:
-        regaddr  = STM32_RCC_APB2RSTR;
-        resetbit = RCC_APB2RSTR_TIM1RST;
-        break;
-#endif
-#ifdef CONFIG_STM32_TIM2_PWM
-      case 2:
-        regaddr  = STM32_RCC_APB1RSTR;
-        resetbit = RCC_APB1RSTR_TIM2RST;
-        break;
-#endif
-#ifdef CONFIG_STM32_TIM3_PWM
-      case 3:
-        regaddr  = STM32_RCC_APB1RSTR;
-        resetbit = RCC_APB1RSTR_TIM3RST;
-        break;
-#endif
-#ifdef CONFIG_STM32_TIM4_PWM
-      case 4:
-        regaddr  = STM32_RCC_APB1RSTR;
-        resetbit = RCC_APB1RSTR_TIM4RST;
-        break;
-#endif
-#ifdef CONFIG_STM32_TIM5_PWM
-      case 5:
-        regaddr  = STM32_RCC_APB1RSTR;
-        resetbit = RCC_APB1RSTR_TIM5RST;
-        break;
-#endif
-#ifdef CONFIG_STM32_TIM8_PWM
-      case 8:
-        regaddr  = STM32_RCC_APB2RSTR;
-        resetbit = RCC_APB2RSTR_TIM8RST;
-        break;
-#endif
-#ifdef CONFIG_STM32_TIM9_PWM
-      case 9:
-        regaddr  = STM32_RCC_APB2RSTR;
-        resetbit = RCC_APB2RSTR_TIM9RST;
-        break;
-#endif
-#ifdef CONFIG_STM32_TIM10_PWM
-      case 10:
-        regaddr  = STM32_RCC_APB2RSTR;
-        resetbit = RCC_APB2RSTR_TIM10RST;
-        break;
-#endif
-#ifdef CONFIG_STM32_TIM11_PWM
-      case 11:
-        regaddr  = STM32_RCC_APB2RSTR;
-        resetbit = RCC_APB2RSTR_TIM11RST;
-        break;
-#endif
-#ifdef CONFIG_STM32_TIM12_PWM
-      case 12:
-        regaddr  = STM32_RCC_APB1RSTR;
-        resetbit = RCC_APB1RSTR_TIM12RST;
-        break;
-#endif
-#ifdef CONFIG_STM32_TIM13_PWM
-      case 13:
-        regaddr  = STM32_RCC_APB1RSTR;
-        resetbit = RCC_APB1RSTR_TIM13RST;
-        break;
-#endif
-#ifdef CONFIG_STM32_TIM14_PWM
-      case 14:
-        regaddr  = STM32_RCC_APB1RSTR;
-        resetbit = RCC_APB1RSTR_TIM14RST;
-        break;
-#endif
-#ifdef CONFIG_STM32_TIM15_PWM
-      case 15:
-        regaddr  = STM32_RCC_APB2RSTR;
-        resetbit = RCC_APB2RSTR_TIM15RST;
-        break;
-#endif
-#ifdef CONFIG_STM32_TIM16_PWM
-      case 16:
-        regaddr  = STM32_RCC_APB2RSTR;
-        resetbit = RCC_APB2RSTR_TIM16RST;
-        break;
-#endif
-#ifdef CONFIG_STM32_TIM17_PWM
-      case 17:
-        regaddr  = STM32_RCC_APB2RSTR;
-        resetbit = RCC_APB2RSTR_TIM17RST;
-        break;
-#endif
-      default:
-        return -EINVAL;
-    }
-
   /* Reset the timer - stopping the output and putting the timer back
    * into a state where pwm_start() can be called.
    */

arch/arm/src/stm32/stm32_sdio.c

@@ -1,7 +1,7 @@
 /****************************************************************************
  * arch/arm/src/stm32/stm32_sdio.c
  *
- *   Copyright (C) 2009, 2011-2014 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009, 2011-2014, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -52,6 +52,7 @@
 #include <nuttx/clock.h>
 #include <nuttx/sdio.h>
 #include <nuttx/wqueue.h>
+#include <nuttx/semaphore.h>
 #include <nuttx/mmcsd.h>
 
 #include <nuttx/irq.h>
@@ -2853,8 +2854,18 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
   struct stm32_dev_s *priv = &g_sdiodev;
 
   /* Initialize the SDIO slot structure */
+  /* Initialize semaphores */
 
   sem_init(&priv->waitsem, 0, 0);
+
+  /* The waitsem semaphore is used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
+  sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
+
+  /* Create a watchdog timer */
+
   priv->waitwdog = wd_create();
   DEBUGASSERT(priv->waitwdog);
 

arch/arm/src/stm32/stm32_spi.c

@@ -70,6 +70,7 @@
 
 #include <nuttx/irq.h>
 #include <nuttx/arch.h>
+#include <nuttx/semaphore.h>
 #include <nuttx/spi/spi.h>
 
 #include <arch/board/board.h>
@@ -1719,12 +1720,18 @@ static void spi_bus_initialize(FAR struct stm32_spidev_s *priv)
 
   sem_init(&priv->exclsem, 0, 1);
 
-  /* Initialize the SPI semaphores that is used to wait for DMA completion */
-
 #ifdef CONFIG_STM32_SPI_DMA
+  /* Initialize the SPI semaphores that is used to wait for DMA completion.
+   * This semaphore is used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
   sem_init(&priv->rxsem, 0, 0);
   sem_init(&priv->txsem, 0, 0);
 
+  sem_setprotocol(&priv->rxsem, SEM_PRIO_NONE);
+  sem_setprotocol(&priv->txsem, SEM_PRIO_NONE);
+
   /* Get DMA channels.  NOTE: stm32_dmachannel() will always assign the DMA channel.
    * if the channel is not available, then stm32_dmachannel() will block and wait
    * until the channel becomes available.  WARNING: If you have another device sharing

arch/arm/src/stm32/stm32f30xxx_i2c.c

@@ -85,8 +85,9 @@
 
 #include <nuttx/arch.h>
 #include <nuttx/irq.h>
-#include <nuttx/i2c/i2c_master.h>
 #include <nuttx/clock.h>
+#include <nuttx/semaphore.h>
+#include <nuttx/i2c/i2c_master.h>
 
 #include <arch/board/board.h>
 
@@ -899,8 +900,14 @@ static inline void stm32_i2c_sem_post(FAR struct stm32_i2c_priv_s *priv)
 static inline void stm32_i2c_sem_init(FAR struct stm32_i2c_priv_s *priv)
 {
   sem_init(&priv->sem_excl, 0, 1);
+
 #ifndef CONFIG_I2C_POLLED
+  /* This semaphore is used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
   sem_init(&priv->sem_isr, 0, 0);
+  sem_setprotocol(&priv->sem_isr, SEM_PRIO_NONE);
 #endif
 }
 

arch/arm/src/stm32/stm32f40xxx_i2c.c

@@ -84,8 +84,9 @@
 
 #include <nuttx/arch.h>
 #include <nuttx/irq.h>
-#include <nuttx/i2c/i2c_master.h>
 #include <nuttx/clock.h>
+#include <nuttx/semaphore.h>
+#include <nuttx/i2c/i2c_master.h>
 
 #include <arch/board/board.h>
 
@@ -786,8 +787,14 @@ static inline void stm32_i2c_sem_post(struct stm32_i2c_priv_s *priv)
 static inline void stm32_i2c_sem_init(FAR struct stm32_i2c_priv_s *priv)
 {
   sem_init(&priv->sem_excl, 0, 1);
+
 #ifndef CONFIG_I2C_POLLED
+  /* This semaphore is used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
   sem_init(&priv->sem_isr, 0, 0);
+  sem_setprotocol(&priv->sem_isr, SEM_PRIO_NONE);
 #endif
 }
 

arch/arm/src/stm32f7/Kconfig

@@ -992,6 +992,10 @@ config STM32F7_SAI
 	bool
 	default n
 
+config STM32F7_SDMMC
+	bool
+	default n
+
 config STM32F7_SPI
 	bool
 	default n
@@ -1006,7 +1010,6 @@ config STM32F7_USART
 
 # These are the peripheral selections proper
 
-
 config STM32F7_ADC1
 	bool "ADC1"
 	default n
@@ -1218,6 +1221,7 @@ config STM32F7_SAI2
 config STM32F7_SDMMC1
 	bool "SDMMC1"
 	default n
+	select STM32F7_SDMMC
 	select ARCH_HAVE_SDIO
 	select ARCH_HAVE_SDIOWAIT_WRCOMPLETE
 	select SDIO_PREFLIGHT
@@ -1226,6 +1230,7 @@ config STM32F7_SDMMC2
 	bool "SDMMC2"
 	default n
 	depends on STM32F7_HAVE_SDMMC2
+	select STM32F7_SDMMC
 	select ARCH_HAVE_SDIO
 	select ARCH_HAVE_SDIOWAIT_WRCOMPLETE
 	select SDIO_PREFLIGHT
@@ -1718,9 +1723,12 @@ config STM32F7_I2C_DUTY16_9
 
 endmenu # "I2C Configuration"
 
+menu "SD/MMC Configuration"
+	depends on STM32F7_SDMMC
+
 config STM32F7_SDMMC_XFRDEBUG
 	bool "SDMMC transfer debug"
-	depends on DEBUG_FS_INFO && (STM32F7_SDMMC1 || STM32F7_SDMMC2)
+	depends on DEBUG_FS_INFO
 	default n
 	---help---
 		Enable special debug instrumentation analyze SDMMC data transfers.
@@ -1730,13 +1738,20 @@ config STM32F7_SDMMC_XFRDEBUG
 		enabled, then DMA register will be collected as well.  Requires also
 		DEBUG_FS and CONFIG_DEBUG_INFO.
 
+config STM32F7_SDMMC_DMA
+	bool "Support DMA data transfers"
+	default n
+	depends on STM32F7_DMA
+	---help---
+		Support DMA data transfers.
+
 menu "SDMMC1 Configuration"
 	depends on STM32F7_SDMMC1
 
 config SDMMC1_DMA
 	bool "Support DMA data transfers on SDMMC1"
 	default y if STM32F7_DMA2
-	depends on STM32F7_DMA2
+	depends on STM32F7_SDMMC_DMA && STM32F7_DMA2
 	---help---
 		Support DMA data transfers on SDMMC1.  Requires STM32F7_SDMMC1 and config STM32F7_DMA2.
 
@@ -1770,7 +1785,7 @@ menu "SDMMC2 Configuration"
 config SDMMC2_DMA
 	bool "Support DMA data transfers on SDMMC2"
 	default y if STM32F7_DMA2
-	depends on STM32F7_DMA2
+	depends on STM32F7_SDMMC_DMA && STM32F7_DMA2
 	---help---
 		Support DMA data transfers on SDMMC2.  Requires STM32F7_SDMMC2 and config STM32F7_DMA2.
 
@@ -1797,6 +1812,7 @@ config SDMMC2_WIDTH_D1_ONLY
 		Select 1-bit transfer mode.  Default: 4-bit transfer mode.
 
 endmenu # "SDMMC2 Configuration"
+endmenu # "SD/MMC Configuration"
 
 if STM32F7_BKPSRAM
 

arch/arm/src/stm32f7/Make.defs

@@ -161,7 +161,7 @@ ifeq ($(CONFIG_STM32F7_SPI),y)
 CHIP_CSRCS += stm32_spi.c
 endif
 
-ifeq ($(CONFIG_STM32F7_SDMMC1),y)
+ifeq ($(CONFIG_STM32F7_SDMMC),y)
 CHIP_CSRCS += stm32_sdmmc.c
 endif
 

arch/arm/src/stm32f7/chip/stm32_otg.h

@@ -77,7 +77,7 @@
 #define STM32_OTG_CID_OFFSET          0x003c /* Core ID register  */
 #define STM32_OTG_HPTXFSIZ_OFFSET     0x0100 /* Host periodic transmit FIFO size register */
 
-#define STM32_OTG_DIEPTXF_OFFSET(n)   (104+(((n)-1) << 2))
+#define STM32_OTG_DIEPTXF_OFFSET(n)   (0x0104+(((n)-1) << 2))
 
 /* Host-mode control and status registers */
 

arch/arm/src/stm32f7/chip/stm32f74xx75xx_rcc.h

@@ -580,7 +580,7 @@
 #  define RCC_PLLI2SCFGR_PLLI2SQ(n)  ((uint32_t)(n) << RCC_PLLI2SCFGR_PLLI2SQ_SHIFT)
 #define RCC_PLLI2SCFGR_PLLI2SR_SHIFT (28)      /* Bits 28-30: PLLI2S division factor for I2S clocks */
 #define RCC_PLLI2SCFGR_PLLI2SR_MASK  (7 << RCC_PLLI2SCFGR_PLLI2SR_SHIFT)
-#  define RCC_PLLI2SCFGR_PLLI2SR(n)  (uint32_t)(n) << RCC_PLLI2SCFGR_PLLI2SR_SHIFT)
+#  define RCC_PLLI2SCFGR_PLLI2SR(n)  ((uint32_t)(n) << RCC_PLLI2SCFGR_PLLI2SR_SHIFT)
 
 /* PLLSAI configuration register */
 

arch/arm/src/stm32f7/chip/stm32f76xx77xx_rcc.h

@@ -601,7 +601,7 @@
 #  define RCC_PLLI2SCFGR_PLLI2SQ(n)  ((uint32_t)(n) << RCC_PLLI2SCFGR_PLLI2SQ_SHIFT)
 #define RCC_PLLI2SCFGR_PLLI2SR_SHIFT (28)      /* Bits 28-30: PLLI2S division factor for I2S clocks */
 #define RCC_PLLI2SCFGR_PLLI2SR_MASK  (7 << RCC_PLLI2SCFGR_PLLI2SR_SHIFT)
-#  define RCC_PLLI2SCFGR_PLLI2SR(n)  (uint32_t)(n) << RCC_PLLI2SCFGR_PLLI2SR_SHIFT)
+#  define RCC_PLLI2SCFGR_PLLI2SR(n)  ((uint32_t)(n) << RCC_PLLI2SCFGR_PLLI2SR_SHIFT)
 
 /* PLLSAI configuration register */
 

arch/arm/src/stm32f7/stm32_i2c.c

@@ -231,9 +231,10 @@
 
 #include <nuttx/arch.h>
 #include <nuttx/irq.h>
-#include <nuttx/i2c/i2c_master.h>
+#include <nuttx/semaphore.h>
 #include <nuttx/kmalloc.h>
 #include <nuttx/clock.h>
+#include <nuttx/i2c/i2c_master.h>
 
 #include <arch/board/board.h>
 
@@ -1089,8 +1090,14 @@ static inline void stm32_i2c_sem_post(FAR struct i2c_master_s *dev)
 static inline void stm32_i2c_sem_init(FAR struct i2c_master_s *dev)
 {
   sem_init(&((struct stm32_i2c_inst_s *)dev)->priv->sem_excl, 0, 1);
+
 #ifndef CONFIG_I2C_POLLED
+  /* This semaphore is used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
   sem_init(&((struct stm32_i2c_inst_s *)dev)->priv->sem_isr, 0, 0);
+  sem_setprotocol(&((struct stm32_i2c_inst_s *)dev)->priv->sem_isr, SEM_PRIO_NONE);
 #endif
 }
 
@@ -1306,17 +1313,17 @@ static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv, uint32_t frequ
         if (frequency == 100000)
           {
             presc        = 0;
-            scl_delay    = 3;
+            scl_delay    = 5;
             sda_delay    = 0;
-            scl_h_period = 30;
+            scl_h_period = 61;
-            scl_l_period = 120;
+            scl_l_period = 89;
 
           }
         else if (frequency == 400000)
            {
              presc        = 0;
              scl_delay    = 3;
-             sda_delay    = 9;
+             sda_delay    = 0;
              scl_h_period = 6;
              scl_l_period = 24;
            }

arch/arm/src/stm32f7/stm32_otgdev.c

@@ -4230,7 +4230,9 @@ static void stm32_epin_disable(FAR struct stm32_ep_s *privep)
 
   /* Clear the EPDISD interrupt indication */
 
-  stm32_putreg(OTG_DIEPINT_EPDISD, stm32_getreg(regaddr));
+  regval = stm32_getreg(regaddr);
+  regval |= OTG_DIEPINT_EPDISD;
+  stm32_putreg(regval, regaddr);
 
   /* Flush any data remaining in the TxFIFO */
 

arch/arm/src/stm32f7/stm32_otghost.c

@@ -53,6 +53,7 @@
 #include <nuttx/arch.h>
 #include <nuttx/kmalloc.h>
 #include <nuttx/clock.h>
+#include <nuttx/semaphore.h>
 #include <nuttx/usb/usb.h>
 #include <nuttx/usb/usbhost.h>
 #include <nuttx/usb/usbhost_devaddr.h>
@@ -5089,6 +5090,12 @@ static inline void stm32_sw_initialize(FAR struct stm32_usbhost_s *priv)
   sem_init(&priv->pscsem,  0, 0);
   sem_init(&priv->exclsem, 0, 1);
 
+  /* The pscsem semaphore is used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
+ sem_setprotocol(&priv->pscsem, SEM_PRIO_NONE);
+
   /* Initialize the driver state data */
 
   priv->smstate   = SMSTATE_DETACHED;
@@ -5104,8 +5111,15 @@ static inline void stm32_sw_initialize(FAR struct stm32_usbhost_s *priv)
   for (i = 0; i < STM32_MAX_TX_FIFOS; i++)
     {
       FAR struct stm32_chan_s *chan = &priv->chan[i];
+
       chan->chidx = i;
+
+      /* The waitsem semaphore is used for signaling and, hence, should not
+       * have priority inheritance enabled.
+       */
+
       sem_init(&chan->waitsem,  0, 0);
+      sem_setprotocol(&chan->waitsem, SEM_PRIO_NONE);
     }
 }
 

arch/arm/src/stm32f7/stm32_sdmmc.c

@@ -53,6 +53,7 @@
 #include <nuttx/clock.h>
 #include <nuttx/sdio.h>
 #include <nuttx/wqueue.h>
+#include <nuttx/semaphore.h>
 #include <nuttx/mmcsd.h>
 
 #include <nuttx/irq.h>
@@ -86,7 +87,7 @@
  *   CONFIG_SDIO_MUXBUS - Setting this configuration enables some locking
  *     APIs to manage concurrent accesses on the SDMMC bus.  This is not
  *     needed for the simple case of a single SD card, for example.
- *   CONFIG_SDIO_DMA - Enable SDMMC.  This is a marginally optional.  For
+ *   CONFIG_STM32F7_SDMMC_DMA - Enable SDMMC.  This is a marginally optional.  For
  *     most usages, SDMMC will cause data overruns if used without DMA.
  *     NOTE the above system DMA configuration options.
  *   CONFIG_SDMMC_WIDTH_D1_ONLY - This may be selected to force the driver
@@ -95,16 +96,16 @@
  *   CONFIG_SDMMC_PRI - SDMMC interrupt priority.  This setting is not very
  *     important since interrupt nesting is not currently supported.
  *   CONFIG_SDMMMC_DMAPRIO - SDMMC DMA priority.  This can be selecte if
- *     CONFIG_SDIO_DMA is enabled.
+ *     CONFIG_STM32F7_SDMMC_DMA is enabled.
  *   CONFIG_CONFIG_STM32F7_SDMMC_XFRDEBUG - Enables some very low-level debug output
  *     This also requires CONFIG_DEBUG_FS and CONFIG_DEBUG_INFO
  */
 
-#if defined(CONFIG_SDIO_DMA) && !defined(CONFIG_STM32F7_DMA2)
+#if defined(CONFIG_STM32F7_SDMMC_DMA) && !defined(CONFIG_STM32F7_DMA2)
-#  warning "CONFIG_SDIO_DMA support requires CONFIG_STM32F7_DMA2"
+#  warning "CONFIG_STM32F7_SDMMC_DMA support requires CONFIG_STM32F7_DMA2"
 #endif
 
-#ifndef CONFIG_SDIO_DMA
+#ifndef CONFIG_STM32F7_SDMMC_DMA
 #  warning "Large Non-DMA transfer may result in RX overrun failures"
 #endif
 
@@ -113,11 +114,11 @@
 #endif
 
 #ifdef CONFIG_STM32F7_SDMMC1
-#  ifndef CONFIG_SDMMC1_PRI
+#  if defined(CONFIG_ARCH_IRQPRIO) && !defined(CONFIG_SDMMC1_PRI)
 #    define CONFIG_SDMMC1_PRI        NVIC_SYSH_PRIORITY_DEFAULT
 #  endif
 
-#  ifdef CONFIG_SDIO_DMA
+#  ifdef CONFIG_STM32F7_SDMMC_DMA
 #    ifndef CONFIG_SDMMC1_DMAPRIO
 #        define CONFIG_SDMMC1_DMAPRIO DMA_SCR_PRIVERYHI
 #    endif
@@ -130,11 +131,11 @@
 #endif
 
 #ifdef CONFIG_STM32F7_SDMMC2
-#  ifndef CONFIG_SDMMC2_PRI
+#  if defined(CONFIG_ARCH_IRQPRIO) && !defined(CONFIG_SDMMC2_PRI)
 #    define CONFIG_SDMMC2_PRI        NVIC_SYSH_PRIORITY_DEFAULT
 #  endif
 
-#  ifdef CONFIG_SDIO_DMA
+#  ifdef CONFIG_STM32F7_SDMMC_DMA
 #    ifndef CONFIG_SDMMC2_DMAPRIO
 #        define CONFIG_SDMMC2_DMAPRIO DMA_SCR_PRIVERYHI
 #    endif
@@ -306,7 +307,7 @@
 /* Register logging support */
 
 #ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG
-#  ifdef CONFIG_SDIO_DMA
+#  ifdef CONFIG_STM32F7_SDMMC_DMA
 #    define SAMPLENDX_BEFORE_SETUP  0
 #    define SAMPLENDX_BEFORE_ENABLE 1
 #    define SAMPLENDX_AFTER_SETUP   2
@@ -342,7 +343,7 @@ struct stm32_dev_s
   uint32_t          d0_gpio;
   xcpt_t            wrchandler;
 #endif
-#ifdef CONFIG_SDIO_DMA
+#ifdef CONFIG_STM32F7_SDMMC_DMA
   uint32_t          dmapri;
 #endif
 
@@ -371,7 +372,7 @@ struct stm32_dev_s
   /* DMA data transfer support */
 
   bool               widebus;    /* Required for DMA support */
-#ifdef CONFIG_SDIO_DMA
+#ifdef CONFIG_STM32F7_SDMMC_DMA
   volatile uint8_t   xfrflags;   /* Used to synchronize SDMMC and DMA completion events */
   bool               dmamode;    /* true: DMA mode transfer */
   DMA_HANDLE         dma;        /* Handle for DMA channel */
@@ -397,7 +398,7 @@ struct stm32_sdioregs_s
 struct stm32_sampleregs_s
 {
   struct stm32_sdioregs_s sdio;
-#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_SDIO_DMA)
+#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32F7_SDMMC_DMA)
   struct stm32_dmaregs_s  dma;
 #endif
 };
@@ -438,7 +439,7 @@ static void stm32_dumpsamples(struct stm32_dev_s *priv);
 #  define   stm32_dumpsamples(priv)
 #endif
 
-#ifdef CONFIG_SDIO_DMA
+#ifdef CONFIG_STM32F7_SDMMC_DMA
 static void stm32_dmacallback(DMA_HANDLE handle, uint8_t status, void *arg);
 #endif
 
@@ -524,7 +525,7 @@ static int  stm32_registercallback(FAR struct sdio_dev_s *dev,
 
 /* DMA */
 
-#ifdef CONFIG_SDIO_DMA
+#ifdef CONFIG_STM32F7_SDMMC_DMA
 static bool stm32_dmasupported(FAR struct sdio_dev_s *dev);
 #ifdef CONFIG_SDIO_PREFLIGHT
 static int  stm32_dmapreflight(FAR struct sdio_dev_s *dev,
@@ -576,7 +577,7 @@ struct stm32_dev_s g_sdmmcdev1 =
     .eventwait        = stm32_eventwait,
     .callbackenable   = stm32_callbackenable,
     .registercallback = stm32_registercallback,
-#ifdef CONFIG_SDIO_DMA
+#ifdef CONFIG_STM32F7_SDMMC_DMA
     .dmasupported     = stm32_dmasupported,
 #ifdef CONFIG_SDIO_PREFLIGHT
     .dmapreflight     = stm32_dmapreflight,
@@ -632,7 +633,7 @@ struct stm32_dev_s g_sdmmcdev2 =
     .eventwait        = stm32_eventwait,
     .callbackenable   = stm32_callbackenable,
     .registercallback = stm32_registercallback,
-#ifdef CONFIG_SDIO_DMA
+#ifdef CONFIG_STM32F7_SDMMC_DMA
     .dmasupported     = stm32_dmasupported,
 #ifdef CONFIG_SDIO_PREFLIGHT
     .dmapreflight     = stm32_dmapreflight,
@@ -839,7 +840,7 @@ static void stm32_configwaitints(struct stm32_dev_s *priv, uint32_t waitmask,
   priv->waitevents = waitevents;
   priv->wkupevent  = wkupevent;
   priv->waitmask   = waitmask;
-#ifdef CONFIG_SDIO_DMA
+#ifdef CONFIG_STM32F7_SDMMC_DMA
   priv->xfrflags   = 0;
 #endif
   sdmmc_putreg32(priv, priv->xfrmask | priv->waitmask, STM32_SDMMC_MASK_OFFSET);
@@ -974,7 +975,7 @@ static void stm32_sample(struct stm32_dev_s *priv, int index)
 {
   struct stm32_sampleregs_s *regs = &g_sampleregs[index];
 
-#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_SDIO_DMA)
+#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32F7_SDMMC_DMA)
   if (priv->dmamode)
     {
       stm32_dmasample(priv->dma, &regs->dma);
@@ -1021,7 +1022,7 @@ static void stm32_sdiodump(struct stm32_sdioregs_s *regs, const char *msg)
 static void stm32_dumpsample(struct stm32_dev_s *priv,
                              struct stm32_sampleregs_s *regs, const char *msg)
 {
-#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_SDIO_DMA)
+#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32F7_SDMMC_DMA)
   if (priv->dmamode)
     {
       stm32_dmadump(priv->dma, &regs->dma, msg);
@@ -1045,7 +1046,7 @@ static void stm32_dumpsamples(struct stm32_dev_s *priv)
 {
   stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_SETUP], "Before setup");
 
-#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_SDIO_DMA)
+#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32F7_SDMMC_DMA)
   if (priv->dmamode)
     {
       stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_ENABLE], "Before DMA enable");
@@ -1055,7 +1056,7 @@ static void stm32_dumpsamples(struct stm32_dev_s *priv)
   stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_AFTER_SETUP], "After setup");
   stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_END_TRANSFER], "End of transfer");
 
-#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_SDIO_DMA)
+#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32F7_SDMMC_DMA)
   if (priv->dmamode)
     {
       stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_DMA_CALLBACK], "DMA Callback");
@@ -1072,7 +1073,7 @@ static void stm32_dumpsamples(struct stm32_dev_s *priv)
  *
  ****************************************************************************/
 
-#ifdef CONFIG_SDIO_DMA
+#ifdef CONFIG_STM32F7_SDMMC_DMA
 static void stm32_dmacallback(DMA_HANDLE handle, uint8_t status, void *arg)
 {
   FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)arg;
@@ -1433,7 +1434,7 @@ static void stm32_endtransfer(struct stm32_dev_s *priv,
 
   /* If this was a DMA transfer, make sure that DMA is stopped */
 
-#ifdef CONFIG_SDIO_DMA
+#ifdef CONFIG_STM32F7_SDMMC_DMA
   if (priv->dmamode)
     {
       /* DMA debug instrumentation */
@@ -1536,7 +1537,7 @@ static int stm32_sdmmc_interrupt(struct stm32_dev_s  *priv)
       pending  = enabled & priv->xfrmask;
       if (pending != 0)
         {
-#ifdef CONFIG_SDIO_DMA
+#ifdef CONFIG_STM32F7_SDMMC_DMA
           if (!priv->dmamode)
 #endif
             {
@@ -1575,7 +1576,7 @@ static int stm32_sdmmc_interrupt(struct stm32_dev_s  *priv)
 
               /* Was this transfer performed in DMA mode? */
 
-#ifdef CONFIG_SDIO_DMA
+#ifdef CONFIG_STM32F7_SDMMC_DMA
               if (priv->dmamode)
                 {
                   /* Yes.. Terminate the transfers only if the DMA has also
@@ -1811,7 +1812,7 @@ static void stm32_reset(FAR struct sdio_dev_s *dev)
   priv->waitevents = 0;      /* Set of events to be waited for */
   priv->waitmask   = 0;      /* Interrupt enables for event waiting */
   priv->wkupevent  = 0;      /* The event that caused the wakeup */
-#ifdef CONFIG_SDIO_DMA
+#ifdef CONFIG_STM32F7_SDMMC_DMA
   priv->xfrflags   = 0;      /* Used to synchronize SDIO and DMA
                               * completion events */
 #endif
@@ -1827,7 +1828,7 @@ static void stm32_reset(FAR struct sdio_dev_s *dev)
   /* DMA data transfer support */
 
   priv->widebus    = false;  /* Required for DMA support */
-#ifdef CONFIG_SDIO_DMA
+#ifdef CONFIG_STM32F7_SDMMC_DMA
   priv->dmamode    = false;  /* true: DMA mode transfer */
 #endif
 
@@ -2107,7 +2108,7 @@ static int stm32_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
 
   priv->buffer    = (uint32_t *)buffer;
   priv->remaining = nbytes;
-#ifdef CONFIG_SDIO_DMA
+#ifdef CONFIG_STM32F7_SDMMC_DMA
   priv->dmamode   = false;
 #endif
 
@@ -2162,7 +2163,7 @@ static int stm32_sendsetup(FAR struct sdio_dev_s *dev, FAR const
 
   priv->buffer    = (uint32_t *)buffer;
   priv->remaining = nbytes;
-#ifdef CONFIG_SDIO_DMA
+#ifdef CONFIG_STM32F7_SDMMC_DMA
   priv->dmamode   = false;
 #endif
 
@@ -2216,7 +2217,7 @@ static int stm32_cancel(FAR struct sdio_dev_s *dev)
 
   /* If this was a DMA transfer, make sure that DMA is stopped */
 
-#ifdef CONFIG_SDIO_DMA
+#ifdef CONFIG_STM32F7_SDMMC_DMA
   if (priv->dmamode)
     {
       /* Make sure that the DMA is stopped (it will be stopped automatically
@@ -2711,7 +2712,7 @@ static sdio_eventset_t stm32_eventwait(FAR struct sdio_dev_s *dev,
   /* Disable event-related interrupts */
 
   stm32_configwaitints(priv, 0, 0, 0);
-#ifdef CONFIG_SDIO_DMA
+#ifdef CONFIG_STM32F7_SDMMC_DMA
   priv->xfrflags   = 0;
 #endif
 
@@ -2807,7 +2808,7 @@ static int stm32_registercallback(FAR struct sdio_dev_s *dev,
  *
  ****************************************************************************/
 
-#ifdef CONFIG_SDIO_DMA
+#ifdef CONFIG_STM32F7_SDMMC_DMA
 static bool stm32_dmasupported(FAR struct sdio_dev_s *dev)
 {
   return true;
@@ -2830,7 +2831,7 @@ static bool stm32_dmasupported(FAR struct sdio_dev_s *dev)
  *   OK on success; a negated errno on failure
  ****************************************************************************/
 
-#if defined(CONFIG_SDIO_DMA) && defined(CONFIG_SDIO_PREFLIGHT)
+#if defined(CONFIG_STM32F7_SDMMC_DMA) && defined(CONFIG_SDIO_PREFLIGHT)
 static int stm32_dmapreflight(FAR struct sdio_dev_s *dev,
                               FAR const uint8_t *buffer, size_t buflen)
 {
@@ -2876,7 +2877,7 @@ static int stm32_dmapreflight(FAR struct sdio_dev_s *dev,
  *
  ****************************************************************************/
 
-#ifdef CONFIG_SDIO_DMA
+#ifdef CONFIG_STM32F7_SDMMC_DMA
 static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
                               size_t buflen)
 {
@@ -2961,7 +2962,7 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
  *
  ****************************************************************************/
 
-#ifdef CONFIG_SDIO_DMA
+#ifdef CONFIG_STM32F7_SDMMC_DMA
 static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev,
                               FAR const uint8_t *buffer, size_t buflen)
 {
@@ -3151,7 +3152,7 @@ static void stm32_default(struct stm32_dev_s *priv)
 FAR struct sdio_dev_s *sdio_initialize(int slotno)
 {
   struct stm32_dev_s *priv = NULL;
-#ifdef CONFIG_SDIO_DMA
+#ifdef CONFIG_STM32F7_SDMMC_DMA
   unsigned int      dmachan;
 #endif
 
@@ -3161,7 +3162,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
       /* Select SDMMC 1 */
 
       priv = &g_sdmmcdev1;
-#ifdef CONFIG_SDIO_DMA
+#ifdef CONFIG_STM32F7_SDMMC_DMA
       dmachan = SDMMC1_DMACHAN;
 #endif
 
@@ -3191,7 +3192,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
       /* Select SDMMC 2 */
 
       priv = &g_sdmmcdev2;
-#ifdef CONFIG_SDIO_DMA
+#ifdef CONFIG_STM32F7_SDMMC_DMA
       dmachan = SDMMC2_DMACHAN;
 #endif
 
@@ -3214,14 +3215,24 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
     }
 
   /* Initialize the SDIO slot structure */
+  /* Initialize semaphores */
 
   sem_init(&priv->waitsem, 0, 0);
+
+  /* The waitsem semaphore is used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
+  sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
+
+  /* Create a watchdog timer */
+
   priv->waitwdog = wd_create();
   DEBUGASSERT(priv->waitwdog);
 
   /* Allocate a DMA channel */
 
-#ifdef CONFIG_SDIO_DMA
+#ifdef CONFIG_STM32F7_SDMMC_DMA
   priv->dma = stm32_dmachannel(dmachan);
   DEBUGASSERT(priv->dma);
 #endif

arch/arm/src/stm32f7/stm32_spi.c

@@ -72,6 +72,7 @@
 
 #include <nuttx/irq.h>
 #include <nuttx/arch.h>
+#include <nuttx/semaphore.h>
 #include <nuttx/spi/spi.h>
 
 #include <arch/board/board.h>
@@ -1665,16 +1666,22 @@ static void spi_bus_initialize(FAR struct stm32_spidev_s *priv)
 
   spi_putreg(priv, STM32_SPI_CRCPR_OFFSET, 7);
 
-  /* Initialize the SPI semaphore that enforces mutually exclusive access */
+  /* Initialize the SPI semaphore that enforces mutually exclusive access. */
 
   sem_init(&priv->exclsem, 0, 1);
 
-  /* Initialize the SPI semaphores that is used to wait for DMA completion */
-
 #ifdef CONFIG_STM32F7_SPI_DMA
+  /* Initialize the SPI semaphores that is used to wait for DMA completion.
+   * This semaphore is used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
   sem_init(&priv->rxsem, 0, 0);
   sem_init(&priv->txsem, 0, 0);
 
+  sem_setprotocol(&priv->rxsem, SEM_PRIO_NONE);
+  sem_setprotocol(&priv->txsem, SEM_PRIO_NONE);
+
   /* Get DMA channels.  NOTE: stm32_dmachannel() will always assign the DMA channel.
    * if the channel is not available, then stm32_dmachannel() will block and wait
    * until the channel becomes available.  WARNING: If you have another device sharing

arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c

@@ -882,10 +882,10 @@ static void stm32_stdclockconfig(void)
                   | RCC_PLLI2SCFGR_PLLI2SP_MASK
                   | RCC_PLLI2SCFGR_PLLI2SQ_MASK
                   | RCC_PLLI2SCFGR_PLLI2SR_MASK);
-      regval |= (STM32_RCC_PLLSAICFGR_PLLSAIN
+      regval |= (STM32_RCC_PLLI2SCFGR_PLLI2SN
-                 | STM32_RCC_PLLSAICFGR_PLLSAIP
+                 | STM32_RCC_PLLI2SCFGR_PLLI2SP
-                 | STM32_RCC_PLLSAICFGR_PLLSAIQ
+                 | STM32_RCC_PLLI2SCFGR_PLLI2SQ
-                 | STM32_RCC_PLLSAICFGR_PLLSAIR);
+                 | STM32_RCC_PLLI2SCFGR_PLLI2SR);
       putreg32(regval, STM32_RCC_PLLI2SCFGR);
 
       regval  = getreg32(STM32_RCC_DCKCFGR2);

arch/arm/src/stm32l4/Kconfig

@@ -2807,11 +2807,12 @@ config STM32L4_TIM1_QE
 
 if STM32L4_TIM1_QE
 
-config STM32L4_TIM1_QECLKOUT
+config STM32L4_TIM1_QEPSC
-	int "TIM1 output clock"
+	int "TIM1 pulse prescaler"
-	default 2800000
+	default 1
 	---help---
-		The output clock of TIM1.
+		This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution.
+		Replaces the obscure "output clock of TIM1." (CONFIG_TIM1_QECLKOUT).
 
 endif
 
@@ -2824,11 +2825,12 @@ config STM32L4_TIM2_QE
 
 if STM32L4_TIM2_QE
 
-config STM32L4_TIM2_QECLKOUT
+config STM32L4_TIM2_QEPSC
-	int "TIM2 output clock"
+	int "TIM2 pulse prescaler"
-	default 2800000
+	default 1
 	---help---
-		The output clock of TIM2.
+		This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution.
+		Replaces the obscure "output clock of TIM2." (CONFIG_TIM2_QECLKOUT).
 
 endif
 
@@ -2841,11 +2843,12 @@ config STM32L4_TIM3_QE
 
 if STM32L4_TIM3_QE
 
-config STM32L4_TIM3_QECLKOUT
+config STM32L4_TIM3_QEPSC
-	int "TIM3 output clock"
+	int "TIM3 pulse prescaler"
-	default 2800000
+	default 1
 	---help---
-		The output clock of TIM3.
+		This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution.
+		Replaces the obscure "output clock of TIM3." (CONFIG_TIM3_QECLKOUT).
 
 endif
 
@@ -2858,11 +2861,12 @@ config STM32L4_TIM4_QE
 
 if STM32L4_TIM4_QE
 
-config STM32L4_TIM4_QECLKOUT
+config STM32L4_TIM4_QEPSC
-	int "TIM4 output clock"
+	int "TIM4 pulse prescaler"
-	default 2800000
+	default 1
 	---help---
-		The output clock of TIM4.
+		This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution.
+		Replaces the obscure "output clock of TIM4." (CONFIG_TIM4_QECLKOUT).
 
 endif
 
@@ -2875,11 +2879,12 @@ config STM32L4_TIM5_QE
 
 if STM32L4_TIM5_QE
 
-config STM32L4_TIM5_QECLKOUT
+config STM32L4_TIM5_QEPSC
-	int "TIM5 output clock"
+	int "TIM5 pulse prescaler"
-	default 2800000
+	default 1
 	---help---
-		The output clock of TIM5.
+		This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution.
+		Replaces the obscure "output clock of TIM5." (CONFIG_TIM5_QECLKOUT).
 
 endif
 
@@ -2892,11 +2897,12 @@ config STM32L4_TIM8_QE
 
 if STM32L4_TIM8_QE
 
-config STM32L4_TIM8_QECLKOUT
+config STM32L4_TIM8_QEPSC
-	int "TIM8 output clock"
+	int "TIM8 pulse prescaler"
-	default 2800000
+	default 1
 	---help---
-		The output clock of TIM8.
+		This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution.
+		Replaces the obscure "output clock of TIM8." (CONFIG_TIM8_QECLKOUT).
 
 endif
 

arch/arm/src/stm32l4/stm32l4_i2c.c

@@ -81,8 +81,9 @@
 
 #include <nuttx/arch.h>
 #include <nuttx/irq.h>
-#include <nuttx/i2c/i2c_master.h>
 #include <nuttx/clock.h>
+#include <nuttx/semaphore.h>
+#include <nuttx/i2c/i2c_master.h>
 
 #include <arch/board/board.h>
 
@@ -843,8 +844,14 @@ static inline void stm32l4_i2c_sem_post(FAR struct stm32l4_i2c_priv_s *priv)
 static inline void stm32l4_i2c_sem_init(FAR struct stm32l4_i2c_priv_s *priv)
 {
   sem_init(&priv->sem_excl, 0, 1);
+
 #ifndef CONFIG_I2C_POLLED
+  /* This semaphore is used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
   sem_init(&priv->sem_isr, 0, 0);
+  sem_setprotocol(&priv->sem_isr, SEM_PRIO_NONE);
 #endif
 }
 

arch/arm/src/stm32l4/stm32l4_otgfshost.c

@@ -53,6 +53,7 @@
 #include <nuttx/arch.h>
 #include <nuttx/kmalloc.h>
 #include <nuttx/clock.h>
+#include <nuttx/semaphore.h>
 #include <nuttx/usb/usb.h>
 #include <nuttx/usb/usbhost.h>
 #include <nuttx/usb/usbhost_devaddr.h>
@@ -5096,6 +5097,12 @@ static inline void stm32l4_sw_initialize(FAR struct stm32l4_usbhost_s *priv)
   sem_init(&priv->pscsem,  0, 0);
   sem_init(&priv->exclsem, 0, 1);
 
+  /* The pscsem semaphore is used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
+ sem_setprotocol(&priv->pscsem, SEM_PRIO_NONE);
+
   /* Initialize the driver state data */
 
   priv->smstate   = SMSTATE_DETACHED;
@@ -5111,8 +5118,15 @@ static inline void stm32l4_sw_initialize(FAR struct stm32l4_usbhost_s *priv)
   for (i = 0; i < STM32L4_MAX_TX_FIFOS; i++)
     {
       FAR struct stm32l4_chan_s *chan = &priv->chan[i];
+
       chan->chidx = i;
+
+      /* The waitsem semaphore is used for signaling and, hence, should not
+       * have priority inheritance enabled.
+       */
+
       sem_init(&chan->waitsem,  0, 0);
+      sem_setprotocol(&chan->waitsem, SEM_PRIO_NONE);
     }
 }
 

arch/arm/src/stm32l4/stm32l4_qencoder.c

@@ -66,31 +66,6 @@
  * Pre-processor Definitions
  ************************************************************************************/
 /* Clocking *************************************************************************/
-/* The CLKOUT value should not exceed the CLKIN value */
-
-#if defined(CONFIG_STM32L4_TIM1_QE) && CONFIG_STM32L4_TIM1_QECLKOUT > STM32L4_APB2_TIM1_CLKIN
-#  warning "CONFIG_STM32L4_TIM1_QECLKOUT exceeds STM32L4_APB2_TIM1_CLKIN"
-#endif
-
-#if defined(CONFIG_STM32L4_TIM2_QE) && CONFIG_STM32L4_TIM2_QECLKOUT > STM32L4_APB1_TIM2_CLKIN
-#  warning "CONFIG_STM32L4_TIM2_QECLKOUT exceeds STM32L4_APB2_TIM2_CLKIN"
-#endif
-
-#if defined(CONFIG_STM32L4_TIM3_QE) && CONFIG_STM32L4_TIM3_QECLKOUT >  STM32L4_APB1_TIM3_CLKIN
-#  warning "CONFIG_STM32L4_TIM3_QECLKOUT exceeds STM32L4_APB2_TIM3_CLKIN"
-#endif
-
-#if defined(CONFIG_STM32L4_TIM4_QE) && CONFIG_STM32L4_TIM4_QECLKOUT > STM32L4_APB1_TIM4_CLKIN
-#  warning "CONFIG_STM32L4_TIM4_QECLKOUT exceeds STM32L4_APB2_TIM4_CLKIN"
-#endif
-
-#if defined(CONFIG_STM32L4_TIM5_QE) && CONFIG_STM32L4_TIM5_QECLKOUT > STM32L4_APB1_TIM5_CLKIN
-#  warning "CONFIG_STM32L4_TIM5_QECLKOUT exceeds STM32L4_APB2_TIM5_CLKIN"
-#endif
-
-#if defined(CONFIG_STM32L4_TIM8_QE) && CONFIG_STM32L4_TIM8_QECLKOUT > STM32L4_APB2_TIM8_CLKIN
-#  warning "CONFIG_STM32L4_TIM8_QECLKOUT exceeds STM32L4_APB2_TIM8_CLKIN"
-#endif
 
 /* Timers ***************************************************************************/
 
@@ -223,7 +198,7 @@ struct stm32l4_qeconfig_s
   uint32_t ti1cfg;  /* TI1 input pin configuration (20-bit encoding) */
   uint32_t ti2cfg;  /* TI2 input pin configuration (20-bit encoding) */
   uint32_t base;    /* Register base address */
-  uint32_t psc;     /* Timer input clock prescaler */
+  uint32_t psc;     /* Encoder pulses prescaler */
   xcpt_t   handler; /* Interrupt handler for this IRQ */
 };
 
@@ -323,7 +298,7 @@ static const struct stm32l4_qeconfig_s g_tim1config =
   .width    = TIM1_BITWIDTH,
 #endif
   .base     = STM32L4_TIM1_BASE,
-  .psc      = (STM32L4_APB2_TIM1_CLKIN / CONFIG_STM32L4_TIM1_QECLKOUT) - 1,
+  .psc      = CONFIG_STM32L4_TIM1_QEPSC,
   .ti1cfg   = GPIO_TIM1_CH1IN,
   .ti2cfg   = GPIO_TIM1_CH2IN,
 #if TIM1_BITWIDTH == 16
@@ -349,7 +324,7 @@ static const struct stm32l4_qeconfig_s g_tim2config =
   .width    = TIM2_BITWIDTH,
 #endif
   .base     = STM32L4_TIM2_BASE,
-  .psc      = (STM32L4_APB1_TIM2_CLKIN / CONFIG_STM32L4_TIM2_QECLKOUT) - 1,
+  .psc      = CONFIG_STM32L4_TIM2_QEPSC,
   .ti1cfg   = GPIO_TIM2_CH1IN,
   .ti2cfg   = GPIO_TIM2_CH2IN,
 #if TIM2_BITWIDTH == 16
@@ -375,7 +350,7 @@ static const struct stm32l4_qeconfig_s g_tim3config =
   .width    = TIM3_BITWIDTH,
 #endif
   .base     = STM32L4_TIM3_BASE,
-  .psc      = (STM32L4_APB1_TIM3_CLKIN / CONFIG_STM32L4_TIM3_QECLKOUT) - 1,
+  .psc      = CONFIG_STM32L4_TIM3_QEPSC,
   .ti1cfg   = GPIO_TIM3_CH1IN,
   .ti2cfg   = GPIO_TIM3_CH2IN,
 #if TIM3_BITWIDTH == 16
@@ -401,7 +376,7 @@ static const struct stm32l4_qeconfig_s g_tim4config =
   .width    = TIM4_BITWIDTH,
 #endif
   .base     = STM32L4_TIM4_BASE,
-  .psc      = (STM32L4_APB1_TIM4_CLKIN / CONFIG_STM32L4_TIM4_QECLKOUT) - 1,
+  .psc      = CONFIG_STM32L4_TIM4_QEPSC,
   .ti1cfg   = GPIO_TIM4_CH1IN,
   .ti2cfg   = GPIO_TIM4_CH2IN,
 #if TIM4_BITWIDTH == 16
@@ -427,7 +402,7 @@ static const struct stm32l4_qeconfig_s g_tim5config =
   .width    = TIM5_BITWIDTH,
 #endif
   .base     = STM32L4_TIM5_BASE,
-  .psc      = (STM32L4_APB1_TIM5_CLKIN / CONFIG_STM32L4_TIM5_QECLKOUT) - 1,
+  .psc      = CONFIG_STM32L4_TIM5_QEPSC,
   .ti1cfg   = GPIO_TIM5_CH1IN,
   .ti2cfg   = GPIO_TIM5_CH2IN,
 #if TIM5_BITWIDTH == 16
@@ -453,7 +428,7 @@ static const struct stm32l4_qeconfig_s g_tim8config =
   .width    = TIM8_BITWIDTH,
 #endif
   .base     = STM32L4_TIM8_BASE,
-  .psc      = (STM32L4_APB2_TIM8_CLKIN / CONFIG_STM32L4_TIM8_QECLKOUT) - 1,
+  .psc      = CONFIG_STM32L4_TIM8_QEPSC,
   .ti1cfg   = GPIO_TIM8_CH1IN,
   .ti2cfg   = GPIO_TIM8_CH2IN,
 #if TIM8_BITWIDTH == 16
@@ -804,10 +779,23 @@ static int stm32l4_setup(FAR struct qe_lowerhalf_s *lower)
   stm32l4_putreg16(priv, STM32L4_GTIM_ARR_OFFSET, 0xffff);
 #endif
 
-  /* Set the timer prescaler value.  The clock input value (CLKIN) is based on the
+  /* Set the timer prescaler value.
-   * peripheral clock (PCLK) and a multiplier.  These CLKIN values are provided in
+   *
-   * the board.h file.  The prescaler value is then that CLKIN value divided by the
+   * Previously, and still in the stm32fx driver, the clock input value (CLKIN)
-   * configured CLKOUT value (minus one)
+   * was based on the peripheral clock (PCLK) and a multiplier.
+   * These CLKIN values are provided in the board.h file.
+   * The prescaler value is then that CLKIN value divided by the configured
+   * CLKOUT value (minus one).
+   *
+   * It was determined that this configuration makes no sense for a qencoder.
+   * If we are doing precise shaft positioning, each qe pulse is important.
+   * So the STM32L4 has direct config control on the pulse count prescaler,
+   * instead of deriving this value from an obscure "output" setting AND the
+   * timer input clock. This input clock just limits the incoming pulse rate,
+   * which should be lower than the peripheral clock due to resynchronization,
+   * but it is the responsibility of the system designer to decide the
+   * correct prescaler value, because it has a direct influence on the
+   * encoder resolution.
    */
 
   stm32l4_putreg16(priv, STM32L4_GTIM_PSC_OFFSET, (uint16_t)priv->config->psc);
@@ -1184,6 +1172,8 @@ static int stm32l4_ioctl(FAR struct qe_lowerhalf_s *lower, int cmd, unsigned lon
 {
   /* No ioctl commands supported */
 
+  /* TODO add an IOCTL to control the encoder pulse count prescaler */
+
   return -ENOTTY;
 }
 

arch/arm/src/stm32l4/stm32l4_qspi.c

@@ -55,6 +55,7 @@
 #include <nuttx/wdog.h>
 #include <nuttx/clock.h>
 #include <nuttx/kmalloc.h>
+#include <nuttx/semaphore.h>
 #include <nuttx/spi/qspi.h>
 
 #include "up_internal.h"
@@ -2501,10 +2502,12 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf)
         }
 
       /* Initialize the QSPI semaphore that is used to wake up the waiting
-       * thread when the DMA transfer completes.
+       * thread when the DMA transfer completes.  This semaphore is used for
+       * signaling and, hence, should not have priority inheritance enabled.
        */
 
       sem_init(&priv->dmawait, 0, 0);
+      sem_setprotocol(&priv->dmawait, SEM_PRIO_NONE);
 
       /* Create a watchdog time to catch DMA timeouts */
 
@@ -2526,10 +2529,13 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf)
           goto errout_with_dmadog;
         }
 
-      /* Initialize the semaphore that blocks until the operation completes */
+      /* Initialize the semaphore that blocks until the operation completes.
+       * This semaphore is used for signaling and, hence, should not have
+       * priority inheritance enabled.
+       */
 
       sem_init(&priv->op_sem, 0, 0);
-
+      sem_setprotocol(&priv->op_sem, SEM_PRIO_NONE);
 #endif
 
       /* Perform hardware initialization.  Puts the QSPI into an active

arch/arm/src/stm32l4/stm32l4_rng.c

@@ -47,6 +47,7 @@
 
 #include <nuttx/irq.h>
 #include <nuttx/arch.h>
+#include <nuttx/semaphore.h>
 #include <nuttx/fs/fs.h>
 #include <nuttx/drivers/drivers.h>
 
@@ -259,11 +260,14 @@ static ssize_t stm32l4_rngread(struct file *filep, char *buffer, size_t buflen)
     {
       /* We've got the device semaphore, proceed with reading */
 
-      /* Initialize the operation semaphore with 0 for blocking until
+      /* Initialize the operation semaphore with 0 for blocking until the
-       * the buffer is filled from interrupts.
+       * buffer is filled from interrupts.  The waitsem semaphore is used
+       * for signaling and, hence, should not have priority inheritance
+       * enabled.
        */
 
       sem_init(&g_rngdev.rd_readsem, 0, 0);
+      sem_setprotocol(&g_rngdev.rd_readsem, SEM_PRIO_NONE);
 
       g_rngdev.rd_buflen = buflen;
       g_rngdev.rd_buf = buffer;

arch/arm/src/stm32l4/stm32l4_spi.c

@@ -76,6 +76,7 @@
 
 #include <nuttx/irq.h>
 #include <nuttx/arch.h>
+#include <nuttx/semaphore.h>
 #include <nuttx/spi/spi.h>
 
 #include <arch/board/board.h>
@@ -1517,6 +1518,13 @@ static void spi_bus_initialize(FAR struct stm32l4_spidev_s *priv)
   sem_init(&priv->rxsem, 0, 0);
   sem_init(&priv->txsem, 0, 0);
 
+  /* These semaphores are used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
+  sem_setprotocol(&priv->rxsem, SEM_PRIO_NONE);
+  sem_setprotocol(&priv->txsem, SEM_PRIO_NONE);
+
   /* Get DMA channels.  NOTE: stm32l4_dmachannel() will always assign the DMA channel.
    * if the channel is not available, then stm32l4_dmachannel() will block and wait
    * until the channel becomes available.  WARNING: If you have another device sharing

arch/arm/src/tiva/tiva_i2c.c

@@ -57,8 +57,9 @@
 
 #include <nuttx/arch.h>
 #include <nuttx/irq.h>
-#include <nuttx/i2c/i2c_master.h>
 #include <nuttx/clock.h>
+#include <nuttx/semaphore.h>
+#include <nuttx/i2c/i2c_master.h>
 
 #include <arch/board/board.h>
 
@@ -891,8 +892,14 @@ static inline void tiva_i2c_sem_post(struct tiva_i2c_priv_s *priv)
 static inline void tiva_i2c_sem_init(struct tiva_i2c_priv_s *priv)
 {
   sem_init(&priv->exclsem, 0, 1);
+
 #ifndef CONFIG_I2C_POLLED
+  /* This semaphore is used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
   sem_init(&priv->waitsem, 0, 0);
+  sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
 #endif
 }
 

arch/arm/src/tiva/tiva_ssi.c

@@ -47,6 +47,7 @@
 #include <debug.h>
 
 #include <nuttx/arch.h>
+#include <nuttx/semaphore.h>
 #include <nuttx/spi/spi.h>
 
 #include <nuttx/irq.h>
@@ -1635,7 +1636,12 @@ FAR struct spi_dev_s *tiva_ssibus_initialize(int port)
   /* Initialize the state structure */
 
 #ifndef CONFIG_SSI_POLLWAIT
+  /* The xfrsem semaphore is used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
   sem_init(&priv->xfrsem, 0, 0);
+  sem_setprotocol(&priv->xfrsem, SEM_PRIO_NONE);
 #endif
   sem_init(&priv->exclsem, 0, 1);
 

arch/mips/src/pic32mz/pic32mz-dma.h

@@ -224,5 +224,10 @@ void pic32mx_dmadump(DMA_HANDLE handle, const struct pic32mx_dmaregs_s *regs,
 #endif
 #endif
 
+#if defined(__cplusplus)
+}
+#endif
+#undef EXTERN
+
 #endif /* __ASSEMBLY__ */
 #endif /* __ARCH_MIPS_SRC_PIC32MZ_PIC32MZ_DMA_H */

arch/misoc/Kconfig

@@ -0,0 +1,72 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+if ARCH_MISOC
+
+choice
+	prompt "Misoc Chip Selection"
+	default ARCH_CHIP_LM32
+
+config ARCH_CHIP_LM32
+	bool "LM32"
+	select MISOC_HAVE_UART1
+	---help---
+		LM32 Chip Selected
+
+config ARCH_CHIP_MOR1K
+	bool "MOR1K"
+	---help---
+		MOR1K Chip Selected
+
+endchoice # Misoc Chip Selection
+
+config ARCH_CHIP
+	string
+	default "lm32"		if ARCH_CHIP_LM32
+	default "mor1k"		if ARCH_CHIP_MOR1K
+
+menu "MISOC Peripheral Support"
+
+# These "hidden" settings determine is a peripheral option is available for the
+# selection MCU
+
+config MISOC_HAVE_UART1
+	bool
+	default n
+	select UART1_SERIALDRIVER
+
+config MISOC_UART1
+	bool "UART1"
+	default n
+	select ARCH_HAVE_UART1
+	select MISOC_UART
+
+endmenu # MISOC Peripheral Support
+
+config MISOC_UART
+	bool
+
+config MISOC_UART_RX_BUF_SIZE
+	int "UART RX Bufer size"
+	default 64
+	depends on MISOC_UART
+	---help---
+		Size of RX buffers for MISOC UARTs
+
+config MISOC_UART_TX_BUF_SIZE
+	int "UART TX Bufer size"
+	default 64
+	depends on MISOC_UART
+	---help---
+		Size of TX buffers for MISOC UARTs
+
+if ARCH_CHIP_LM32
+source arch/misoc/src/lm32/Kconfig
+endif
+if ARCH_CHIP_MOR1K
+#source arch/misoc/src/mor1k/Kconfig
+endif
+
+endif # ARCH_MISOC

arch/misoc/include/.gitignore

@@ -0,0 +1,3 @@
+/board
+/chip
+

arch/misoc/include/inttypes.h

@@ -0,0 +1,245 @@
+/****************************************************************************
+ * arch/misoc/include/inttypes.h
+ *
+ *   Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved.
+ *   Author: Paul Alexander Patience <paul-a.patience@polymtl.ca>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_MISOC_INCLUDE_INTTYPES_H
+#define __ARCH_MISOC_INCLUDE_INTTYPES_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define PRId8       "d"
+#define PRId16      "d"
+#define PRId32      "d"
+#define PRId64      "lld"
+
+#define PRIdLEAST8  "d"
+#define PRIdLEAST16 "d"
+#define PRIdLEAST32 "d"
+#define PRIdLEAST64 "lld"
+
+#define PRIdFAST8   "d"
+#define PRIdFAST16  "d"
+#define PRIdFAST32  "d"
+#define PRIdFAST64  "lld"
+
+#define PRIdMAX     "lld"
+#define PRIdPTR     "d"
+
+#define PRIi8       "i"
+#define PRIi16      "i"
+#define PRIi32      "i"
+#define PRIi64      "lli"
+
+#define PRIiLEAST8  "i"
+#define PRIiLEAST16 "i"
+#define PRIiLEAST32 "i"
+#define PRIiLEAST64 "lli"
+
+#define PRIiFAST8   "i"
+#define PRIiFAST16  "i"
+#define PRIiFAST32  "i"
+#define PRIiFAST64  "lli"
+
+#define PRIiMAX     "lli"
+#define PRIiPTR     "i"
+
+#define PRIo8       "o"
+#define PRIo16      "o"
+#define PRIo32      "o"
+#define PRIo64      "llo"
+
+#define PRIoLEAST8  "o"
+#define PRIoLEAST16 "o"
+#define PRIoLEAST32 "o"
+#define PRIoLEAST64 "llo"
+
+#define PRIoFAST8   "o"
+#define PRIoFAST16  "o"
+#define PRIoFAST32  "o"
+#define PRIoFAST64  "llo"
+
+#define PRIoMAX     "llo"
+#define PRIoPTR     "o"
+
+#define PRIu8       "u"
+#define PRIu16      "u"
+#define PRIu32      "u"
+#define PRIu64      "llu"
+
+#define PRIuLEAST8  "u"
+#define PRIuLEAST16 "u"
+#define PRIuLEAST32 "u"
+#define PRIuLEAST64 "llu"
+
+#define PRIuFAST8   "u"
+#define PRIuFAST16  "u"
+#define PRIuFAST32  "u"
+#define PRIuFAST64  "llu"
+
+#define PRIuMAX     "llu"
+#define PRIuPTR     "u"
+
+#define PRIx8       "x"
+#define PRIx16      "x"
+#define PRIx32      "x"
+#define PRIx64      "llx"
+
+#define PRIxLEAST8  "x"
+#define PRIxLEAST16 "x"
+#define PRIxLEAST32 "x"
+#define PRIxLEAST64 "llx"
+
+#define PRIxFAST8   "x"
+#define PRIxFAST16  "x"
+#define PRIxFAST32  "x"
+#define PRIxFAST64  "llx"
+
+#define PRIxMAX     "llx"
+#define PRIxPTR     "x"
+
+#define PRIX8       "X"
+#define PRIX16      "X"
+#define PRIX32      "X"
+#define PRIX64      "llX"
+
+#define PRIXLEAST8  "X"
+#define PRIXLEAST16 "X"
+#define PRIXLEAST32 "X"
+#define PRIXLEAST64 "llX"
+
+#define PRIXFAST8   "X"
+#define PRIXFAST16  "X"
+#define PRIXFAST32  "X"
+#define PRIXFAST64  "llX"
+
+#define PRIXMAX     "llX"
+#define PRIXPTR     "X"
+
+#define SCNd8       "hhd"
+#define SCNd16      "hd"
+#define SCNd32      "d"
+#define SCNd64      "lld"
+
+#define SCNdLEAST8  "hhd"
+#define SCNdLEAST16 "hd"
+#define SCNdLEAST32 "d"
+#define SCNdLEAST64 "lld"
+
+#define SCNdFAST8   "hhd"
+#define SCNdFAST16  "hd"
+#define SCNdFAST32  "d"
+#define SCNdFAST64  "lld"
+
+#define SCNdMAX     "lld"
+#define SCNdPTR     "d"
+
+#define SCNi8       "hhi"
+#define SCNi16      "hi"
+#define SCNi32      "i"
+#define SCNi64      "lli"
+
+#define SCNiLEAST8  "hhi"
+#define SCNiLEAST16 "hi"
+#define SCNiLEAST32 "i"
+#define SCNiLEAST64 "lli"
+
+#define SCNiFAST8   "hhi"
+#define SCNiFAST16  "hi"
+#define SCNiFAST32  "i"
+#define SCNiFAST64  "lli"
+
+#define SCNiMAX     "lli"
+#define SCNiPTR     "i"
+
+#define SCNo8       "hho"
+#define SCNo16      "ho"
+#define SCNo32      "o"
+#define SCNo64      "llo"
+
+#define SCNoLEAST8  "hho"
+#define SCNoLEAST16 "ho"
+#define SCNoLEAST32 "o"
+#define SCNoLEAST64 "llo"
+
+#define SCNoFAST8   "hho"
+#define SCNoFAST16  "ho"
+#define SCNoFAST32  "o"
+#define SCNoFAST64  "llo"
+
+#define SCNoMAX     "llo"
+#define SCNoPTR     "o"
+
+#define SCNu8       "hhu"
+#define SCNu16      "hu"
+#define SCNu32      "u"
+#define SCNu64      "llu"
+
+#define SCNuLEAST8  "hhu"
+#define SCNuLEAST16 "hu"
+#define SCNuLEAST32 "u"
+#define SCNuLEAST64 "llu"
+
+#define SCNuFAST8   "hhu"
+#define SCNuFAST16  "hu"
+#define SCNuFAST32  "u"
+#define SCNuFAST64  "llu"
+
+#define SCNuMAX     "llu"
+#define SCNuPTR     "u"
+
+#define SCNx8       "hhx"
+#define SCNx16      "hx"
+#define SCNx32      "x"
+#define SCNx64      "llx"
+
+#define SCNxLEAST8  "hhx"
+#define SCNxLEAST16 "hx"
+#define SCNxLEAST32 "x"
+#define SCNxLEAST64 "llx"
+
+#define SCNxFAST8   "hhx"
+#define SCNxFAST16  "hx"
+#define SCNxFAST32  "x"
+#define SCNxFAST64  "llx"
+
+#define SCNxMAX     "llx"
+#define SCNxPTR     "x"
+
+#endif /* __ARCH_MISOC_INCLUDE_INTTYPES_H */

arch/misoc/include/irq.h

@@ -0,0 +1,80 @@
+/****************************************************************************
+ * arch/misoc/include/irq.h
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directed but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_MISOC_INCLUDE_IRQ_H
+#define __ARCH_MISOC_INCLUDE_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/irq.h>
+#include <arch/chip/irq.h>
+
+#include <arch/lm32/irq.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+irqstate_t up_irq_save(void);
+void up_irq_restore(irqstate_t flags);
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif /* __ARCH_MISOC_INCLUDE_IRQ_H */

arch/misoc/include/limits.h

@@ -0,0 +1,88 @@
+/****************************************************************************
+ * arch/misoc/include/limits.h
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_MISOC_INCLUDE_LIMITS_H
+#define __ARCH_MISOC_INCLUDE_LIMITS_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define CHAR_BIT    8
+#define SCHAR_MIN   (-SCHAR_MAX - 1)
+#define SCHAR_MAX   127
+#define UCHAR_MAX   255
+
+/* These could be different on machines where char is unsigned */
+
+#ifdef __CHAR_UNSIGNED__
+#define CHAR_MIN    0
+#define CHAR_MAX    UCHAR_MAX
+#else
+#define CHAR_MIN    SCHAR_MIN
+#define CHAR_MAX    SCHAR_MAX
+#endif
+
+#define SHRT_MIN    (-SHRT_MAX - 1)
+#define SHRT_MAX    32767
+#define USHRT_MAX   65535U
+
+/* Integer is four bytes */
+
+#define INT_MIN     (-INT_MAX - 1)
+#define INT_MAX     2147483647
+#define UINT_MAX    4294967295U
+
+/* These change on 32-bit and 64-bit platforms */
+
+#define LONG_MIN    (-LONG_MAX - 1)
+#define LONG_MAX    2147483647L
+#define ULONG_MAX   4294967295UL
+
+#define LLONG_MIN   (-LLONG_MAX - 1)
+#define LLONG_MAX   9223372036854775807LL
+#define ULLONG_MAX  18446744073709551615ULL
+
+/* A pointer is four bytes */
+
+#define PTR_MIN     (-PTR_MAX - 1)
+#define PTR_MAX     2147483647
+#define UPTR_MAX    4294967295U
+
+#endif /* __ARCH_MISOC_INCLUDE_LIMITS_H */

arch/misoc/include/lm32/irq.h

@@ -0,0 +1,205 @@
+/****************************************************************************
+ * arch/misoc/include/lm32/irq.h
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *           Ramtin Amin <keytwo@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_MISOC_INCLUDE_LM32_IRQ_H
+#define __ARCH_MISOC_INCLUDE_LM32_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <arch/types.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* 32 True interrupts plus the sofware interrupt */
+
+#define LM32_NINTERRUPTS 32
+#define LM32_IRQ_SWINT   32
+#define NR_IRQS          33
+
+/* Registers */
+
+#define REG_X0_NDX    0      /* Holds the value zero */
+#define REG_X1_NDX    1      /* General-purpose/argument 0/return value 0 */
+#define REG_X2_NDX    2      /* General-purpose/argument 1/return value 1 */
+#define REG_X3_NDX    3      /* General-purpose/argument 2 */
+#define REG_X4_NDX    4      /* General-purpose/argument 3 */
+#define REG_X5_NDX    5      /* General-purpose/argument 4 */
+#define REG_X6_NDX    6      /* General-purpose/argument 5 */
+#define REG_X7_NDX    7      /* General-purpose/argument 6 */
+#define REG_X8_NDX    8      /* General-purpose/argument 7 */
+#define REG_X9_NDX    9      /* General-purpose */
+#define REG_X10_NDX   10     /* General-purpose */
+#define REG_X11_NDX   11     /* General-purpose */
+#define REG_X12_NDX   12     /* General-purpose */
+#define REG_X13_NDX   13     /* General-purpose */
+#define REG_X14_NDX   14     /* General-purpose */
+#define REG_X15_NDX   15     /* General-purpose */
+#define REG_X16_NDX   16     /* General-purpose */
+#define REG_X17_NDX   17     /* General-purpose */
+#define REG_X18_NDX   18     /* General-purpose */
+#define REG_X19_NDX   19     /* General-purpose */
+#define REG_X20_NDX   20     /* General-purpose */
+#define REG_X21_NDX   21     /* General-purpose */
+#define REG_X22_NDX   22     /* General-purpose */
+#define REG_X23_NDX   23     /* General-purpose */
+#define REG_X24_NDX   24     /* General-purpose */
+#define REG_X25_NDX   25     /* General-purpose */
+#define REG_X26_NDX   26     /* General-purpose/global pointer */
+#define REG_X27_NDX   27     /* General-purpose/frame pointer */
+#define REG_X28_NDX   28     /* Stack pointer */
+#define REG_X29_NDX   29     /* General-purpose/return address */
+#define REG_X30_NDX   30     /* Exception address */
+#define REG_X31_NDX   31     /* Breakpoint address */
+#define REG_X32_NDX   32     /* Reg IE */
+
+/* Interrupt Context register */
+
+#define XCPTCONTEXT_REGS  33
+#define XCPTCONTEXT_SIZE  (4 * XCPTCONTEXT_REGS)
+
+#ifdef __ASSEMBLY__
+#  define REG_X0      (4*REG_X0_NDX)
+#  define REG_X1      (4*REG_X1_NDX)
+#  define REG_X2      (4*REG_X2_NDX)
+#  define REG_X3      (4*REG_X3_NDX)
+#  define REG_X4      (4*REG_X4_NDX)
+#  define REG_X5      (4*REG_X5_NDX)
+#  define REG_X6      (4*REG_X6_NDX)
+#  define REG_X7      (4*REG_X7_NDX)
+#  define REG_X8      (4*REG_X8_NDX)
+#  define REG_X9      (4*REG_X9_NDX)
+#  define REG_X10     (4*REG_X10_NDX)
+#  define REG_X11     (4*REG_X11_NDX)
+#  define REG_X12     (4*REG_X12_NDX)
+#  define REG_X13     (4*REG_X13_NDX)
+#  define REG_X14     (4*REG_X14_NDX)
+#  define REG_X15     (4*REG_X15_NDX)
+#  define REG_X16     (4*REG_X16_NDX)
+#  define REG_X17     (4*REG_X17_NDX)
+#  define REG_X18     (4*REG_X18_NDX)
+#  define REG_X19     (4*REG_X19_NDX)
+#  define REG_X20     (4*REG_X20_NDX)
+#  define REG_X21     (4*REG_X21_NDX)
+#  define REG_X22     (4*REG_X22_NDX)
+#  define REG_X23     (4*REG_X23_NDX)
+#  define REG_X24     (4*REG_X24_NDX)
+#  define REG_X25     (4*REG_X25_NDX)
+#  define REG_X26     (4*REG_X26_NDX)
+#  define REG_X27     (4*REG_X27_NDX)
+#  define REG_X28     (4*REG_X28_NDX)
+#  define REG_X29     (4*REG_X29_NDX)
+#  define REG_X30     (4*REG_X30_NDX)
+#  define REG_X31     (4*REG_X31_NDX)
+#  define REG_INT_CTX (4*REG_X32_NDX)
+#else
+#  define REG_X0       REG_X0_NDX
+#  define REG_X1       REG_X1_NDX
+#  define REG_X2       REG_X2_NDX
+#  define REG_X3       REG_X3_NDX
+#  define REG_X4       REG_X4_NDX
+#  define REG_X5       REG_X5_NDX
+#  define REG_X6       REG_X6_NDX
+#  define REG_X7       REG_X7_NDX
+#  define REG_X8       REG_X8_NDX
+#  define REG_X9       REG_X9_NDX
+#  define REG_X10      REG_X10_NDX
+#  define REG_X11      REG_X11_NDX
+#  define REG_X12      REG_X12_NDX
+#  define REG_X13      REG_X13_NDX
+#  define REG_X14      REG_X14_NDX
+#  define REG_X15      REG_X15_NDX
+#  define REG_X16      REG_X16_NDX
+#  define REG_X17      REG_X17_NDX
+#  define REG_X18      REG_X18_NDX
+#  define REG_X19      REG_X19_NDX
+#  define REG_X20      REG_X20_NDX
+#  define REG_X21      REG_X21_NDX
+#  define REG_X22      REG_X22_NDX
+#  define REG_X23      REG_X23_NDX
+#  define REG_X24      REG_X24_NDX
+#  define REG_X25      REG_X25_NDX
+#  define REG_X26      REG_X26_NDX
+#  define REG_X27      REG_X27_NDX
+#  define REG_X28      REG_X28_NDX
+#  define REG_X29      REG_X29_NDX
+#  define REG_X30      REG_X30_NDX
+#  define REG_X31      REG_X31_NDX
+#  define REG_INT_CTX  REG_X32_NDX
+#endif
+
+/* Register aliases */
+
+#define REG_GP         REG_X26
+#define REG_FP         REG_X27
+#define REG_SP         REG_X28
+#define REG_RA         REG_X29
+#define REG_EA         REG_X30
+#define REG_BA         REG_X31
+
+#define REG_EPC        REG_X30
+
+#define REG_A0         REG_X1
+#define REG_A1         REG_X2
+#define REG_A2         REG_X3
+#define REG_A3         REG_X4
+#define REG_A4         REG_X5
+#define REG_A5         REG_X6
+#define REG_A6         REG_X7
+#define REG_A7         REG_X8
+
+#define REG_IE         REG_INT_CTX
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+struct xcptcontext
+{
+  /* Register save area */
+
+  uint32_t regs[XCPTCONTEXT_REGS];
+};
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ARCH_MISOC_INCLUDE_LM32_IRQ_H */

arch/misoc/include/lm32/syscall.h

@@ -0,0 +1,208 @@
+/****************************************************************************
+ * arch/misoc/include/lm32/syscall.h
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *           Ramtin Amin <keytwo@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directed but, rather, only indirectly
+ * through include/syscall.h or include/sys/sycall.h
+ */
+
+#ifndef __ARCH_MISOC_INCLUDE_LM32_SYSCALL_H
+#define __ARCH_MISOC_INCLUDE_LM32_SYSCALL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+#  include <stdint.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define SYS_syscall 0x00
+
+/* Configuration ********************************************************************/
+/* SYS call 1 and 2 are defined for internal use by the LM32 port (see
+ * arch/miscoc/include/lm32/syscall.h).  In addition, SYS call 3 is the return from
+ * a SYS call in kernel mode.  The first four syscall values must, therefore, be
+ * reserved (0 is not used).
+ */
+
+#ifdef CONFIG_BUILD_KERNEL
+#  ifndef CONFIG_SYS_RESERVED
+#    error "CONFIG_SYS_RESERVED must be defined to the value 4"
+#  elif CONFIG_SYS_RESERVED != 4
+#    error "CONFIG_SYS_RESERVED must have the value 4"
+#  endif
+#endif
+
+/* sys_call macros ******************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/* Context switching system calls ***************************************************/
+
+/* SYS call 0: (not used) */
+
+/* SYS call 1:
+ *
+ * void up_fullcontextrestore(uint32_t *restoreregs) noreturn_function;
+ */
+
+#define SYS_restore_context (1)
+#define up_fullcontextrestore(restoreregs) \
+  (void)sys_call1(SYS_restore_context, (uintptr_t)restoreregs)
+
+/* SYS call 2:
+ *
+ * void up_switchcontext(uint32_t *saveregs, uint32_t *restoreregs);
+ */
+
+#define SYS_switch_context (2)
+#define up_switchcontext(saveregs, restoreregs) \
+  (void)sys_call2(SYS_switch_context, (uintptr_t)saveregs, (uintptr_t)restoreregs)
+
+#ifdef CONFIG_BUILD_KERNEL
+/* SYS call 3:
+ *
+ * void up_syscall_return(void);
+ */
+
+#define SYS_syscall_return (3)
+#define up_syscall_return() (void)sys_call0(SYS_syscall_return)
+
+#endif
+#endif /* __ASSEMBLY__ */
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Inline functions
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Name: up_syscall0
+ *
+ * Description:
+ *   System call SYS_ argument and no additional parameters.
+ *
+ ****************************************************************************/
+
+uintptr_t sys_call0(unsigned int nbr);
+
+/****************************************************************************
+ * Name: up_syscall1
+ *
+ * Description:
+ *   System call SYS_ argument and one additional parameter.
+ *
+ ****************************************************************************/
+
+uintptr_t sys_call1(unsigned int nbr, uintptr_t parm1);
+
+/****************************************************************************
+ * Name: up_syscall2
+ *
+ * Description:
+ *   System call SYS_ argument and two additional parameters.
+ *
+ ****************************************************************************/
+
+uintptr_t sys_call2(unsigned int nbr, uintptr_t parm1, uintptr_t parm2);
+
+/****************************************************************************
+ * Name: up_syscall3
+ *
+ * Description:
+ *   System call SYS_ argument and three additional parameters.
+ *
+ ****************************************************************************/
+
+uintptr_t sys_call3(unsigned int nbr, uintptr_t parm1, uintptr_t parm2,
+                    uintptr_t parm3);
+
+/****************************************************************************
+ * Name: up_syscall4
+ *
+ * Description:
+ *   System call SYS_ argument and four additional parameters.
+ *
+ ****************************************************************************/
+
+uintptr_t sys_call4(unsigned int nbr, uintptr_t parm1, uintptr_t parm2,
+                    uintptr_t parm3, uintptr_t parm4);
+
+/****************************************************************************
+ * Name: up_syscall5
+ *
+ * Description:
+ *   System call SYS_ argument and five additional parameters.
+ *
+ ****************************************************************************/
+
+uintptr_t sys_call5(unsigned int nbr, uintptr_t parm1, uintptr_t parm2,
+                    uintptr_t parm3, uintptr_t parm4, uintptr_t parm5);
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_MISOC_INCLUDE_LM32_SYSCALL_H */

arch/misoc/include/lm32/types.h

@@ -0,0 +1,95 @@
+/****************************************************************************
+ * arch/misoc/include/lm32/types.h
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *           Ramtin Amin <keytwo@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directed but, rather, only indirectly
+ * through stdint.h
+ */
+
+#ifndef __ARCH_MISOC_INCLUDE_LM32_TYPES_H
+#define __ARCH_MISOC_INCLUDE_LM32_TYPES_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Type Declarations
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/* These are the sizes of the standard integer types.  NOTE that these type
+ * names have a leading underscore character.  This file will be included
+ * (indirectly) by include/stdint.h and typedef'ed to the final name without
+ * the underscore character.  This roundabout way of doings things allows
+ * the stdint.h to be removed from the include/ directory in the event that
+ * the user prefers to use the definitions provided by their toolchain header
+ * files
+ */
+
+typedef signed char        _int8_t;
+typedef unsigned char      _uint8_t;
+
+typedef signed short       _int16_t;
+typedef unsigned short     _uint16_t;
+
+typedef signed int         _int32_t;
+typedef unsigned int       _uint32_t;
+
+typedef signed long long   _int64_t;
+typedef unsigned long long _uint64_t;
+#define __INT64_DEFINED
+
+/* A pointer is 4 bytes */
+
+typedef signed int         _intptr_t;
+typedef unsigned int       _uintptr_t;
+
+/* This is the size of the interrupt state save returned by up_irq_save(). */
+
+typedef unsigned int       irqstate_t;
+
+#endif /* __ASSEMBLY__ */
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#endif /* __ARCH_MISOC_INCLUDE_LM32_TYPES_H */

arch/misoc/include/syscall.h

@@ -0,0 +1,53 @@
+/****************************************************************************
+ * arch/misoc/include/syscall.h
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directed but, rather, only indirectly
+ * through include/syscall.h or include/sys/sycall.h
+ */
+
+#ifndef __ARCH_MISOC_INCLUDE_SYSCALL_H
+#define __ARCH_MISOC_INCLUDE_SYSCALL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/* Include LM32 architecture-specific syscall macros */
+
+#ifdef CONFIG_ARCH_CHIP_LM32
+# include <arch/lm32/syscall.h>
+#endif
+
+#endif /* __ARCH_MISOC_INCLUDE_SYSCALL_H */

arch/misoc/include/types.h

@@ -0,0 +1,94 @@
+/****************************************************************************
+ * arch/misoc/include/types.h
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directed but, rather, only indirectly
+ * through stdint.h
+ */
+
+#ifndef __ARCH_MISOC_INCLUDE_TYPESL_H
+#define __ARCH_MISOC_INCLUDE_TYPESL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Type Declarations
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/* These are the sizes of the standard integer types.  NOTE that these type
+ * names have a leading underscore character.  This file will be included
+ * (indirectly) by include/stdint.h and typedef'ed to the final name without
+ * the underscore character.  This roundabout way of doings things allows
+ * the stdint.h to be removed from the include/ directory in the event that
+ * the user prefers to use the definitions provided by their toolchain header
+ * files
+ */
+
+typedef signed char        _int8_t;
+typedef unsigned char      _uint8_t;
+
+typedef signed short       _int16_t;
+typedef unsigned short     _uint16_t;
+
+typedef signed int         _int32_t;
+typedef unsigned int       _uint32_t;
+
+typedef signed long long   _int64_t;
+typedef unsigned long long _uint64_t;
+#define __INT64_DEFINED
+
+/* A pointer is 4 bytes */
+
+typedef signed int         _intptr_t;
+typedef unsigned int       _uintptr_t;
+
+/* This is the size of the interrupt state save returned by up_irq_save(). */
+
+typedef unsigned int       irqstate_t;
+
+#endif /* __ASSEMBLY__ */
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#endif /* __ARCH_MISOC_INCLUDE_TYPESL_H */

arch/misoc/src/.gitignore

@@ -0,0 +1,5 @@
+/.depend
+/Make.dep
+/locked.r
+/board
+/chip

arch/misoc/src/Makefile

@@ -0,0 +1,185 @@
+############################################################################
+# arch/misoc/src/Makefile
+#
+#   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <gnutt@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+-include $(TOPDIR)/Make.defs
+-include chip/Make.defs
+
+ARCH_SUBDIR = lm32
+
+ifeq ($(CONFIG_WINDOWS_NATIVE),y)
+  ARCH_SRCDIR = $(TOPDIR)\arch\$(CONFIG_ARCH)\src
+  NUTTX = "$(TOPDIR)\nuttx$(EXEEXT)"
+  INCLUDES += -I "$(ARCH_SRCDIR)\chip"
+  INCLUDES += -I "$(ARCH_SRCDIR)\common"
+  INCLUDES += -I "$(ARCH_SRCDIR)\$(ARCH_SUBDIR)"
+  INCLUDES += -I "$(TOPDIR)\sched"
+else
+  ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src
+ifeq ($(WINTOOL),y)
+  NUTTX = "${shell cygpath -w $(TOPDIR)/nuttx$(EXEEXT)}"
+  INCLUDES += -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}"
+  INCLUDES += -I "${shell cygpath -w $(ARCH_SRCDIR)/common}"
+  INCLUDES += -I "${shell cygpath -w $(ARCH_SRCDIR)/$(ARCH_SUBDIR)}"
+  INCLUDES += -I "${shell cygpath -w $(TOPDIR)/sched}"
+else
+  NUTTX = "$(TOPDIR)/nuttx$(EXEEXT)"
+  INCLUDES += -I "$(ARCH_SRCDIR)/chip"
+  INCLUDES += -I "$(ARCH_SRCDIR)/common"
+  INCLUDES += -I "$(ARCH_SRCDIR)/$(ARCH_SUBDIR)"
+  INCLUDES += -I "$(TOPDIR)/sched"
+endif
+endif
+
+CPPFLAGS += $(INCLUDES) $(EXTRADEFINES)
+CFLAGS += $(INCLUDES) $(EXTRADEFINES)
+CXXFLAGS += $(INCLUDES) $(EXTRADEFINES)
+AFLAGS += $(INCLUDES) $(EXTRADEFINES)
+
+HEAD_OBJ = $(HEAD_ASRC:.S=$(OBJEXT))
+STARTUP_OBJS ?= $(HEAD_OBJ)
+
+ASRCS = $(CHIP_ASRCS) $(CMN_ASRCS)
+AOBJS = $(ASRCS:.S=$(OBJEXT))
+
+CSRCS = $(CHIP_CSRCS) $(CMN_CSRCS)
+COBJS = $(CSRCS:.c=$(OBJEXT))
+
+SRCS = $(ASRCS) $(CSRCS)
+OBJS = $(AOBJS) $(COBJS)
+
+# Override in Make.defs if linker is not 'ld'
+
+LDSTARTGROUP ?= --start-group
+LDENDGROUP ?= --end-group
+
+LDFLAGS += $(ARCHSCRIPT)
+EXTRA_LIBS ?=
+LINKLIBS ?=
+
+ifeq ($(CONFIG_WINDOWS_NATIVE),y)
+  BOARDMAKE = $(if $(wildcard .\board\Makefile),y,)
+  LIBPATHS += -L"$(TOPDIR)\lib"
+ifeq ($(BOARDMAKE),y)
+  LIBPATHS += -L"$(TOPDIR)\arch\$(CONFIG_ARCH)\src\board"
+endif
+
+else
+  BOARDMAKE = $(if $(wildcard ./board/Makefile),y,)
+
+ifeq ($(WINTOOL),y)
+  LIBPATHS += -L"${shell cygpath -w "$(TOPDIR)/lib"}"
+ifeq ($(BOARDMAKE),y)
+  LIBPATHS += -L"${shell cygpath -w "$(TOPDIR)/arch/$(CONFIG_ARCH)/src/board"}"
+endif
+
+else
+  LIBPATHS += -L"$(TOPDIR)/lib"
+ifeq ($(BOARDMAKE),y)
+  LIBPATHS += -L"$(TOPDIR)/arch/$(CONFIG_ARCH)/src/board"
+endif
+endif
+endif
+
+LDLIBS = $(patsubst %.a,%,$(patsubst lib%,-l%,$(LINKLIBS)))
+ifeq ($(BOARDMAKE),y)
+  LDLIBS += -lboard
+endif
+
+LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}"
+
+VPATH = chip:common:$(ARCH_SUBDIR)
+
+all: $(HEAD_OBJ) libarch$(LIBEXT)
+
+.PHONY: board/libboard$(LIBEXT)
+
+$(AOBJS) $(HEAD_OBJ): %$(OBJEXT): %.S
+	$(call ASSEMBLE, $<, $@)
+
+$(COBJS): %$(OBJEXT): %.c
+	$(call COMPILE, $<, $@)
+
+libarch$(LIBEXT): $(OBJS)
+	$(call ARCHIVE, $@, $(OBJS))
+
+board/libboard$(LIBEXT):
+	$(Q) $(MAKE) -C board TOPDIR="$(TOPDIR)" libboard$(LIBEXT) EXTRADEFINES=$(EXTRADEFINES)
+
+nuttx$(EXEEXT): $(HEAD_OBJ) board/libboard$(LIBEXT)
+	$(Q) $(LD) --entry=__start $(LDFLAGS) $(LIBPATHS) -o $(NUTTX) $(HEAD_OBJ) $(EXTRA_OBJS) \
+		$(LDSTARTGROUP) $(LDLIBS) $(EXTRA_LIBS) $(LIBGCC) $(LDENDGROUP)
+ifneq ($(CONFIG_WINDOWS_NATIVE),y)
+	$(Q) $(NM) $(NUTTX) | \
+	grep -v '\(compiled\)\|\(\$(OBJEXT)$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \
+	sort > $(TOPDIR)/System.map
+endif
+
+# This is part of the top-level export target
+
+export_startup: board/libboard$(LIBEXT) $(STARTUP_OBJS)
+	$(Q) if [ -d "$(EXPORT_DIR)/startup" ]; then \
+		cp -f $(STARTUP_OBJS) "$(EXPORT_DIR)/startup"; \
+	 else \
+		echo "$(EXPORT_DIR)/startup does not exist"; \
+		exit 1; \
+	 fi
+
+# Dependencies
+
+.depend: Makefile chip/Make.defs $(SRCS)
+ifeq ($(BOARDMAKE),y)
+	$(Q) $(MAKE) -C board TOPDIR="$(TOPDIR)" depend
+endif
+	$(Q) $(MKDEP) --dep-path chip --dep-path common --dep-path $(ARCH_SUBDIR) \
+	 "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep
+	$(Q) touch $@
+
+depend: .depend
+
+clean:
+ifeq ($(BOARDMAKE),y)
+	$(Q) $(MAKE) -C board TOPDIR="$(TOPDIR)" clean
+endif
+	$(call DELFILE, libarch$(LIBEXT))
+	$(call CLEAN)
+
+distclean: clean
+ifeq ($(BOARDMAKE),y)
+	$(Q) $(MAKE) -C board TOPDIR="$(TOPDIR)" distclean
+endif
+	$(call DELFILE, Make.dep)
+	$(call DELFILE, .depend)
+
+-include Make.dep

arch/misoc/src/common/hw/common.h

@@ -0,0 +1,49 @@
+/****************************************************************************
+ *  arch/misoc/src/common/hw/common.h
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Author: Ramtin Amin <keytwo@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_MISOC_SRC_COMMON_HW_COMMON_H
+#define __ARCH_MISOC_SRC_COMMON_HW_COMMON_H
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifdef __ASSEMBLER__
+#  define MMPTR(x) x
+#else
+#  define MMPTR(x) (*((volatile unsigned int *)(x)))
+#endif
+
+#endif /* __ARCH_MISOC_SRC_COMMON_HW_COMMON_H */

arch/misoc/src/common/hw/ethmac_mem.h

@@ -0,0 +1,54 @@
+/****************************************************************************
+ *  arch/misoc/src/common/hw/emac_mem.h
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Author: Ramtin Amin <keytwo@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_MISOC_SRC_COMMON_HW_EMAC_MEM_H
+#define __ARCH_MISOC_SRC_COMMON_HW_EMAC_MEM_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <arch/board/generated/mem.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define ETHMAC_RX0_BASE	ETHMAC_BASE
+#define ETHMAC_RX1_BASE	(ETHMAC_BASE+0x0800)
+#define ETHMAC_TX0_BASE	(ETHMAC_BASE+0x1000)
+#define ETHMAC_TX1_BASE	(ETHMAC_BASE+0x1800)
+
+#endif /* __ARCH_MISOC_SRC_COMMON_HW_EMAC_MEM_H */

arch/misoc/src/common/hw/flags.h

@@ -0,0 +1,79 @@
+/****************************************************************************
+ *  arch/misoc/src/common/hw/emac_mem.h
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Author: Ramtin Amin <keytwo@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_MISOC_SRC_COMMON_HW_FLAGS_H
+#define __ARCH_MISOC_SRC_COMMON_HW_FLAGS_H
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define UART_EV_TX                      0x1
+#define UART_EV_RX                      0x2
+
+#define DFII_CONTROL_SEL                0x01
+#define DFII_CONTROL_CKE                0x02
+#define DFII_CONTROL_ODT                0x04
+#define DFII_CONTROL_RESET_N            0x08
+
+#define DFII_COMMAND_CS                 0x01
+#define DFII_COMMAND_WE                 0x02
+#define DFII_COMMAND_CAS                0x04
+#define DFII_COMMAND_RAS                0x08
+#define DFII_COMMAND_WRDATA             0x10
+#define DFII_COMMAND_RDDATA             0x20
+
+#define ETHMAC_EV_SRAM_WRITER           0x1
+#define ETHMAC_EV_SRAM_READER           0x1
+
+#define CLKGEN_STATUS_BUSY              0x1
+#define CLKGEN_STATUS_PROGDONE          0x2
+#define CLKGEN_STATUS_LOCKED            0x4
+
+#define DVISAMPLER_TOO_LATE             0x1
+#define DVISAMPLER_TOO_EARLY            0x2
+
+#define DVISAMPLER_DELAY_MASTER_CAL     0x01
+#define DVISAMPLER_DELAY_MASTER_RST     0x02
+#define DVISAMPLER_DELAY_SLAVE_CAL      0x04
+#define DVISAMPLER_DELAY_SLAVE_RST      0x08
+#define DVISAMPLER_DELAY_INC            0x10
+#define DVISAMPLER_DELAY_DEC            0x20
+
+#define DVISAMPLER_SLOT_EMPTY           0
+#define DVISAMPLER_SLOT_LOADED          1
+#define DVISAMPLER_SLOT_PENDING         2
+
+#endif /* __ARCH_MISOC_SRC_COMMON_HW_FLAGS_H */

arch/misoc/src/common/misoc.h

@@ -0,0 +1,120 @@
+/****************************************************************************
+ * arch/misoc/src/common/serial.h
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *           Ramtin Amin <keytwo@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_MISOC_SRC_COMMON_MISOC_H
+#define __ARCH_MISOC_SRC_COMMON_MISOC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <stdint.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Low-level register access */
+
+#define getreg8(a)            (*(volatile uint8_t *)(a))
+#define putreg8(v,a)          (*(volatile uint8_t *)(a) = (v))
+#define getreg16(a)           (*(volatile uint16_t *)(a))
+#define putreg16(v,a)         (*(volatile uint16_t *)(a) = (v))
+#define getreg32(a)           (*(volatile uint32_t *)(a))
+#define putreg32(v,a)         (*(volatile uint32_t *)(a) = (v))
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Name: up_serialinit
+ *
+ * Description:
+ *   Register serial console and serial ports.  This assumes that
+ *   misoc_earlyserialinit was called previously.
+ *
+ ****************************************************************************/
+
+void misoc_serial_initialize(void);
+
+/****************************************************************************
+ * Name: misoc_puts
+ *
+ * Description:
+ *   This is a low-level helper function used to support debug.
+ *
+ ****************************************************************************/
+
+void misoc_puts(const char *str);
+
+/****************************************************************************
+ * Name: misoc_lowputc
+ *
+ * Description:
+ *   Low-level, blocking character output the the serial console.
+ *
+ ****************************************************************************/
+
+void misoc_lowputc(char ch);
+
+/****************************************************************************
+ * Name: misoc_lowputs
+ *
+ * Description:
+ *   This is a low-level helper function used to support debug.
+ *
+ ****************************************************************************/
+
+void misoc_lowputs(const char *str);
+
+/****************************************************************************
+ * Name: modifyreg[N]
+ *
+ * Description:
+ *   Atomic modification of registers.
+ *
+ ****************************************************************************/
+
+void modifyreg8(unsigned int addr, uint8_t clearbits, uint8_t setbits);
+void modifyreg16(unsigned int addr, uint16_t clearbits, uint16_t setbits);
+void modifyreg32(unsigned int addr, uint32_t clearbits, uint32_t setbits);
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_MISOC_SRC_COMMON_MISOC_H */

arch/misoc/src/common/misoc_lowputs.c

@@ -0,0 +1,62 @@
+/****************************************************************************
+ * arch/misoc/src/common/misoc_lowputs.c
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "misoc.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: misoc_lowputs
+ *
+ * Description:
+ *   This is a low-level helper function used to support debug.
+ *
+ ****************************************************************************/
+
+void misoc_lowputs(const char *str)
+{
+  while (*str)
+    {
+      misoc_lowputc(*str++);
+    }
+}

arch/misoc/src/common/misoc_mdelay.c

@@ -0,0 +1,70 @@
+/****************************************************************************
+ *  arch/misoc/src/common/misoc_mdelay.c
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_mdelay
+ *
+ * Description:
+ *   Delay inline for the requested number of milliseconds.
+ *   *** NOT multi-tasking friendly ***
+ *
+ * ASSUMPTIONS:
+ *   The setting CONFIG_BOARD_LOOPSPERMSEC has been calibrated
+ *
+ ****************************************************************************/
+
+void up_mdelay(unsigned int milliseconds)
+{
+  volatile int i;
+  volatile int j;
+
+  for (i = 0; i < milliseconds; i++)
+    {
+      for (j = 0; j < CONFIG_BOARD_LOOPSPERMSEC; j++)
+        {
+        }
+    }
+}

arch/misoc/src/common/misoc_modifyreg16.c

@@ -0,0 +1,73 @@
+/****************************************************************************
+ * arch/misoc/src/common/misoc_modifyreg16.c
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <debug.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+
+#include "misoc.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: modifyreg16
+ *
+ * Description:
+ *   Atomically modify the specified bits in a memory mapped register
+ *
+ ****************************************************************************/
+
+void modifyreg16(unsigned int addr, uint16_t clearbits, uint16_t setbits)
+{
+  irqstate_t flags;
+  uint16_t   regval;
+
+  flags   = enter_critical_section();
+  regval  = getreg16(addr);
+  regval &= ~clearbits;
+  regval |= setbits;
+  putreg16(regval, addr);
+  leave_critical_section(flags);
+}