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EFM32: More USB register name corrections. Still incomplete

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This commit is contained in:
Gregory Nutt 2014-11-12 10:43:29 -06:00
parent 365afd95a6
commit e424ddbabd
3 changed files with 47 additions and 34 deletions
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29
arch/arm/src/efm32/chip/efm32_usb.h
View File

@ -96,11 +96,12 @@
#define EFM32_USB_GRXSTSP_OFFSET 0x3c020 /* Receive Status Read and Pop Register */
#define EFM32_USB_GRXFSIZ_OFFSET 0x3c024 /* Receive FIFO Size Register */
#define EFM32_USB_GNPTXFSIZ_OFFSET 0x3c028 /* Non-periodic Transmit FIFO Size Register */
#define EFM32_USB_DIEPTXF0_OFFSET 0x3c028 /* Endpoint 0 Transmit FIFO size */
#define EFM32_USB_GNPTXSTS_OFFSET 0x3c02c /* Non-periodic Transmit FIFO/Queue Status Register */
#define EFM32_USB_GDFIFOCFG_OFFSET 0x3c05c /* Global DFIFO Configuration Register */
#define EFM32_USB_HPTXFSIZ_OFFSET 0x3c100 /* Host Periodic Transmit FIFO Size Register */
#define EFM32_USB_DIEPTXF_OFFSET(n) (0x3c104 + ((n) << 2))
#define EFM32_USB_DIEPTXF_OFFSET(n) (0x3c104 + (((n)-1) << 2))
#define EFM32_USB_DIEPTXF1_OFFSET 0x3c104 /* Device IN Endpoint Transmit FIFO 1 Size Register */
#define EFM32_USB_DIEPTXF2_OFFSET 0x3c108 /* Device IN Endpoint Transmit FIFO 2 Size Register */
#define EFM32_USB_DIEPTXF3_OFFSET 0x3c10c /* Device IN Endpoint Transmit FIFO 3 Size Register */
@ -299,17 +300,18 @@
#define EFM32_USB_GRXSTSP (EFM32_USB_BASE+EFM32_USB_GRXSTSP_OFFSET)
#define EFM32_USB_GRXFSIZ (EFM32_USB_BASE+EFM32_USB_GRXFSIZ_OFFSET)
#define EFM32_USB_GNPTXFSIZ (EFM32_USB_BASE+EFM32_USB_GNPTXFSIZ_OFFSET)
#define EFM32_USB_DIEPTXF0 (EFM32_USB_BASE+EFM32_USB_DIEPTXF0_OFFSET)
#define EFM32_USB_GNPTXSTS (EFM32_USB_BASE+EFM32_USB_GNPTXSTS_OFFSET)
#define EFM32_USB_GDFIFOCFG (EFM32_USB_BASE+EFM32_USB_GDFIFOCFG_OFFSET)
#define EFM32_USB_HPTXFSIZ (EFM32_USB_BASE+EFM32_USB_HPTXFSIZ_OFFSET)
#define EFM32_USB_DIEPTXF_BASE(n) (EFM32_USB_BASE+EFM32_USB_DIEPTXF_OFFSET(n))
#define EFM32_USB_DIEPTXF1_BASE (EFM32_USB_BASE+EFM32_USB_DIEPTXF1_OFFSET)
#define EFM32_USB_DIEPTXF2_BASE (EFM32_USB_BASE+EFM32_USB_DIEPTXF2_OFFSET)
#define EFM32_USB_DIEPTXF3_BASE (EFM32_USB_BASE+EFM32_USB_DIEPTXF3_OFFSET)
#define EFM32_USB_DIEPTXF4_BASE (EFM32_USB_BASE+EFM32_USB_DIEPTXF4_OFFSET)
#define EFM32_USB_DIEPTXF5_BASE (EFM32_USB_BASE+EFM32_USB_DIEPTXF5_OFFSET)
#define EFM32_USB_DIEPTXF6_BASE (EFM32_USB_BASE+EFM32_USB_DIEPTXF6_OFFSET)
#define EFM32_USB_DIEPTXF(n) (EFM32_USB_BASE+EFM32_USB_DIEPTXF_OFFSET(n))
#define EFM32_USB_DIEPTXF1 (EFM32_USB_BASE+EFM32_USB_DIEPTXF1_OFFSET)
#define EFM32_USB_DIEPTXF2 (EFM32_USB_BASE+EFM32_USB_DIEPTXF2_OFFSET)
#define EFM32_USB_DIEPTXF3 (EFM32_USB_BASE+EFM32_USB_DIEPTXF3_OFFSET)
#define EFM32_USB_DIEPTXF4 (EFM32_USB_BASE+EFM32_USB_DIEPTXF4_OFFSET)
#define EFM32_USB_DIEPTXF5 (EFM32_USB_BASE+EFM32_USB_DIEPTXF5_OFFSET)
#define EFM32_USB_DIEPTXF6 (EFM32_USB_BASE+EFM32_USB_DIEPTXF6_OFFSET)
#define EFM32_USB_HCFG (EFM32_USB_BASE+EFM32_USB_HCFG_OFFSET)
#define EFM32_USB_HFIR (EFM32_USB_BASE+EFM32_USB_HFIR_OFFSET)
@ -1324,6 +1326,17 @@
#define _USB_GNPTXFSIZ_NPTXFINEPTXF0DEP_DEFAULT 0x00000200UL /* Mode DEFAULT for USB_GNPTXFSIZ */
#define USB_GNPTXFSIZ_NPTXFINEPTXF0DEP_DEFAULT (_USB_GNPTXFSIZ_NPTXFINEPTXF0DEP_DEFAULT << 16) /* Shifted mode DEFAULT for USB_GNPTXFSIZ */
/* Bit fields for USB DIEPTXF0 */
#define _USB_DIEPTXF0_TXFSTADDR_SHIFT 0 /* Shift value for USB_NPTXFSTADDR */
#define _USB_DIEPTXF0_TXFSTADDR_MASK 0x3FFUL /* Bit mask for USB_NPTXFSTADDR */
#define _USB_DIEPTXF0_TXFSTADDR_DEFAULT 0x00000200UL /* Mode DEFAULT for USB_GNPTXFSIZ */
#define USB_DIEPTXF0_TXFSTADDR_DEFAULT (_USB_DIEPTXF0_TXFSTADDR_DEFAULT << 0) /* Shifted mode DEFAULT for USB_GNPTXFSIZ */
#define _USB_DIEPTXF0_TXFINEPTXF0DEP_SHIFT 16 /* Shift value for USB_NPTXFINEPTXF0DEP */
#define _USB_DIEPTXF0_TXFINEPTXF0DEP_MASK 0xFFFF0000UL /* Bit mask for USB_NPTXFINEPTXF0DEP */
#define _USB_DIEPTXF0_TXFINEPTXF0DEP_DEFAULT 0x00000200UL /* Mode DEFAULT for USB_GNPTXFSIZ */
#define USB_DIEPTXF0_TXFINEPTXF0DEP_DEFAULT (_USB_DIEPTXF0_TXFINEPTXF0DEP_DEFAULT << 16) /* Shifted mode DEFAULT for USB_GNPTXFSIZ */
/* Bit fields for USB GNPTXSTS */
#define _USB_GNPTXSTS_RESETVALUE 0x00080200UL /* Default value for USB_GNPTXSTS */

50
arch/arm/src/efm32/efm32_usbdev.c
View File

@ -1,5 +1,5 @@
/*******************************************************************************
* arch/arm/src/efm32/efm32_otgfsdev.c
* arch/arm/src/efm32/efm32_usbdev.c
*
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -3351,7 +3351,7 @@ static inline void efm32_isocininterrupt(FAR struct efm32_usbdev_s *priv)
*/
efm32_req_complete(privep, -EIO);
#warning "Will clear USB_DIEPCTL_USBAEP too"
#warning "Will clear USB_DIEPCTL_USBACTEP too"
efm32_epin_disable(privep);
break;
}
@ -3433,7 +3433,7 @@ static inline void efm32_isocoutinterrupt(FAR struct efm32_usbdev_s *priv)
*/
efm32_req_complete(privep, -EIO);
#warning "Will clear USB_DOEPCTL_USBAEP too"
#warning "Will clear USB_DOEPCTL_USBACTEP too"
efm32_epout_disable(privep);
break;
}
@ -3816,17 +3816,17 @@ static int efm32_epout_configure(FAR struct efm32_ep_s *privep, uint8_t eptype,
regaddr = EFM32_USB_DOEPCTL(privep->epphy);
regval = efm32_getreg(regaddr);
if ((regval & USB_DOEPCTL_USBAEP) == 0)
if ((regval & USB_DOEPCTL_USBACTEP) == 0)
{
if (regval & USB_DOEPCTL_NAKSTS)
{
regval |= USB_DOEPCTL_CNAK;
}
regval &= ~(_USB_DOEPCTL_MPS_MASK | _USB_DOEPCTL_EPTYP_MASK);
regval &= ~(_USB_DOEPCTL_MPS_MASK | _USB_DOEPCTL_EPTYPE_MASK);
regval |= mpsiz;
regval |= (eptype << _USB_DOEPCTL_EPTYP_SHIFT);
regval |= (USB_DOEPCTL_SD0PID | USB_DOEPCTL_USBAEP);
regval |= (eptype << _USB_DOEPCTL_EPTYPE_SHIFT);
regval |= (USB_DOEPCTL_SETD0PIDEF | USB_DOEPCTL_USBACTEP);
efm32_putreg(regval, regaddr);
/* Save the endpoint configuration */
@ -3912,18 +3912,18 @@ static int efm32_epin_configure(FAR struct efm32_ep_s *privep, uint8_t eptype,
regaddr = EFM32_USB_DIEPCTL(privep->epphy);
regval = efm32_getreg(regaddr);
if ((regval & USB_DIEPCTL_USBAEP) == 0)
if ((regval & USB_DIEPCTL_USBACTEP) == 0)
{
if (regval & USB_DIEPCTL_NAKSTS)
{
regval |= USB_DIEPCTL_CNAK;
}
regval &= ~(_USB_DIEPCTL_MPS_MASK | _USB_DIEPCTL_EPTYP_MASK | _USB_DIEPCTL_TXFNUM_MASK);
regval &= ~(_USB_DIEPCTL_MPS_MASK | _USB_DIEPCTL_EPTYPE_MASK | _USB_DIEPCTL_TXFNUM_MASK);
regval |= mpsiz;
regval |= (eptype << _USB_DIEPCTL_EPTYP_SHIFT);
regval |= (eptype << _USB_DIEPCTL_EPTYPE_SHIFT);
regval |= (eptype << _USB_DIEPCTL_TXFNUM_SHIFT);
regval |= (USB_DIEPCTL_SD0PID | USB_DIEPCTL_USBAEP);
regval |= (USB_DIEPCTL_SETD0PIDEF | USB_DIEPCTL_USBACTEP);
efm32_putreg(regval, regaddr);
/* Save the endpoint configuration */
@ -4037,7 +4037,7 @@ static void efm32_epout_disable(FAR struct efm32_ep_s *privep)
regaddr = EFM32_USB_DOEPCTL(privep->epphy);
regval = efm32_getreg(regaddr);
regval &= ~USB_DOEPCTL_USBAEP;
regval &= ~USB_DOEPCTL_USBACTEP;
regval |= (USB_DOEPCTL_EPDIS | USB_DOEPCTL_SNAK);
efm32_putreg(regval, regaddr);
@ -4098,7 +4098,7 @@ static void efm32_epin_disable(FAR struct efm32_ep_s *privep)
regaddr = EFM32_USB_DIEPCTL(privep->epphy);
regval = efm32_getreg(regaddr);
if ((regval & USB_DIEPCTL_USBAEP) == 0)
if ((regval & USB_DIEPCTL_USBACTEP) == 0)
{
return;
}
@ -4118,7 +4118,7 @@ static void efm32_epin_disable(FAR struct efm32_ep_s *privep)
regaddr = EFM32_USB_DIEPCTL(privep->epphy);
regval = efm32_getreg(regaddr);
regval &= ~USB_DIEPCTL_USBAEP;
regval &= ~USB_DIEPCTL_USBACTEP;
regval |= (USB_DIEPCTL_EPDIS | USB_DIEPCTL_SNAK);
efm32_putreg(regval, regaddr);
@ -4139,7 +4139,7 @@ static void efm32_epin_disable(FAR struct efm32_ep_s *privep)
flags = irqsave();
regaddr = EFM32_USB_DIEPCTL(privep->epphy);
regval = efm32_getreg(regaddr);
regval &= ~USB_DIEPCTL_USBAEP;
regval &= ~USB_DIEPCTL_USBACTEP;
regval |= (USB_DIEPCTL_EPDIS | USB_DIEPCTL_SNAK);
efm32_putreg(regval, regaddr);
@ -4589,7 +4589,7 @@ static int efm32_ep_clrstall(FAR struct efm32_ep_s *privep)
regaddr = EFM32_USB_DIEPCTL(privep->epphy);
stallbit = USB_DIEPCTL_STALL;
data0bit = USB_DIEPCTL_SD0PID;
data0bit = USB_DIEPCTL_SETD0PIDEF;
}
else
{
@ -4597,7 +4597,7 @@ static int efm32_ep_clrstall(FAR struct efm32_ep_s *privep)
regaddr = EFM32_USB_DOEPCTL(privep->epphy);
stallbit = USB_DOEPCTL_STALL;
data0bit = USB_DOEPCTL_SD0PID;
data0bit = USB_DOEPCTL_SETD0PIDEF;
}
/* Clear the stall bit */
@ -5272,29 +5272,29 @@ static void efm32_hwinitialize(FAR struct efm32_usbdev_s *priv)
/* EP0 TX */
address = EFM32_RXFIFO_WORDS;
regval = (address << _USB_DIEPTXF0_TX0FD_SHIFT) |
(EFM32_EP0_TXFIFO_WORDS << _USB_DIEPTXF0_TX0FSA_SHIFT);
regval = (address << _USB_DIEPTXF0_TXFSTADDR_SHIFT) |
(EFM32_EP0_TXFIFO_WORDS << _USB_DIEPTXF0_TXFINEPTXF0DEP_SHIFT);
efm32_putreg(regval, EFM32_USB_DIEPTXF0);
/* EP1 TX */
address += EFM32_EP0_TXFIFO_WORDS;
regval = (address << _USB_DIEPTXF_INEPTXSA_SHIFT) |
(EFM32_EP1_TXFIFO_WORDS << _USB_DIEPTXF_INEPTXFD_SHIFT);
regval = (address << _USB_DIEPTXF1_INEPNTXFSTADDR_SHIFT) |
(EFM32_EP1_TXFIFO_WORDS << _USB_DIEPTXF1_INEPNTXFDEP_SHIFT);
efm32_putreg(regval, EFM32_USB_DIEPTXF1);
/* EP2 TX */
address += EFM32_EP1_TXFIFO_WORDS;
regval = (address << _USB_DIEPTXF_INEPTXSA_SHIFT) |
(EFM32_EP2_TXFIFO_WORDS << _USB_DIEPTXF_INEPTXFD_SHIFT);
regval = (address << _USB_DIEPTXF2_INEPNTXFSTADDR_SHIFT) |
(EFM32_EP2_TXFIFO_WORDS << _USB_DIEPTXF2_INEPNTXFDEP_SHIFT);
efm32_putreg(regval, EFM32_USB_DIEPTXF2);
/* EP3 TX */
address += EFM32_EP2_TXFIFO_WORDS;
regval = (address << _USB_DIEPTXF_INEPTXSA_SHIFT) |
(EFM32_EP3_TXFIFO_WORDS << _USB_DIEPTXF_INEPTXFD_SHIFT);
regval = (address << _USB_DIEPTXF3_INEPNTXFSTADDR_SHIFT) |
(EFM32_EP3_TXFIFO_WORDS << _USB_DIEPTXF3_INEPNTXFDEP_SHIFT);
efm32_putreg(regval, EFM32_USB_DIEPTXF3);
/* Flush the FIFOs */

2
arch/arm/src/efm32/efm32_usbhost.c
View File

@ -1,5 +1,5 @@
/*******************************************************************************
* arch/arm/src/efm32/efm32_otgfshost.c
* arch/arm/src/efm32/efm32_usbhost.c
*
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>