Merge remote-tracking branch 'origin/master' into photon

arch/arm/src/efm32/efm32_i2c.c

@@ -220,7 +220,6 @@ struct efm32_i2c_config_s
   uint32_t scl_pin;           /* GPIO configuration for SCL as SCL */
   uint32_t sda_pin;           /* GPIO configuration for SDA as SDA */
 #ifndef CONFIG_I2C_POLLED
-  int (*isr) (int, void *, void *);   /* Interrupt handler */
   uint32_t irq;               /* Event IRQ */
 #endif
 };
@@ -294,15 +293,10 @@ static void efm32_i2c_tracedump(FAR struct efm32_i2c_priv_s *priv);
 static void efm32_i2c_setclock(FAR struct efm32_i2c_priv_s *priv,
                                uint32_t frequency);
 
-static int efm32_i2c_isr(struct efm32_i2c_priv_s *priv);
+static int efm32_i2c_isr_process(struct efm32_i2c_priv_s *priv);
 
 #ifndef CONFIG_I2C_POLLED
-#ifdef CONFIG_EFM32_I2C0
+static int efm32_i2c_isr(int irq, void *context, FAR void *arg);
-static int efm32_i2c0_isr(int irq, void *context, FAR void *arg);
-#endif
-#ifdef CONFIG_EFM32_I2C1
-static int efm32_i2c1_isr(int irq, void *context, FAR void *arg);
-#endif
 #endif /* !CONFIG_I2C_POLLED */
 
 static void efm32_i2c_hwreset(FAR struct efm32_i2c_priv_s *priv);
@@ -343,7 +337,6 @@ static const struct efm32_i2c_config_s efm32_i2c0_config =
   .scl_pin = BOARD_I2C0_SCL,
   .sda_pin = BOARD_I2C0_SDA,
 #ifndef CONFIG_I2C_POLLED
-  .isr = efm32_i2c0_isr,
   .irq = EFM32_IRQ_I2C0
 #endif
 };
@@ -371,7 +364,6 @@ static const struct efm32_i2c_config_s efm32_i2c1_config =
   .scl_pin = BOARD_I2C1_SCL,
   .sda_pin = BOARD_I2C1_SDA,
 #ifndef CONFIG_I2C_POLLED
-  .isr = efm32_i2c1_isr,
   .irq = EFM32_IRQ_I2C1
 #endif
 };
@@ -632,7 +624,7 @@ static inline int efm32_i2c_sem_waitdone(FAR struct efm32_i2c_priv_s *priv)
        * that it is done.
        */
 
-      efm32_i2c_isr(priv);
+      efm32_i2c_isr_process(priv);
 
       /* Calculate the elapsed time */
 
@@ -869,14 +861,14 @@ static void efm32_i2c_setclock(FAR struct efm32_i2c_priv_s *priv,
 }
 
 /****************************************************************************
- * Name: efm32_i2c_isr
+ * Name: efm32_i2c_isr_process
  *
  * Description:
  *  Common Interrupt Service Routine
  *
  ****************************************************************************/
 
-static int efm32_i2c_isr(struct efm32_i2c_priv_s *priv)
+static int efm32_i2c_isr_process(struct efm32_i2c_priv_s *priv)
 {
   for (; ; )
     {
@@ -1279,44 +1271,24 @@ done:
   return OK;
 }
 
+/****************************************************************************
+ * Name: efm32_i2c_isr
+ *
+ * Description:
+ *   Common I2C interrupt service routine
+ *
+ ****************************************************************************/
+
 #ifndef CONFIG_I2C_POLLED
-
+static int efm32_i2c_isr(int irq, void *context, FAR void *arg)
-/****************************************************************************
- * Name: efm32_i2c0_isr
- *
- * Description:
- *   I2C0 interrupt service routine
- *
- ****************************************************************************/
-
-#ifdef CONFIG_EFM32_I2C0
-static int efm32_i2c0_isr(int irq, void *context, FAR void *arg)
 {
-  return efm32_i2c_isr(&efm32_i2c0_priv);
+  struct efm32_i2c_priv_s *priv = (struct efm32_i2c_priv_s *)arg;
+
+  DEBUGASSERT(priv != NULL);
+  return efm32_i2c_isr_process(priv);
 }
 #endif
 
-/****************************************************************************
- * Name: efm32_i2c1_isr
- *
- * Description:
- *   I2C1 interrupt service routine
- *
- ****************************************************************************/
-
-#ifdef CONFIG_EFM32_I2C1
-static int efm32_i2c1_isr(int irq, void *context, FAR void *arg)
-{
-  return efm32_i2c_isr(&efm32_i2c1_priv);
-}
-#endif
-
-#endif
-
-/****************************************************************************
- * Private Initialization and Deinitialization
- ****************************************************************************/
-
 /****************************************************************************
  * Name: efm32_i2c_hwreset
  *
@@ -1389,7 +1361,7 @@ static int efm32_i2c_init(FAR struct efm32_i2c_priv_s *priv)
   /* Attach ISRs */
 
 #ifndef CONFIG_I2C_POLLED
-  irq_attach(priv->config->irq, priv->config->isr, NULL);
+  irq_attach(priv->config->irq, efm32_i2c_isr, priv);
   up_enable_irq(priv->config->irq);
 #endif
 
@@ -1523,7 +1495,7 @@ static int efm32_i2c_transfer(FAR struct i2c_master_s *dev,
    * be enabled in efm32_i2c_sem_waitdone if CONFIG_I2C_POLLED is NOT defined
    */
 
-  efm32_i2c_isr(priv);
+  efm32_i2c_isr_process(priv);
 
   /* Wait for an ISR, if there was a timeout, fetch latest status to get the
    * BUSY flag.

arch/arm/src/stm32/stm32_i2c.c

@@ -230,7 +230,6 @@ struct stm32_i2c_config_s
   uint32_t scl_pin;           /* GPIO configuration for SCL as SCL */
   uint32_t sda_pin;           /* GPIO configuration for SDA as SDA */
 #ifndef CONFIG_I2C_POLLED
-  int (*isr)(int, void *, void *);    /* Interrupt handler */
   uint32_t ev_irq;            /* Event IRQ */
   uint32_t er_irq;            /* Error IRQ */
 #endif
@@ -313,18 +312,10 @@ static inline uint32_t stm32_i2c_disablefsmc(FAR struct stm32_i2c_priv_s *priv);
 static inline void stm32_i2c_enablefsmc(uint32_t ahbenr);
 #endif /* I2C1_FSMC_CONFLICT */
 
-static int stm32_i2c_isr(struct stm32_i2c_priv_s * priv);
+static int stm32_i2c_isr_process(struct stm32_i2c_priv_s * priv);
 
 #ifndef CONFIG_I2C_POLLED
-#ifdef CONFIG_STM32_I2C1
+static int stm32_i2c_isr(int irq, void *context, FAR void *arg);
-static int stm32_i2c1_isr(int irq, void *context, FAR void *arg);
-#endif
-#ifdef CONFIG_STM32_I2C2
-static int stm32_i2c2_isr(int irq, void *context, FAR void *arg);
-#endif
-#ifdef CONFIG_STM32_I2C3
-static int stm32_i2c3_isr(int irq, void *context, FAR void *arg);
-#endif
 #endif /* !CONFIG_I2C_POLLED */
 
 static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv);
@@ -379,7 +370,6 @@ static const struct stm32_i2c_config_s stm32_i2c1_config =
   .scl_pin    = GPIO_I2C1_SCL,
   .sda_pin    = GPIO_I2C1_SDA,
 #ifndef CONFIG_I2C_POLLED
-  .isr        = stm32_i2c1_isr,
   .ev_irq     = STM32_IRQ_I2C1EV,
   .er_irq     = STM32_IRQ_I2C1ER
 #endif
@@ -409,7 +399,6 @@ static const struct stm32_i2c_config_s stm32_i2c2_config =
   .scl_pin    = GPIO_I2C2_SCL,
   .sda_pin    = GPIO_I2C2_SDA,
 #ifndef CONFIG_I2C_POLLED
-  .isr        = stm32_i2c2_isr,
   .ev_irq     = STM32_IRQ_I2C2EV,
   .er_irq     = STM32_IRQ_I2C2ER
 #endif
@@ -439,7 +428,6 @@ static const struct stm32_i2c_config_s stm32_i2c3_config =
   .scl_pin    = GPIO_I2C3_SCL,
   .sda_pin    = GPIO_I2C3_SDA,
 #ifndef CONFIG_I2C_POLLED
-  .isr        = stm32_i2c3_isr,
   .ev_irq     = STM32_IRQ_I2C3EV,
   .er_irq     = STM32_IRQ_I2C3ER
 #endif
@@ -678,7 +666,7 @@ static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv)
        * reports that it is done.
        */
 
-      stm32_i2c_isr(priv);
+      stm32_i2c_isr_process(priv);
     }
 
   /* Loop until the transfer is complete. */
@@ -1172,14 +1160,14 @@ static inline void stm32_i2c_enablefsmc(uint32_t ahbenr)
 #endif /* I2C1_FSMC_CONFLICT */
 
 /************************************************************************************
- * Name: stm32_i2c_isr
+ * Name: stm32_i2c_isr_process
  *
  * Description:
  *  Common Interrupt Service Routine
  *
  ************************************************************************************/
 
-static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
+static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
 {
   uint32_t status = stm32_i2c_getstatus(priv);
 
@@ -1459,56 +1447,23 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
 }
 
 /************************************************************************************
- * Name: stm32_i2c1_isr
+ * Name: stm32_i2c_isr
  *
  * Description:
- *   I2C1 interrupt service routine
+ *   Common I2C interrupt service routine
  *
  ************************************************************************************/
 
-#ifndef CONFIG_I2C_POLLED
+#ifdef CONFIG_I2C_POLLED
-#ifdef CONFIG_STM32_I2C1
-static int stm32_i2c1_isr(int irq, void *context, FAR void *arg)
-{
-  return stm32_i2c_isr(&stm32_i2c1_priv);
-}
-#endif
-
-/************************************************************************************
- * Name: stm32_i2c2_isr
- *
- * Description:
- *   I2C2 interrupt service routine
- *
- ************************************************************************************/
-
-#ifdef CONFIG_STM32_I2C2
 static int stm32_i2c2_isr(int irq, void *context, FAR void *arg)
 {
-  return stm32_i2c_isr(&stm32_i2c2_priv);
+  struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)arg;
+
+  DEBUGASSERT(priv != NULL);
+  return stm32_i2c_isr_process(priv);
 }
 #endif
 
-/************************************************************************************
- * Name: stm32_i2c3_isr
- *
- * Description:
- *   I2C2 interrupt service routine
- *
- ************************************************************************************/
-
-#ifdef CONFIG_STM32_I2C3
-static int stm32_i2c3_isr(int irq, void *context, FAR void *arg)
-{
-  return stm32_i2c_isr(&stm32_i2c3_priv);
-}
-#endif
-#endif
-
-/************************************************************************************
- * Private Initialization and Deinitialization
- ************************************************************************************/
-
 /************************************************************************************
  * Name: stm32_i2c_init
  *
@@ -1543,8 +1498,8 @@ static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv)
   /* Attach ISRs */
 
 #ifndef CONFIG_I2C_POLLED
-  irq_attach(priv->config->ev_irq, priv->config->isr, NULL);
+  irq_attach(priv->config->ev_irq, stm32_i2c_isr, priv);
-  irq_attach(priv->config->er_irq, priv->config->isr, NULL);
+  irq_attach(priv->config->er_irq, stm32_i2c_isr, priv);
   up_enable_irq(priv->config->ev_irq);
   up_enable_irq(priv->config->er_irq);
 #endif

arch/arm/src/stm32/stm32_i2c_alt.c

@@ -257,7 +257,6 @@ struct stm32_i2c_config_s
   uint32_t scl_pin;            /* GPIO configuration for SCL as SCL */
   uint32_t sda_pin;            /* GPIO configuration for SDA as SDA */
 #ifndef CONFIG_I2C_POLLED
-  int (*isr)(int, void *, void *);     /* Interrupt handler */
   uint32_t ev_irq;             /* Event IRQ */
   uint32_t er_irq;             /* Error IRQ */
 #endif
@@ -342,18 +341,10 @@ static inline uint32_t stm32_i2c_disablefsmc(FAR struct stm32_i2c_priv_s *priv);
 static inline void stm32_i2c_enablefsmc(uint32_t ahbenr);
 #endif /* I2C1_FSMC_CONFLICT */
 
-static int stm32_i2c_isr(struct stm32_i2c_priv_s * priv);
+static int stm32_i2c_isr_process(struct stm32_i2c_priv_s * priv);
 
 #ifndef CONFIG_I2C_POLLED
-#ifdef CONFIG_STM32_I2C1
+static int stm32_i2c_isr(int irq, void *context, FAR void *arg);
-static int stm32_i2c1_isr(int irq, void *context, FAR void *arg);
-#endif
-#ifdef CONFIG_STM32_I2C2
-static int stm32_i2c2_isr(int irq, void *context, FAR void *arg);
-#endif
-#ifdef CONFIG_STM32_I2C3
-static int stm32_i2c3_isr(int irq, void *context, FAR void *arg);
-#endif
 #endif /* !CONFIG_I2C_POLLED */
 
 static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv);
@@ -387,7 +378,6 @@ static const struct stm32_i2c_config_s stm32_i2c1_config =
   .scl_pin    = GPIO_I2C1_SCL,
   .sda_pin    = GPIO_I2C1_SDA,
 #ifndef CONFIG_I2C_POLLED
-  .isr        = stm32_i2c1_isr,
   .ev_irq     = STM32_IRQ_I2C1EV,
   .er_irq     = STM32_IRQ_I2C1ER
 #endif
@@ -417,7 +407,6 @@ static const struct stm32_i2c_config_s stm32_i2c2_config =
   .scl_pin    = GPIO_I2C2_SCL,
   .sda_pin    = GPIO_I2C2_SDA,
 #ifndef CONFIG_I2C_POLLED
-  .isr        = stm32_i2c2_isr,
   .ev_irq     = STM32_IRQ_I2C2EV,
   .er_irq     = STM32_IRQ_I2C2ER
 #endif
@@ -447,7 +436,6 @@ static const struct stm32_i2c_config_s stm32_i2c3_config =
   .scl_pin    = GPIO_I2C3_SCL,
   .sda_pin    = GPIO_I2C3_SDA,
 #ifndef CONFIG_I2C_POLLED
-  .isr        = stm32_i2c3_isr,
   .ev_irq     = STM32_IRQ_I2C3EV,
   .er_irq     = STM32_IRQ_I2C3ER
 #endif
@@ -686,7 +674,7 @@ static int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv)
        * reports that it is done.
        */
 
-      stm32_i2c_isr(priv);
+      stm32_i2c_isr_process(priv);
     }
 
   /* Loop until the transfer is complete. */
@@ -1180,7 +1168,7 @@ static inline void stm32_i2c_enablefsmc(uint32_t ahbenr)
 #endif /* I2C1_FSMC_CONFLICT */
 
 /************************************************************************************
- * Name: stm32_i2c_isr
+ * Name: stm32_i2c_isr_process
  *
  * Description:
  *  Common interrupt service routine (ISR) that handles I2C protocol logic.
@@ -1202,7 +1190,7 @@ static inline void stm32_i2c_enablefsmc(uint32_t ahbenr)
  *
  ************************************************************************************/
 
-static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
+static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
 {
 #ifndef CONFIG_I2C_POLLED
   uint32_t regval;
@@ -1892,56 +1880,23 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
 }
 
 /************************************************************************************
- * Name: stm32_i2c1_isr
+ * Name: stm32_i2c_isr
  *
  * Description:
- *   I2C1 interrupt service routine
+ *   Common I2C interrupt service routine
  *
  ************************************************************************************/
 
 #ifndef CONFIG_I2C_POLLED
-#ifdef CONFIG_STM32_I2C1
+static int stm32_i2c_isr(int irq, void *context, FAR void *arg)
-static int stm32_i2c1_isr(int irq, void *context, FAR void *arg)
 {
-  return stm32_i2c_isr(&stm32_i2c1_priv);
+  struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)arg;
+
+  DEBUGASSERT(priv != NULL);
+  return stm32_i2c_isr_process(priv);
 }
 #endif
 
-/************************************************************************************
- * Name: stm32_i2c2_isr
- *
- * Description:
- *   I2C2 interrupt service routine
- *
- ************************************************************************************/
-
-#ifdef CONFIG_STM32_I2C2
-static int stm32_i2c2_isr(int irq, void *context, FAR void *arg)
-{
-  return stm32_i2c_isr(&stm32_i2c2_priv);
-}
-#endif
-
-/************************************************************************************
- * Name: stm32_i2c3_isr
- *
- * Description:
- *   I2C2 interrupt service routine
- *
- ************************************************************************************/
-
-#ifdef CONFIG_STM32_I2C3
-static int stm32_i2c3_isr(int irq, void *context, FAR void *arg)
-{
-  return stm32_i2c_isr(&stm32_i2c3_priv);
-}
-#endif
-#endif
-
-/************************************************************************************
- * Private Initialization and Deinitialization
- ************************************************************************************/
-
 /************************************************************************************
  * Name: stm32_i2c_init
  *
@@ -1976,8 +1931,8 @@ static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv)
   /* Attach ISRs */
 
 #ifndef CONFIG_I2C_POLLED
-  irq_attach(priv->config->ev_irq, priv->config->isr, NULL);
+  irq_attach(priv->config->ev_irq, stm32_i2c_isr, priv);
-  irq_attach(priv->config->er_irq, priv->config->isr, NULL);
+  irq_attach(priv->config->er_irq, stm32_i2c_isr, priv);
   up_enable_irq(priv->config->ev_irq);
   up_enable_irq(priv->config->er_irq);
 #endif

arch/arm/src/stm32/stm32f30xxx_i2c.c

@@ -222,7 +222,6 @@ struct stm32_i2c_config_s
   uint32_t scl_pin;           /* GPIO configuration for SCL as SCL */
   uint32_t sda_pin;           /* GPIO configuration for SDA as SDA */
 #ifndef CONFIG_I2C_POLLED
-  int (*isr)(int, void *, void *);    /* Interrupt handler */
   uint32_t ev_irq;            /* Event IRQ */
   uint32_t er_irq;            /* Error IRQ */
 #endif
@@ -301,17 +300,9 @@ static inline void stm32_i2c_sendstart(FAR struct stm32_i2c_priv_s *priv);
 static inline void stm32_i2c_clrstart(FAR struct stm32_i2c_priv_s *priv);
 static inline void stm32_i2c_sendstop(FAR struct stm32_i2c_priv_s *priv);
 static inline uint32_t stm32_i2c_getstatus(FAR struct stm32_i2c_priv_s *priv);
-static int stm32_i2c_isr(struct stm32_i2c_priv_s * priv);
+static int stm32_i2c_isr_process(struct stm32_i2c_priv_s * priv);
 #ifndef CONFIG_I2C_POLLED
-#ifdef CONFIG_STM32_I2C1
+static int stm32_i2c_isr(int irq, void *context, FAR void *arg);
-static int stm32_i2c1_isr(int irq, void *context, FAR void *arg);
-#endif
-#ifdef CONFIG_STM32_I2C2
-static int stm32_i2c2_isr(int irq, void *context, FAR void *arg);
-#endif
-#ifdef CONFIG_STM32_I2C3
-static int stm32_i2c3_isr(int irq, void *context, FAR void *arg);
-#endif
 #endif
 static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv);
 static int stm32_i2c_deinit(FAR struct stm32_i2c_priv_s *priv);
@@ -344,7 +335,6 @@ static const struct stm32_i2c_config_s stm32_i2c1_config =
   .scl_pin    = GPIO_I2C1_SCL,
   .sda_pin    = GPIO_I2C1_SDA,
 #ifndef CONFIG_I2C_POLLED
-  .isr        = stm32_i2c1_isr,
   .ev_irq     = STM32_IRQ_I2C1EV,
   .er_irq     = STM32_IRQ_I2C1ER
 #endif
@@ -374,7 +364,6 @@ static const struct stm32_i2c_config_s stm32_i2c2_config =
   .scl_pin    = GPIO_I2C2_SCL,
   .sda_pin    = GPIO_I2C2_SDA,
 #ifndef CONFIG_I2C_POLLED
-  .isr        = stm32_i2c2_isr,
   .ev_irq     = STM32_IRQ_I2C2EV,
   .er_irq     = STM32_IRQ_I2C2ER
 #endif
@@ -404,7 +393,6 @@ static const struct stm32_i2c_config_s stm32_i2c3_config =
   .scl_pin    = GPIO_I2C3_SCL,
   .sda_pin    = GPIO_I2C3_SDA,
 #ifndef CONFIG_I2C_POLLED
-  .isr        = stm32_i2c3_isr,
   .ev_irq     = STM32_IRQ_I2C3EV,
   .er_irq     = STM32_IRQ_I2C3ER
 #endif
@@ -712,7 +700,7 @@ static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv)
        * reports that it is done.
        */
 
-      stm32_i2c_isr(priv);
+      stm32_i2c_isr_process(priv);
     }
 
   /* Loop until the transfer is complete. */
@@ -1243,7 +1231,7 @@ static inline uint32_t stm32_i2c_getstatus(FAR struct stm32_i2c_priv_s *priv)
 }
 
 /************************************************************************************
- * Name: stm32_i2c_isr
+ * Name: stm32_i2c_isr_startmessage
  *
  * Description:
  *   Common logic when a message is started.  Just adds the even to the trace buffer
@@ -1276,14 +1264,14 @@ static inline void stm32_i2c_clearinterrupts(struct stm32_i2c_priv_s *priv)
 }
 
 /************************************************************************************
- * Name: stm32_i2c_isr
+ * Name: stm32_i2c_isr_process
  *
  * Description:
  *  Common Interrupt Service Routine
  *
  ************************************************************************************/
 
-static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
+static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
 {
   uint32_t status = stm32_i2c_getstatus(priv);
 
@@ -1485,56 +1473,23 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
 }
 
 /************************************************************************************
- * Name: stm32_i2c1_isr
+ * Name: stm32_i2c_isr
  *
  * Description:
- *   I2C1 interrupt service routine
+ *   Common I2C interrupt service routine
  *
  ************************************************************************************/
 
 #ifndef CONFIG_I2C_POLLED
-#ifdef CONFIG_STM32_I2C1
+static int stm32_i2c_isr(int irq, void *context, FAR void *arg)
-static int stm32_i2c1_isr(int irq, void *context, FAR void *arg)
 {
-  return stm32_i2c_isr(&stm32_i2c1_priv);
+  struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)arg;
+
+  DEBUGASSERT(priv != NULL);
+  return stm32_i2c_isr_process(priv);
 }
 #endif
 
-/************************************************************************************
- * Name: stm32_i2c2_isr
- *
- * Description:
- *   I2C2 interrupt service routine
- *
- ************************************************************************************/
-
-#ifdef CONFIG_STM32_I2C2
-static int stm32_i2c2_isr(int irq, void *context, FAR void *arg)
-{
-  return stm32_i2c_isr(&stm32_i2c2_priv);
-}
-#endif
-
-/************************************************************************************
- * Name: stm32_i2c3_isr
- *
- * Description:
- *   I2C2 interrupt service routine
- *
- ************************************************************************************/
-
-#ifdef CONFIG_STM32_I2C3
-static int stm32_i2c3_isr(int irq, void *context, FAR void *arg)
-{
-  return stm32_i2c_isr(&stm32_i2c3_priv);
-}
-#endif
-#endif
-
-/************************************************************************************
- * Private Initialization and Deinitialization
- ************************************************************************************/
-
 /************************************************************************************
  * Name: stm32_i2c_init
  *
@@ -1569,8 +1524,8 @@ static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv)
   /* Attach ISRs */
 
 #ifndef CONFIG_I2C_POLLED
-  irq_attach(priv->config->ev_irq, priv->config->isr, NULL);
+  irq_attach(priv->config->ev_irq, stm32_i2c_isr, priv);
-  irq_attach(priv->config->er_irq, priv->config->isr, NULL);
+  irq_attach(priv->config->er_irq, stm32_i2c_isr, priv);
   up_enable_irq(priv->config->ev_irq);
   up_enable_irq(priv->config->er_irq);
 #endif

arch/arm/src/stm32/stm32f40xxx_i2c.c

@@ -245,7 +245,6 @@ struct stm32_i2c_config_s
   uint32_t scl_pin;           /* GPIO configuration for SCL as SCL */
   uint32_t sda_pin;           /* GPIO configuration for SDA as SDA */
 #ifndef CONFIG_I2C_POLLED
-  int (*isr)(int, void *, void *);    /* Interrupt handler */
   uint32_t ev_irq;            /* Event IRQ */
   uint32_t er_irq;            /* Error IRQ */
 #endif
@@ -339,18 +338,10 @@ static inline uint32_t stm32_i2c_disablefsmc(FAR struct stm32_i2c_priv_s *priv);
 static inline void stm32_i2c_enablefsmc(uint32_t ahbenr);
 #endif /* I2C1_FSMC_CONFLICT */
 
-static int stm32_i2c_isr(struct stm32_i2c_priv_s * priv);
+static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv);
 
 #ifndef CONFIG_I2C_POLLED
-#ifdef CONFIG_STM32_I2C1
+static int stm32_i2c_isr(int irq, void *context, FAR void *arg);
-static int stm32_i2c1_isr(int irq, void *context, FAR void *arg);
-#endif
-#ifdef CONFIG_STM32_I2C2
-static int stm32_i2c2_isr(int irq, void *context, FAR void *arg);
-#endif
-#ifdef CONFIG_STM32_I2C3
-static int stm32_i2c3_isr(int irq, void *context, FAR void *arg);
-#endif
 #endif /* !CONFIG_I2C_POLLED */
 
 static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv);
@@ -364,8 +355,8 @@ static int stm32_i2c_reset(FAR struct i2c_master_s *dev);
 /* DMA support */
 
 #ifdef CONFIG_STM32_I2C_DMA
-static void stm32_i2c_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg);
+static void stm32_i2c_dmarxcallback(DMA_HANDLE handle, uint8_t status, void *arg);
-static void stm32_i2c_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg);
+static void stm32_i2c_dmatxcallback(DMA_HANDLE handle, uint8_t status, void *arg);
 #endif
 
 /************************************************************************************
@@ -412,7 +403,6 @@ static const struct stm32_i2c_config_s stm32_i2c1_config =
   .scl_pin    = GPIO_I2C1_SCL,
   .sda_pin    = GPIO_I2C1_SDA,
 #ifndef CONFIG_I2C_POLLED
-  .isr        = stm32_i2c1_isr,
   .ev_irq     = STM32_IRQ_I2C1EV,
   .er_irq     = STM32_IRQ_I2C1ER
 #endif
@@ -451,7 +441,6 @@ static const struct stm32_i2c_config_s stm32_i2c2_config =
   .scl_pin    = GPIO_I2C2_SCL,
   .sda_pin    = GPIO_I2C2_SDA,
 #ifndef CONFIG_I2C_POLLED
-  .isr        = stm32_i2c2_isr,
   .ev_irq     = STM32_IRQ_I2C2EV,
   .er_irq     = STM32_IRQ_I2C2ER
 #endif
@@ -488,7 +477,6 @@ static const struct stm32_i2c_config_s stm32_i2c3_config =
   .scl_pin    = GPIO_I2C3_SCL,
   .sda_pin    = GPIO_I2C3_SDA,
 #ifndef CONFIG_I2C_POLLED
-  .isr        = stm32_i2c3_isr,
   .ev_irq     = STM32_IRQ_I2C3EV,
   .er_irq     = STM32_IRQ_I2C3ER
 #endif
@@ -734,7 +722,7 @@ static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv)
        * reports that it is done.
        */
 
-      stm32_i2c_isr(priv);
+      stm32_i2c_isr_process(priv);
     }
 
   /* Loop until the transfer is complete. */
@@ -1229,14 +1217,14 @@ static inline void stm32_i2c_enablefsmc(uint32_t ahbenr)
 #endif /* I2C1_FSMC_CONFLICT */
 
 /************************************************************************************
- * Name: stm32_i2c_isr
+ * Name: stm32_i2c_isr_process
  *
  * Description:
  *  Common Interrupt Service Routine
  *
  ************************************************************************************/
 
-static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
+static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
 {
   uint32_t status;
 #ifndef CONFIG_I2C_POLLED
@@ -2069,6 +2057,24 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
   return OK;
 }
 
+/************************************************************************************
+ * Name: stm32_i2c_isr
+ *
+ * Description:
+ *   Common I2C interrupt service routine
+ *
+ ************************************************************************************/
+
+#ifndef CONFIG_I2C_POLLED
+static int stm32_i2c_isr(int irq, void *context, FAR void *arg)
+{
+  struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)arg;
+
+  DEBUGASSERT(priv != NULL);
+  return stm32_i2c_isr_process(priv);
+}
+#endif
+
 /*****************************************************************************
  * Name: stm32_i2c_dmarxcallback
  *
@@ -2119,7 +2125,7 @@ static void stm32_i2c_dmarxcallback(DMA_HANDLE handle, uint8_t status, void *arg
 
   /* let the ISR routine take care of shutting down or switching to next msg */
 
-  stm32_i2c_isr(priv);
+  stm32_i2c_isr_process(priv);
 }
 #endif /* ifdef CONFIG_STM32_I2C_DMA */
 
@@ -2158,57 +2164,6 @@ static void stm32_i2c_dmatxcallback(DMA_HANDLE handle, uint8_t status, void *arg
 }
 #endif /* ifdef CONFIG_STM32_I2C_DMA */
 
-/************************************************************************************
- * Name: stm32_i2c1_isr
- *
- * Description:
- *   I2C1 interrupt service routine
- *
- ************************************************************************************/
-
-#ifndef CONFIG_I2C_POLLED
-#ifdef CONFIG_STM32_I2C1
-static int stm32_i2c1_isr(int irq, void *context, FAR void *arg)
-{
-  return stm32_i2c_isr(&stm32_i2c1_priv);
-}
-#endif
-
-/************************************************************************************
- * Name: stm32_i2c2_isr
- *
- * Description:
- *   I2C2 interrupt service routine
- *
- ************************************************************************************/
-
-#ifdef CONFIG_STM32_I2C2
-static int stm32_i2c2_isr(int irq, void *context, FAR void *arg)
-{
-  return stm32_i2c_isr(&stm32_i2c2_priv);
-}
-#endif
-
-/************************************************************************************
- * Name: stm32_i2c3_isr
- *
- * Description:
- *   I2C2 interrupt service routine
- *
- ************************************************************************************/
-
-#ifdef CONFIG_STM32_I2C3
-static int stm32_i2c3_isr(int irq, void *context, FAR void *arg)
-{
-  return stm32_i2c_isr(&stm32_i2c3_priv);
-}
-#endif
-#endif /* CONFIG_I2C_POLLED */
-
-/************************************************************************************
- * Private Initialization and Deinitialization
- ************************************************************************************/
-
 /************************************************************************************
  * Name: stm32_i2c_init
  *
@@ -2243,8 +2198,8 @@ static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv)
   /* Attach ISRs */
 
 #ifndef CONFIG_I2C_POLLED
-  irq_attach(priv->config->ev_irq, priv->config->isr, NULL);
+  irq_attach(priv->config->ev_irq, stm32_i2c_isr, priv);
-  irq_attach(priv->config->er_irq, priv->config->isr, NULL);
+  irq_attach(priv->config->er_irq, stm32_i2c_isr, priv);
   up_enable_irq(priv->config->ev_irq);
   up_enable_irq(priv->config->er_irq);
 #endif

arch/arm/src/stm32f0/Make.defs

@@ -95,6 +95,10 @@ ifeq ($(CONFIG_STM32F0_USB),y)
 CHIP_CSRCS += stm32f0_usbdev.c
 endif
 
+ifeq ($(CONFIG_STM32F0_I2C),y)
+CHIP_CSRCS += stm32f0_i2c.c
+endif
+
 ifeq ($(CONFIG_STM32F0_SPI0),y)
 CHIP_CSRCS += stm32f0_spi.c
 else

arch/arm/src/stm32f0/chip/stm32f05x_pinmap.h

@@ -70,22 +70,22 @@
 
 /* ADC */
 
-#define GPIO_ADC_IN0        (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_ADC_IN0        (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN0)
-#define GPIO_ADC_IN1        (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_ADC_IN1        (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1)
-#define GPIO_ADC_IN2        (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_ADC_IN2        (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN2)
-#define GPIO_ADC_IN3        (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_ADC_IN3        (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3)
-#define GPIO_ADC_IN4        (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4)
+#define GPIO_ADC_IN4        (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN4)
-#define GPIO_ADC_IN5        (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5)
+#define GPIO_ADC_IN5        (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5)
-#define GPIO_ADC_IN6        (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN6)
+#define GPIO_ADC_IN6        (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN6)
-#define GPIO_ADC_IN7        (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN7)
+#define GPIO_ADC_IN7        (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7)
-#define GPIO_ADC_IN8        (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0)
+#define GPIO_ADC_IN8        (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN0)
-#define GPIO_ADC_IN9        (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN1)
+#define GPIO_ADC_IN9        (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN1)
-#define GPIO_ADC_IN10       (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN0)
+#define GPIO_ADC_IN10       (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN0)
-#define GPIO_ADC_IN11       (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN1)
+#define GPIO_ADC_IN11       (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN1)
-#define GPIO_ADC_IN12       (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN2)
+#define GPIO_ADC_IN12       (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN2)
-#define GPIO_ADC_IN13       (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN3)
+#define GPIO_ADC_IN13       (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN3)
-#define GPIO_ADC_IN14       (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN4)
+#define GPIO_ADC_IN14       (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN4)
-#define GPIO_ADC_IN15       (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN5)
+#define GPIO_ADC_IN15       (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5)
 
 /* TIMERS */
 
@@ -93,44 +93,44 @@
 
 /* USART */
 
-#define GPIO_USART1_TX_1    (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN9)
+#define GPIO_USART1_TX_1    (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN9)
-#define GPIO_USART1_TX_2    (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN6)
+#define GPIO_USART1_TX_2    (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN6)
-#define GPIO_USART1_RX_1    (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN10)
+#define GPIO_USART1_RX_1    (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN10)
-#define GPIO_USART1_RX_2    (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN7)
+#define GPIO_USART1_RX_2    (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN7)
-#define GPIO_USART1_CTS     (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN11)
+#define GPIO_USART1_CTS     (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN11)
-#define GPIO_USART1_RTS     (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN12)
+#define GPIO_USART1_RTS     (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN12)
-#define GPIO_USART1_CK      (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN8)
+#define GPIO_USART1_CK      (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN8)
 
-#define GPIO_USART2_CTS     (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_USART2_CTS     (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN0)
-#define GPIO_USART2_RTS     (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_USART2_RTS     (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN1)
-#define GPIO_USART2_TX      (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_USART2_TX      (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN2)
-#define GPIO_USART2_RX      (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_USART2_RX      (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN3)
-#define GPIO_USART2_CK      (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN4)
+#define GPIO_USART2_CK      (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN4)
 
 /* SPI */
 
-#define GPIO_SPI1_NSS_1     (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN4)
+#define GPIO_SPI1_NSS_1     (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN4)
-#define GPIO_SPI1_NSS_2     (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN15)
+#define GPIO_SPI1_NSS_2     (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN15)
-#define GPIO_SPI1_SCK_1     (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN5)
+#define GPIO_SPI1_SCK_1     (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN5)
-#define GPIO_SPI1_SCK_2     (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN3)
+#define GPIO_SPI1_SCK_2     (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN3)
-#define GPIO_SPI1_MISO_1    (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN6)
+#define GPIO_SPI1_MISO_1    (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN6)
-#define GPIO_SPI1_MISO_2    (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN4)
+#define GPIO_SPI1_MISO_2    (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN4)
-#define GPIO_SPI1_MOSI_1    (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN7)
+#define GPIO_SPI1_MOSI_1    (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN7)
-#define GPIO_SPI1_MOSI_2    (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN5)
+#define GPIO_SPI1_MOSI_2    (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN5)
-#define GPIO_SPI2_NSS       (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN12)
+#define GPIO_SPI2_NSS       (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN12)
-#define GPIO_SPI2_SCK       (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN13)
+#define GPIO_SPI2_SCK       (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN13)
-#define GPIO_SPI2_MISO      (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN14)
+#define GPIO_SPI2_MISO      (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN14)
-#define GPIO_SPI2_MOSI      (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN15)
+#define GPIO_SPI2_MOSI      (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN15)
 
 /* I2C */
 
-#define GPIO_I2C1_SCL_1     (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN6)
+#define GPIO_I2C1_SCL_1     (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN6)
-#define GPIO_I2C1_SCL_2     (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN8)
+#define GPIO_I2C1_SCL_2     (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN8)
-#define GPIO_I2C1_SDA_1     (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN7)
+#define GPIO_I2C1_SDA_1     (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN7)
-#define GPIO_I2C1_SDA_2     (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN9)
+#define GPIO_I2C1_SDA_2     (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN9)
-#define GPIO_I2C1_SMBA      (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN5)
+#define GPIO_I2C1_SMBA      (GPIO_ALT | GPIO_AF3 | GPIO_FLOAT | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN5)
 
-#define GPIO_I2C2_SCL       (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN10)
+#define GPIO_I2C2_SCL       (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN10)
-#define GPIO_I2C2_SDA       (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN11)
+#define GPIO_I2C2_SDA       (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN11)
 
 #endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F05X_PINMAP_H */

arch/arm/src/stm32f0/chip/stm32f07x_pinmap.h

@@ -144,16 +144,16 @@
 
 /* I2C */
 
-#define GPIO_I2C1_SCL_1          (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN6)
+#define GPIO_I2C1_SCL_1          (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN6)
-#define GPIO_I2C1_SCL_2          (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN8)
+#define GPIO_I2C1_SCL_2          (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN8)
-#define GPIO_I2C1_SDA_1          (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN7)
+#define GPIO_I2C1_SDA_1          (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN7)
-#define GPIO_I2C1_SDA_2          (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN9)
+#define GPIO_I2C1_SDA_2          (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN9)
-#define GPIO_I2C1_SMBA           (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN5)
+#define GPIO_I2C1_SMBA           (GPIO_ALT | GPIO_AF3 | GPIO_FLOAT | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN5)
 
-#define GPIO_I2C2_SCL_1          (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN10)
+#define GPIO_I2C2_SCL_1          (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN10)
-#define GPIO_I2C2_SCL_2          (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN13)
+#define GPIO_I2C2_SCL_2          (GPIO_ALT | GPIO_AF5 | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN13)
-#define GPIO_I2C2_SDA_1          (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN11)
+#define GPIO_I2C2_SDA_1          (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN11)
-#define GPIO_I2C2_SDA_2          (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN14)
+#define GPIO_I2C2_SDA_2          (GPIO_ALT | GPIO_AF5 | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN14)
 
 /* I2S */
 

arch/arm/src/stm32f0/stm32f0_i2c.h

@@ -0,0 +1,104 @@
+/****************************************************************************
+ * arch/arm/src/stm32f0/stm32f0_i2c.h
+ *
+ *   Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32F0_STM32F0_I2C_H
+#define __ARCH_ARM_SRC_STM32F0_STM32F0_I2C_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/i2c/i2c_master.h>
+
+#include "chip.h"
+#include "chip/stm32f0_i2c.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* If a dynamic timeout is selected, then a non-negative, non-zero micro-
+ * seconds per byte value must be provided as well.
+ */
+
+#ifdef CONFIG_STM32F0_I2C_DYNTIMEO
+#  if CONFIG_STM32F0_I2C_DYNTIMEO_USECPERBYTE < 1
+#    warning "Ignoring CONFIG_STM32F0_I2C_DYNTIMEO because of CONFIG_STM32F0_I2C_DYNTIMEO_USECPERBYTE"
+#    undef CONFIG_STM32F0_I2C_DYNTIMEO
+#  endif
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32f0_i2cbus_initialize
+ *
+ * Description:
+ *   Initialize the selected I2C port. And return a unique instance of struct
+ *   struct i2c_master_s.  This function may be called to obtain multiple
+ *   instances of the interface, each of which may be set up with a
+ *   different frequency and slave address.
+ *
+ * Input Parameter:
+ *   Port number (for hardware that has multiple I2C interfaces)
+ *
+ * Returned Value:
+ *   Valid I2C device structure reference on succcess; a NULL on failure
+ *
+ ****************************************************************************/
+
+FAR struct i2c_master_s *stm32f0_i2cbus_initialize(int port);
+
+/****************************************************************************
+ * Name: stm32f0_i2cbus_uninitialize
+ *
+ * Description:
+ *   De-initialize the selected I2C port, and power down the device.
+ *
+ * Input Parameter:
+ *   Device structure as returned by the stm32f0_i2cbus_initialize()
+ *
+ * Returned Value:
+ *   OK on success, ERROR when internal reference count mismatch or dev
+ *   points to invalid hardware device.
+ *
+ ****************************************************************************/
+
+int stm32f0_i2cbus_uninitialize(FAR struct i2c_master_s *dev);
+
+#endif /* __ARCH_ARM_SRC_STM32F0_STM32F0_I2C_H */

arch/arm/src/stm32f0/stm32f0_uart.h

@@ -79,11 +79,40 @@
 #  undef CONFIG_STM32F0_USART1
 #endif
 
+/* USART 3-8 are multiplexed to the same interrupt.  Current interrupt
+ * handling logic will support only one USART in that range.  That is
+ * not an issue for currently supported chips but could become an
+ * issue in the future.
+ */
+
+#if defined(CONFIG_STM32F0_USART3)
+#  undef CONFIG_STM32F0_USART4
+#  undef CONFIG_STM32F0_USART5
+#  undef CONFIG_STM32F0_USART6
+#  undef CONFIG_STM32F0_USART7
+#  undef CONFIG_STM32F0_USART8
+#elif defined(CONFIG_STM32F0_USART4)
+#  undef CONFIG_STM32F0_USART5
+#  undef CONFIG_STM32F0_USART6
+#  undef CONFIG_STM32F0_USART7
+#  undef CONFIG_STM32F0_USART8
+#elif defined(CONFIG_STM32F0_USART5)
+#  undef CONFIG_STM32F0_USART6
+#  undef CONFIG_STM32F0_USART7
+#  undef CONFIG_STM32F0_USART8
+#elif defined(CONFIG_STM32F0_USART6)
+#  undef CONFIG_STM32F0_USART7
+#  undef CONFIG_STM32F0_USART8
+#elif defined(CONFIG_STM32F0_USART7)
+#  undef CONFIG_STM32F0_USART8
+#endif
+
 /* Is there a USART enabled? */
 
 #if defined(CONFIG_STM32F0_USART1) || defined(CONFIG_STM32F0_USART2) || \
     defined(CONFIG_STM32F0_USART3) || defined(CONFIG_STM32F0_USART4) || \
-    defined(CONFIG_STM32F0_USART5)
+    defined(CONFIG_STM32F0_USART5) || defined(CONFIG_STM32F0_USART6) || \
+    defined(CONFIG_STM32F0_USART7) || defined(CONFIG_STM32F0_USART8)
 #  define HAVE_USART 1
 #endif
 

arch/arm/src/stm32f7/stm32_i2c.c

@@ -402,7 +402,6 @@ struct stm32_i2c_config_s
   uint32_t scl_pin;           /* GPIO configuration for SCL as SCL */
   uint32_t sda_pin;           /* GPIO configuration for SDA as SDA */
 #ifndef CONFIG_I2C_POLLED
-  int (*isr)(int, void *, void *);    /* Interrupt handler */
   uint32_t ev_irq;            /* Event IRQ */
   uint32_t er_irq;            /* Error IRQ */
 #endif
@@ -484,20 +483,9 @@ static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv,
 static inline void stm32_i2c_sendstart(FAR struct stm32_i2c_priv_s *priv);
 static inline void stm32_i2c_sendstop(FAR struct stm32_i2c_priv_s *priv);
 static inline uint32_t stm32_i2c_getstatus(FAR struct stm32_i2c_priv_s *priv);
-static int stm32_i2c_isr(struct stm32_i2c_priv_s * priv);
+static int stm32_i2c_isr_process(struct stm32_i2c_priv_s * priv);
 #ifndef CONFIG_I2C_POLLED
-#  ifdef CONFIG_STM32F7_I2C1
+static int stm32_i2c_isr(int irq, void *context, FAR void *arg);
-static int stm32_i2c1_isr(int irq, void *context, FAR void *arg);
-#  endif
-#  ifdef CONFIG_STM32F7_I2C2
-static int stm32_i2c2_isr(int irq, void *context, FAR void *arg);
-#  endif
-#  ifdef CONFIG_STM32F7_I2C3
-static int stm32_i2c3_isr(int irq, void *context, FAR void *arg);
-#  endif
-#  ifdef CONFIG_STM32F7_I2C4
-static int stm32_i2c4_isr(int irq, void *context, FAR void *arg);
-#  endif
 #endif
 static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv);
 static int stm32_i2c_deinit(FAR struct stm32_i2c_priv_s *priv);
@@ -523,7 +511,6 @@ static const struct stm32_i2c_config_s stm32_i2c1_config =
   .scl_pin    = GPIO_I2C1_SCL,
   .sda_pin    = GPIO_I2C1_SDA,
 #ifndef CONFIG_I2C_POLLED
-  .isr        = stm32_i2c1_isr,
   .ev_irq     = STM32_IRQ_I2C1EV,
   .er_irq     = STM32_IRQ_I2C1ER
 #endif
@@ -553,7 +540,6 @@ static const struct stm32_i2c_config_s stm32_i2c2_config =
   .scl_pin    = GPIO_I2C2_SCL,
   .sda_pin    = GPIO_I2C2_SDA,
 #ifndef CONFIG_I2C_POLLED
-  .isr        = stm32_i2c2_isr,
   .ev_irq     = STM32_IRQ_I2C2EV,
   .er_irq     = STM32_IRQ_I2C2ER
 #endif
@@ -583,7 +569,6 @@ static const struct stm32_i2c_config_s stm32_i2c3_config =
   .scl_pin    = GPIO_I2C3_SCL,
   .sda_pin    = GPIO_I2C3_SDA,
 #ifndef CONFIG_I2C_POLLED
-  .isr        = stm32_i2c3_isr,
   .ev_irq     = STM32_IRQ_I2C3EV,
   .er_irq     = STM32_IRQ_I2C3ER
 #endif
@@ -613,7 +598,6 @@ static const struct stm32_i2c_config_s stm32_i2c4_config =
   .scl_pin    = GPIO_I2C4_SCL,
   .sda_pin    = GPIO_I2C4_SDA,
 #ifndef CONFIG_I2C_POLLED
-  .isr        = stm32_i2c4_isr,
   .ev_irq     = STM32_IRQ_I2C4EV,
   .er_irq     = STM32_IRQ_I2C4ER
 #endif
@@ -905,7 +889,7 @@ static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv)
        * reports that it is done.
        */
 
-      stm32_i2c_isr(priv);
+      stm32_i2c_isr_process(priv);
     }
 
   /* Loop until the transfer is complete. */
@@ -1538,7 +1522,7 @@ static inline void stm32_i2c_clearinterrupts(struct stm32_i2c_priv_s *priv)
 }
 
 /************************************************************************************
- * Name: stm32_i2c_isr
+ * Name: stm32_i2c_isr_process
  *
  * Description:
  *  Common interrupt service routine (ISR) that handles I2C protocol logic.
@@ -1555,7 +1539,7 @@ static inline void stm32_i2c_clearinterrupts(struct stm32_i2c_priv_s *priv)
  *
  ************************************************************************************/
 
-static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
+static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
 {
   uint32_t status;
 
@@ -2144,71 +2128,23 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
 }
 
 /************************************************************************************
- * Name: stm32_i2c1_isr
+ * Name: stm32_i2c_isr
  *
  * Description:
- *   I2C1 interrupt service routine
+ *   Common I2C interrupt service routine
  *
  ************************************************************************************/
 
 #ifndef CONFIG_I2C_POLLED
-#  ifdef CONFIG_STM32F7_I2C1
+static int stm32_i2c_isr(int irq, void *context, FAR void *arg)
-static int stm32_i2c1_isr(int irq, void *context, FAR void *arg)
 {
-  return stm32_i2c_isr(&stm32_i2c1_priv);
+  struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)arg;
+
+  DEBUGASSERT(priv != NULL);
+  return stm32_i2c_isr_process(&stm32_i2c1_priv);
 }
-#  endif
-
-/************************************************************************************
- * Name: stm32_i2c2_isr
- *
- * Description:
- *   I2C2 interrupt service routine
- *
- ************************************************************************************/
-
-# ifdef CONFIG_STM32F7_I2C2
-static int stm32_i2c2_isr(int irq, void *context, FAR void *arg)
-{
-  return stm32_i2c_isr(&stm32_i2c2_priv);
-}
-#  endif
-
-/************************************************************************************
- * Name: stm32_i2c3_isr
- *
- * Description:
- *   I2C2 interrupt service routine
- *
- ************************************************************************************/
-
-#  ifdef CONFIG_STM32F7_I2C3
-static int stm32_i2c3_isr(int irq, void *context, FAR void *arg)
-{
-  return stm32_i2c_isr(&stm32_i2c3_priv);
-}
-#  endif
-
-/************************************************************************************
- * Name: stm32_i2c4_isr
- *
- * Description:
- *   I2C2 interrupt service routine
- *
- ************************************************************************************/
-
-#  ifdef CONFIG_STM32F7_I2C4
-static int stm32_i2c4_isr(int irq, void *context, FAR void *arg)
-{
-  return stm32_i2c_isr(&stm32_i2c4_priv);
-}
-#  endif
 #endif
 
-/************************************************************************************
- * Private Initialization and Deinitialization
- ************************************************************************************/
-
 /************************************************************************************
  * Name: stm32_i2c_init
  *
@@ -2243,8 +2179,8 @@ static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv)
 #ifndef CONFIG_I2C_POLLED
   /* Attach error and event interrupts to the ISRs */
 
-  irq_attach(priv->config->ev_irq, priv->config->isr, NULL);
+  irq_attach(priv->config->ev_irq, stm32_i2c_isr, priv);
-  irq_attach(priv->config->er_irq, priv->config->isr, NULL);
+  irq_attach(priv->config->er_irq, stm32_i2c_isr, priv);
   up_enable_irq(priv->config->ev_irq);
   up_enable_irq(priv->config->er_irq);
 #endif

arch/arm/src/tiva/tiva_i2c.c

@@ -195,7 +195,6 @@ struct tiva_i2c_config_s
   uint32_t scl_pin;           /* GPIO configuration for SCL as SCL */
   uint32_t sda_pin;           /* GPIO configuration for SDA as SDA */
 #ifndef CONFIG_I2C_POLLED
-  int (*isr)(int, void *, void *);    /* Interrupt handler */
   uint8_t irq;                /* IRQ number */
 #endif
   uint8_t devno;              /* I2Cn where n = devno */
@@ -282,39 +281,10 @@ static void tiva_i2c_tracedump(struct tiva_i2c_priv_s *priv);
 
 static void tiva_i2c_startxfr(struct tiva_i2c_priv_s *priv);
 static void tiva_i2c_nextxfr(struct tiva_i2c_priv_s *priv, uint32_t cmd);
-static int tiva_i2c_interrupt(struct tiva_i2c_priv_s * priv, uint32_t status);
+static int tiva_i2c_process(struct tiva_i2c_priv_s * priv, uint32_t status);
 
 #ifndef CONFIG_I2C_POLLED
-#ifdef CONFIG_TIVA_I2C0
+static int tiva_i2c_interrupt(int irq, void *context, FAR void *arg);
-static int tiva_i2c0_interrupt(int irq, void *context, FAR void *arg);
-#endif
-#ifdef CONFIG_TIVA_I2C1
-static int tiva_i2c1_interrupt(int irq, void *context, FAR void *arg);
-#endif
-#ifdef CONFIG_TIVA_I2C2
-static int tiva_i2c2_interrupt(int irq, void *context, FAR void *arg);
-#endif
-#ifdef CONFIG_TIVA_I2C3
-static int tiva_i2c3_interrupt(int irq, void *context, FAR void *arg);
-#endif
-#ifdef CONFIG_TIVA_I2C4
-static int tiva_i2c4_interrupt(int irq, void *context, FAR void *arg);
-#endif
-#ifdef CONFIG_TIVA_I2C5
-static int tiva_i2c5_interrupt(int irq, void *context, FAR void *arg);
-#endif
-#ifdef CONFIG_TIVA_I2C6
-static int tiva_i2c6_interrupt(int irq, void *context, FAR void *arg);
-#endif
-#ifdef CONFIG_TIVA_I2C7
-static int tiva_i2c7_interrupt(int irq, void *context, FAR void *arg);
-#endif
-#ifdef CONFIG_TIVA_I2C8
-static int tiva_i2c8_interrupt(int irq, void *context, FAR void *arg);
-#endif
-#ifdef CONFIG_TIVA_I2C9
-static int tiva_i2c9_interrupt(int irq, void *context, FAR void *arg);
-#endif
 #endif /* !CONFIG_I2C_POLLED */
 
 static int tiva_i2c_initialize(struct tiva_i2c_priv_s *priv, uint32_t frequency);
@@ -353,7 +323,6 @@ static const struct tiva_i2c_config_s tiva_i2c0_config =
   .scl_pin    = GPIO_I2C0_SCL,
   .sda_pin    = GPIO_I2C0_SDA,
 #ifndef CONFIG_I2C_POLLED
-  .isr        = tiva_i2c0_interrupt,
   .irq        = TIVA_IRQ_I2C0,
 #endif
   .devno      = 0,
@@ -375,7 +344,6 @@ static const struct tiva_i2c_config_s tiva_i2c1_config =
   .scl_pin    = GPIO_I2C1_SCL,
   .sda_pin    = GPIO_I2C1_SDA,
 #ifndef CONFIG_I2C_POLLED
-  .isr        = tiva_i2c1_interrupt,
   .irq        = TIVA_IRQ_I2C1,
 #endif
   .devno      = 1,
@@ -397,7 +365,6 @@ static const struct tiva_i2c_config_s tiva_i2c2_config =
   .scl_pin    = GPIO_I2C2_SCL,
   .sda_pin    = GPIO_I2C2_SDA,
 #ifndef CONFIG_I2C_POLLED
-  .isr        = tiva_i2c2_interrupt,
   .irq        = TIVA_IRQ_I2C2,
 #endif
   .devno      = 2,
@@ -419,7 +386,6 @@ static const struct tiva_i2c_config_s tiva_i2c3_config =
   .scl_pin    = GPIO_I2C3_SCL,
   .sda_pin    = GPIO_I2C3_SDA,
 #ifndef CONFIG_I2C_POLLED
-  .isr        = tiva_i2c3_interrupt,
   .irq        = TIVA_IRQ_I2C3,
 #endif
   .devno      = 3,
@@ -441,7 +407,6 @@ static const struct tiva_i2c_config_s tiva_i2c4_config =
   .scl_pin    = GPIO_I2C4_SCL,
   .sda_pin    = GPIO_I2C4_SDA,
 #ifndef CONFIG_I2C_POLLED
-  .isr        = tiva_i2c4_interrupt,
   .irq        = TIVA_IRQ_I2C4,
 #endif
   .devno      = 4,
@@ -463,7 +428,6 @@ static const struct tiva_i2c_config_s tiva_i2c5_config =
   .scl_pin    = GPIO_I2C5_SCL,
   .sda_pin    = GPIO_I2C5_SDA,
 #ifndef CONFIG_I2C_POLLED
-  .isr        = tiva_i2c5_interrupt,
   .irq        = TIVA_IRQ_I2C5,
 #endif
   .devno      = 5,
@@ -485,7 +449,6 @@ static const struct tiva_i2c_config_s tiva_i2c6_config =
   .scl_pin    = GPIO_I2C6_SCL,
   .sda_pin    = GPIO_I2C6_SDA,
 #ifndef CONFIG_I2C_POLLED
-  .isr        = tiva_i2c6_interrupt,
   .irq        = TIVA_IRQ_I2C6,
 #endif
   .devno      = 6,
@@ -507,7 +470,6 @@ static const struct tiva_i2c_config_s tiva_i2c7_config =
   .scl_pin    = GPIO_I2C7_SCL,
   .sda_pin    = GPIO_I2C7_SDA,
 #ifndef CONFIG_I2C_POLLED
-  .isr        = tiva_i2c7_interrupt,
   .irq        = TIVA_IRQ_I2C7,
 #endif
   .devno      = 7,
@@ -529,7 +491,6 @@ static const struct tiva_i2c_config_s tiva_i2c8_config =
   .scl_pin    = GPIO_I2C8_SCL,
   .sda_pin    = GPIO_I2C8_SDA,
 #ifndef CONFIG_I2C_POLLED
-  .isr        = tiva_i2c8_interrupt,
   .irq        = TIVA_IRQ_I2C8,
 #endif
   .devno      = 8,
@@ -551,7 +512,6 @@ static const struct tiva_i2c_config_s tiva_i2c9_config =
   .scl_pin    = GPIO_I2C9_SCL,
   .sda_pin    = GPIO_I2C9_SDA,
 #ifndef CONFIG_I2C_POLLED
-  .isr        = tiva_i2c9_interrupt,
   .irq        = TIVA_IRQ_I2C9,
 #endif
   .devno      = 9,
@@ -846,7 +806,7 @@ static inline int tiva_i2c_sem_waitdone(struct tiva_i2c_priv_s *priv)
        * interrupt status until it reports that it is done.
        */
 
-      tiva_i2c_interrupt(priv, status);
+      tiva_i2c_process(priv, status);
 
       /* Calculate the elapsed time */
 
@@ -1186,14 +1146,14 @@ static void tiva_i2c_nextxfr(struct tiva_i2c_priv_s *priv, uint32_t cmd)
 }
 
 /************************************************************************************
- * Name: tiva_i2c_interrupt
+ * Name: tiva_i2c_process
  *
  * Description:
  *  Common Interrupt Service Routine
  *
  ************************************************************************************/
 
-static int tiva_i2c_interrupt(struct tiva_i2c_priv_s *priv, uint32_t status)
+static int tiva_i2c_process(struct tiva_i2c_priv_s *priv, uint32_t status)
 {
   /* Check for new trace setup */
 
@@ -1411,252 +1371,28 @@ static int tiva_i2c_interrupt(struct tiva_i2c_priv_s *priv, uint32_t status)
 }
 
 /************************************************************************************
- * Name: tiva_i2c0_interrupt
+ * Name: tiva_i2c_interrupt
  *
  * Description:
- *   I2C0 interrupt service routine
+ *   Common I2C interrupt service routine
  *
  ************************************************************************************/
 
 #if !defined(CONFIG_I2C_POLLED) && defined(CONFIG_TIVA_I2C0)
-static int tiva_i2c0_interrupt(int irq, void *context, void *arg)
+static int tiva_i2c_interrupt(int irq, void *context, void *arg)
 {
-  struct tiva_i2c_priv_s *priv;
+  struct tiva_i2c_priv_s *priv = (struct tiva_i2c_priv_s *)arg;
   uint32_t status;
 
+  DEBUGASSERT(priv != NULL);
+
   /* Read the masked interrupt status */
 
-  priv   = &tiva_i2c0_priv;
   status = tiva_i2c_getreg(priv, TIVA_I2CM_MIS_OFFSET);
 
   /* Let the common interrupt handler do the rest of the work */
 
-  return tiva_i2c_interrupt(priv, status);
+  return tiva_i2c_process(priv, status);
-}
-#endif
-
-/************************************************************************************
- * Name: tiva_i2c1_interrupt
- *
- * Description:
- *   I2C1 interrupt service routine
- *
- ************************************************************************************/
-
-#if !defined(CONFIG_I2C_POLLED) && defined(CONFIG_TIVA_I2C1)
-static int tiva_i2c1_interrupt(int irq, void *context, FAR void *arg)
-{
-  struct tiva_i2c_priv_s *priv;
-  uint32_t status;
-
-  /* Read the masked interrupt status */
-
-  priv   = &tiva_i2c1_priv;
-  status = tiva_i2c_getreg(priv, TIVA_I2CM_MIS_OFFSET);
-
-  /* Let the common interrupt handler do the rest of the work */
-
-  return tiva_i2c_interrupt(priv, status);
-}
-#endif
-
-/************************************************************************************
- * Name: tiva_i2c2_interrupt
- *
- * Description:
- *   I2C2 interrupt service routine
- *
- ************************************************************************************/
-
-#if !defined(CONFIG_I2C_POLLED) && defined(CONFIG_TIVA_I2C2)
-static int tiva_i2c2_interrupt(int irq, void *context, FAR void *arg)
-{
-  struct tiva_i2c_priv_s *priv;
-  uint32_t status;
-
-  /* Read the masked interrupt status */
-
-  priv   = &tiva_i2c2_priv;
-  status = tiva_i2c_getreg(priv, TIVA_I2CM_MIS_OFFSET);
-
-  /* Let the common interrupt handler do the rest of the work */
-
-  return tiva_i2c_interrupt(priv, status);
-}
-#endif
-
-/************************************************************************************
- * Name: tiva_i2c3_interrupt
- *
- * Description:
- *   I2C2 interrupt service routine
- *
- ************************************************************************************/
-
-#if !defined(CONFIG_I2C_POLLED) && defined(CONFIG_TIVA_I2C3)
-static int tiva_i2c3_interrupt(int irq, void *context, FAR void *arg)
-{
-  struct tiva_i2c_priv_s *priv;
-  uint32_t status;
-
-  /* Read the masked interrupt status */
-
-  priv   = &tiva_i2c3_priv;
-  status = tiva_i2c_getreg(priv, TIVA_I2CM_MIS_OFFSET);
-
-  /* Let the common interrupt handler do the rest of the work */
-
-  return tiva_i2c_interrupt(priv, status);
-}
-#endif
-
-/************************************************************************************
- * Name: tiva_i2c4_interrupt
- *
- * Description:
- *   I2C4 interrupt service routine
- *
- ************************************************************************************/
-
-#if !defined(CONFIG_I2C_POLLED) && defined(CONFIG_TIVA_I2C4)
-static int tiva_i2c4_interrupt(int irq, void *context, FAR void *arg)
-{
-  struct tiva_i2c_priv_s *priv;
-  uint32_t status;
-
-  /* Read the masked interrupt status */
-
-  priv   = &tiva_i2c4_priv;
-  status = tiva_i2c_getreg(priv, TIVA_I2CM_MIS_OFFSET);
-
-  /* Let the common interrupt handler do the rest of the work */
-
-  return tiva_i2c_interrupt(priv, status);
-}
-#endif
-
-/************************************************************************************
- * Name: tiva_i2c5_interrupt
- *
- * Description:
- *   I2C5 interrupt service routine
- *
- ************************************************************************************/
-
-#if !defined(CONFIG_I2C_POLLED) && defined(CONFIG_TIVA_I2C5)
-static int tiva_i2c5_interrupt(int irq, void *context, FAR void *arg)
-{
-  struct tiva_i2c_priv_s *priv;
-  uint32_t status;
-
-  /* Read the masked interrupt status */
-
-  priv   = &tiva_i2c5_priv;
-  status = tiva_i2c_getreg(priv, TIVA_I2CM_MIS_OFFSET);
-
-  /* Let the common interrupt handler do the rest of the work */
-
-  return tiva_i2c_interrupt(priv, status);
-}
-#endif
-
-/************************************************************************************
- * Name: tiva_i2c6_interrupt
- *
- * Description:
- *   I2C6 interrupt service routine
- *
- ************************************************************************************/
-
-#if !defined(CONFIG_I2C_POLLED) && defined(CONFIG_TIVA_I2C6)
-static int tiva_i2c6_interrupt(int irq, void *context, FAR void *arg)
-{
-  struct tiva_i2c_priv_s *priv;
-  uint32_t status;
-
-  /* Read the masked interrupt status */
-
-  priv   = &tiva_i2c6_priv;
-  status = tiva_i2c_getreg(priv, TIVA_I2CM_MIS_OFFSET);
-
-  /* Let the common interrupt handler do the rest of the work */
-
-  return tiva_i2c_interrupt(priv, status);
-}
-#endif
-
-/************************************************************************************
- * Name: tiva_i2c7_interrupt
- *
- * Description:
- *   I2C7 interrupt service routine
- *
- ************************************************************************************/
-
-#if !defined(CONFIG_I2C_POLLED) && defined(CONFIG_TIVA_I2C7)
-static int tiva_i2c7_interrupt(int irq, void *context, FAR void *arg)
-{
-  struct tiva_i2c_priv_s *priv;
-  uint32_t status;
-
-  /* Read the masked interrupt status */
-
-  priv   = &tiva_i2c7_priv;
-  status = tiva_i2c_getreg(priv, TIVA_I2CM_MIS_OFFSET);
-
-  /* Let the common interrupt handler do the rest of the work */
-
-  return tiva_i2c_interrupt(priv, status);
-}
-#endif
-
-/************************************************************************************
- * Name: tiva_i2c8_interrupt
- *
- * Description:
- *   I2C8 interrupt service routine
- *
- ************************************************************************************/
-
-#if !defined(CONFIG_I2C_POLLED) && defined(CONFIG_TIVA_I2C8)
-static int tiva_i2c8_interrupt(int irq, void *context, FAR void *arg)
-{
-  struct tiva_i2c_priv_s *priv;
-  uint32_t status;
-
-  /* Read the masked interrupt status */
-
-  priv   = &tiva_i2c8_priv;
-  status = tiva_i2c_getreg(priv, TIVA_I2CM_MIS_OFFSET);
-
-  /* Let the common interrupt handler do the rest of the work */
-
-  return tiva_i2c_interrupt(priv, status);
-}
-#endif
-
-/************************************************************************************
- * Name: tiva_i2c9_interrupt
- *
- * Description:
- *   I2C9 interrupt service routine
- *
- ************************************************************************************/
-
-#if !defined(CONFIG_I2C_POLLED) && defined(CONFIG_TIVA_I2C9)
-static int tiva_i2c9_interrupt(int irq, void *context, FAR void *arg)
-{
-  struct tiva_i2c_priv_s *priv;
-  uint32_t status;
-
-  /* Read the masked interrupt status */
-
-  priv   = &tiva_i2c9_priv;
-  status = tiva_i2c_getreg(priv, TIVA_I2CM_MIS_OFFSET);
-
-  /* Let the common interrupt handler do the rest of the work */
-
-  return tiva_i2c_interrupt(priv, status);
 }
 #endif
 
@@ -1758,7 +1494,7 @@ static int tiva_i2c_initialize(struct tiva_i2c_priv_s *priv, uint32_t frequency)
    */
 
 #ifndef CONFIG_I2C_POLLED
-  (void)irq_attach(config->irq, config->isr, NULL);
+  (void)irq_attach(config->irq, tiva_i2c_interrupt, priv);
   up_enable_irq(config->irq);
 #endif
 

configs/nucleo-f072rb/README.txt

@@ -17,32 +17,16 @@ Contents
 
 Status
 ======
-  2017-04-27:  There are many problems.  On start up, I have to reset
+  2017-04-28:  After struggling with some clock configuration and FLASH wait
-    several times before I get NSH prompt (or parts of it).  Apparently the
+    state issues, the board now boots and the basic NSH configurations works
-    STM32 is either hanging (perhaps in clockconfig()) or perhaps it has
+    without problem.
-    taken a hard fault before it is able to generate debug output?
 
-   There are many hardfaults during initial serial output.  This change
+    A USB device driver was added along with support for clocking from the
-   seems to eliminate those hardfaults:
+    HSI48.  That driver remains untested.
 
-      @@ -2163,7 +2163,7 @@ static void stm32f0serial_txint(FAR struct uart_dev_s *dev, bool enable)
+  2017-04-30:  I tried using the I2C driver with the I2C tool (apps/system/i2c).
-            * interrupts disabled (note this may recurse).
+    I may have something wrong, but at present the driver is just timing out
-            */
+    on all transfers.
-
-    -      uart_xmitchars(dev);
-    +//      uart_xmitchars(dev);
-     #endif
-         }
-       else
-
-   Which implies that the hardfaults are due to runaway recursion in the
-   serial driver?  This suggest some error in either determining when there
-   is TX data available or in disabling TX interrupts.
-
-   But this not a solution.  Even without the hard faults, it may hang
-   attempting to output the NSH greeting and prompt or hang unable to
-   receive input.  These symptoms suggest some issue with TX and RX
-   interrupt handling.
 
 Nucleo-64 Boards
 ================
@@ -155,6 +139,8 @@ Serial Console
          PA14
          PD5
 
+  See "Virtual COM Port" and "RS-232 Shield" below.
+
   USART3
   ------
   Pins and Connectors:
@@ -168,8 +154,6 @@ Serial Console
          PC10
          D8
 
-  See "Virtual COM Port" and "RS-232 Shield" below.
-
   USART3
   ------
   Pins and Connectors:
@@ -197,8 +181,8 @@ Serial Console
 
   Configuring USART2 is the same as given above.
 
-  Question:  What BAUD should be configure to interface with the Virtual
+  115200 8N1 BAUD should be configure to interface with the Virtual COM
-  COM port?  115200 8N1?
+  port.
 
   Default
   -------

configs/nucleo-f072rb/include/board.h

@@ -230,12 +230,19 @@
 /* Alternate Pin Functions **********************************************************/
 /* USART 1 */
 
-#define GPIO_USART1_TX           GPIO_USART1_TX_2
+#define GPIO_USART1_TX           GPIO_USART1_TX_2 /* PA9  CN10 pin 21 */
-#define GPIO_USART1_RX           GPIO_USART1_RX_2
+#define GPIO_USART1_RX           GPIO_USART1_RX_2 /* PA10 CN10 pin 33 */
 
 /* USART 2 */
 
-#define GPIO_USART2_TX           GPIO_USART2_TX_3
+#define GPIO_USART2_TX           GPIO_USART2_TX_3 /* PA2  St-Link VCOM */
-#define GPIO_USART2_RX           GPIO_USART2_RX_3
+#define GPIO_USART2_RX           GPIO_USART2_RX_3 /* PA3  St-Link VCOM */
+
+/* I2C1 */
+
+#define GPIO_I2C1_SCL            GPIO_I2C1_SCL_2  /* PB8  CN5 pin 10, D15 */
+#define GPIO_I2C1_SDA            GPIO_I2C1_SDA_2  /* PB9  CN5 pin 9, D14 */
+
+/* I2C2 */
 
 #endif  /* __CONFIG_NUCLEO_F072RB_INCLUDE_BOARD_H */

configs/nucleo-f072rb/src/stm32_bringup.c

@@ -43,8 +43,20 @@
 #include <sys/types.h>
 #include <debug.h>
 
+#include <nuttx/i2c/i2c_master.h>
+
+#include "stm32f0_i2c.h"
 #include "nucleo-f072rb.h"
 
+/****************************************************************************
+ * Pre-processor Defintiionis
+ ****************************************************************************/
+
+#undef HAVE_I2C_DRIVER
+#if defined(CONFIG_STM32F0_I2C1) && defined(CONFIG_I2C_DRIVER)
+#  define HAVE_I2C_DRIVER 1
+#endif
+
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -65,6 +77,9 @@
 
 int stm32_bringup(void)
 {
+#ifdef HAVE_I2C_DRIVER
+  FAR struct i2c_master_s *i2c;
+#endif
   int ret;
 
 #ifdef CONFIG_FS_PROCFS
@@ -77,6 +92,26 @@ int stm32_bringup(void)
     }
 #endif
 
+#ifdef HAVE_I2C_DRIVER
+  /* Get the I2C lower half instance */
+
+  i2c = stm32f0_i2cbus_initialize(1);
+  if (i2c == NULL)
+    {
+      i2cerr("ERROR: Inialize I2C1: %d\n", ret);
+    }
+  else
+    {
+      /* Regiser the I2C character driver */
+
+      ret = i2c_register(i2c, 1);
+      if (ret < 0)
+        {
+          i2cerr("ERROR: Failed to register I2C1 device: %d\n", ret);
+        }
+    }
+#endif
+
   UNUSED(ret);
   return OK;
 }

configs/stm32f0discovery/include/board.h

@@ -239,4 +239,9 @@
 #define GPIO_USART1_TX           GPIO_USART1_TX_1
 #define GPIO_USART1_RX           GPIO_USART1_RX_1
 
+/* I2C pins definition */
+
+#define GPIO_I2C1_SCL            GPIO_I2C1_SCL_1
+#define GPIO_I2C1_SDA            GPIO_I2C1_SDA_1
+
 #endif  /* __CONFIG_STM32F0DISCOVERY_INCLUDE_BOARD_H */

drivers/i2c/i2c_driver.c

@@ -82,8 +82,10 @@ struct i2c_driver_s
  * Private Function Prototypes
  ****************************************************************************/
 
+#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
 static int     i2cdrvr_open(FAR struct file *filep);
 static int     i2cdrvr_close(FAR struct file *filep);
+#endif
 static ssize_t i2cdrvr_read(FAR struct file *filep, FAR char *buffer,
                  size_t buflen);
 static ssize_t i2cdrvr_write(FAR struct file *filep, FAR const char *buffer,
@@ -253,6 +255,7 @@ static int i2cdrvr_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
   priv = (FAR struct i2c_driver_s *)inode->i_private;
   DEBUGASSERT(priv);
 
+#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   /* Get exclusive access to the I2C driver state structure */
 
   ret = sem_wait(&priv->exclsem);
@@ -262,6 +265,7 @@ static int i2cdrvr_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
       DEBUGASSERT(errcode < 0);
       return -errcode;
     }
+#endif
 
   /* Process the IOCTL command */
 
@@ -306,7 +310,9 @@ static int i2cdrvr_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
         break;
     }
 
+#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   sem_post(&priv->exclsem);
+#endif
   return ret;
 }
 

include/nuttx/analog/ltc1867l.h

@@ -97,12 +97,12 @@ enum ltc1867l_analog_input_mode_e
   LTC1867L_BIPOLAR = 0,
 };
 
-struct ltc1867l_channel_config_s
+begin_packed_struct struct ltc1867l_channel_config_s
 {
   uint8_t channel;                                                     /* This will be the channel number returned in struct adc_msg_s for a conversion */
   enum ltc1867l_analog_multiplexer_config_e analog_multiplexer_config; /* Analog multiplexer configuration */
   enum ltc1867l_analog_input_mode_e analog_inputMode;                  /* Analog input mode */
-} packed_struct;
+} end_packed_struct;
 
 /****************************************************************************
  * Public Function Prototypes

include/nuttx/sensors/lis2dh.h

@@ -273,25 +273,25 @@ enum lis2dh_interrupt_mode
   LIS2DH_6D_POSITION = 0xc0,
 };
 
-struct lis2dh_vector_s
+begin_packed_struct struct lis2dh_vector_s
 {
   int16_t  x, y, z;
-} packed_struct;
+} end_packed_struct;
 
-struct lis2dh_res_header
+begin_packed_struct struct lis2dh_res_header
 {
   uint8_t meas_count;
   bool    int1_occurred;
   uint8_t int1_source;
   bool    int2_occurred;
   uint8_t int2_source;
-} packed_struct;
+} end_packed_struct;
 
-struct lis2dh_result
+begin_packed_struct struct lis2dh_result
 {
   struct lis2dh_res_header header;
   struct lis2dh_vector_s measurements[0];
-} packed_struct;
+} end_packed_struct;
 
 struct lis2dh_setup
 {
@@ -402,12 +402,12 @@ struct lis2dh_config_s
   CODE bool (*read_int2_pin)(void);
 };
 
-struct lis2dh_raw_data_s
+begin_packed_struct struct lis2dh_raw_data_s
 {
   uint16_t out_x;
   uint16_t out_y;
   uint16_t out_z;
-} packed_struct;
+} end_packed_struct;
 
 typedef struct lis2dh_raw_data_s lis2dh_raw_data_t;
 

include/nuttx/spi/spi.h

@@ -432,9 +432,10 @@
 #define SPIDEVID_TYPE (devid) (((uint32_t)(devid) >> 16) & 0xffff)
 #define SPIDEVID_INDEX(devid)  ((uint32_t)(devid)        & 0xffff)
 
-/* These are replacement definitions for the currently used SPI device indexes.
+/* These are standard definitions for the defined SPI device IDs.  The index
- * The argument, n, is the instance number. This should be zero is there is
+ * argument, n, is the instance number.  This should be zero if there is
- * only one instance of the SPI device on the bus.
+ * only one instance of the SPI device on the SPI bus. Indices greater than
+ * zero discriminate the additional devices of the same type on the SPI bus.
  */
 
 #define SPIDEV_NONE(n)          SPIDEV_ID(SPIDEVTYPE_NONE,          (n))

include/nuttx/wireless/ieee80211/ieee80211.h

@@ -0,0 +1,889 @@
+/****************************************************************************
+ * include/nuttx/wireless/ieee80211/ieee80211.h
+ * 802.11 protocol definitions.
+ *
+ * Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __INCLUDE_NUTTX_WIRELESS_IEEE80211_IEEE80211_H
+#define __INCLUDE_NUTTX_WIRELESS_IEEE80211_IEEE80211_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/compiler.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define IEEE80211_ADDR_LEN          6  /* size of 802.11 address */
+
+/* is 802.11 address multicast/broadcast? */
+
+#define IEEE80211_IS_MULTICAST(_a)  (*(_a) & 0x01)
+
+/* htframe */
+
+#define IEEE80211_FC0_VERSION_MASK          0x03
+#define IEEE80211_FC0_VERSION_SHIFT         0
+#define IEEE80211_FC0_VERSION_0             0x00
+#define IEEE80211_FC0_TYPE_MASK             0x0c
+#define IEEE80211_FC0_TYPE_SHIFT            2
+#define IEEE80211_FC0_TYPE_MGT              0x00
+#define IEEE80211_FC0_TYPE_CTL              0x04
+#define IEEE80211_FC0_TYPE_DATA             0x08
+
+#define IEEE80211_FC0_SUBTYPE_MASK          0xf0
+#define IEEE80211_FC0_SUBTYPE_SHIFT         4
+
+/* for TYPE_MGT */
+
+#define IEEE80211_FC0_SUBTYPE_ASSOC_REQ     0x00
+#define IEEE80211_FC0_SUBTYPE_ASSOC_RESP    0x10
+#define IEEE80211_FC0_SUBTYPE_REASSOC_REQ   0x20
+#define IEEE80211_FC0_SUBTYPE_REASSOC_RESP  0x30
+#define IEEE80211_FC0_SUBTYPE_PROBE_REQ     0x40
+#define IEEE80211_FC0_SUBTYPE_PROBE_RESP    0x50
+#define IEEE80211_FC0_SUBTYPE_BEACON        0x80
+#define IEEE80211_FC0_SUBTYPE_ATIM          0x90
+#define IEEE80211_FC0_SUBTYPE_DISASSOC      0xa0
+#define IEEE80211_FC0_SUBTYPE_AUTH          0xb0
+#define IEEE80211_FC0_SUBTYPE_DEAUTH        0xc0
+#define IEEE80211_FC0_SUBTYPE_ACTION        0xd0
+#define IEEE80211_FC0_SUBTYPE_ACTION_NOACK  0xe0  /* 11n */
+
+/* for TYPE_CTL */
+
+#define IEEE80211_FC0_SUBTYPE_WRAPPER       0x70  /* 11n */
+#define IEEE80211_FC0_SUBTYPE_BAR           0x80
+#define IEEE80211_FC0_SUBTYPE_BA            0x90
+#define IEEE80211_FC0_SUBTYPE_PS_POLL       0xa0
+#define IEEE80211_FC0_SUBTYPE_RTS           0xb0
+#define IEEE80211_FC0_SUBTYPE_CTS           0xc0
+#define IEEE80211_FC0_SUBTYPE_ACK           0xd0
+#define IEEE80211_FC0_SUBTYPE_CF_END        0xe0
+#define IEEE80211_FC0_SUBTYPE_CF_END_ACK    0xf0
+
+/* for TYPE_DATA (bit combination) */
+
+#define IEEE80211_FC0_SUBTYPE_DATA          0x00
+#define IEEE80211_FC0_SUBTYPE_CF_ACK        0x10
+#define IEEE80211_FC0_SUBTYPE_CF_POLL       0x20
+#define IEEE80211_FC0_SUBTYPE_CF_ACPL       0x30
+#define IEEE80211_FC0_SUBTYPE_NODATA        0x40
+#define IEEE80211_FC0_SUBTYPE_CFACK         0x50
+#define IEEE80211_FC0_SUBTYPE_CFPOLL        0x60
+#define IEEE80211_FC0_SUBTYPE_CF_ACK_CF_ACK 0x70
+#define IEEE80211_FC0_SUBTYPE_QOS           0x80
+
+#define IEEE80211_FC1_DIR_MASK              0x03
+#define IEEE80211_FC1_DIR_NODS              0x00  /* STA->STA */
+#define IEEE80211_FC1_DIR_TODS              0x01  /* STA->AP */
+#define IEEE80211_FC1_DIR_FROMDS            0x02
+                                                  /* AP ->STA */
+#define IEEE80211_FC1_DIR_DSTODS            0x03
+                                                  /* AP ->AP */
+
+#define IEEE80211_FC1_MORE_FRAG             0x04
+#define IEEE80211_FC1_RETRY                 0x08
+#define IEEE80211_FC1_PWR_MGT               0x10
+#define IEEE80211_FC1_MORE_DATA             0x20
+#define IEEE80211_FC1_PROTECTED             0x40
+#define IEEE80211_FC1_WEP                   0x40  /* pre-RSNA compat */
+#define IEEE80211_FC1_ORDER                 0x80
+#define IEEE80211_FC1_BITS \
+    "\20\03MORE_FRAG\04RETRY\05PWR_MGT\06MORE_DATA" \
+    "\07PROTECTED\08ORDER"
+
+/* Sequence Control field (see 7.1.3.4). */
+
+#define IEEE80211_SEQ_FRAG_MASK            0x000f
+#define IEEE80211_SEQ_FRAG_SHIFT           0
+#define IEEE80211_SEQ_SEQ_MASK             0xfff0
+#define IEEE80211_SEQ_SEQ_SHIFT            4
+
+#define IEEE80211_NWID_LEN                 32
+#define IEEE80211_MMIE_LEN                 18  /* 11w */
+
+/* QoS Control field (see 7.1.3.5). */
+
+#define IEEE80211_QOS_TXOP                 0xff00
+#define IEEE80211_QOS_AMSDU                0x0080  /* 11n */
+#define IEEE80211_QOS_ACK_POLICY_NORMAL    0x0000
+#define IEEE80211_QOS_ACK_POLICY_NOACK     0x0020
+#define IEEE80211_QOS_ACK_POLICY_NOEXPLACK 0x0040
+#define IEEE80211_QOS_ACK_POLICY_BA        0x0060
+#define IEEE80211_QOS_ACK_POLICY_MASK      0x0060
+#define IEEE80211_QOS_ACK_POLICY_SHIFT     5
+#define IEEE80211_QOS_EOSP                 0x0010
+#define IEEE80211_QOS_TID                  0x000f
+
+/* Capability Information field (see 7.3.1.4) */
+
+#define IEEE80211_CAPINFO_ESS              0x0001
+#define IEEE80211_CAPINFO_IBSS             0x0002
+#define IEEE80211_CAPINFO_CF_POLLABLE      0x0004
+#define IEEE80211_CAPINFO_CF_POLLREQ       0x0008
+#define IEEE80211_CAPINFO_PRIVACY          0x0010
+#define IEEE80211_CAPINFO_SHORT_PREAMBLE   0x0020
+#define IEEE80211_CAPINFO_PBCC             0x0040
+#define IEEE80211_CAPINFO_CHNL_AGILITY     0x0080
+#define IEEE80211_CAPINFO_SPECTRUM_MGMT    0x0100
+#define IEEE80211_CAPINFO_QOS              0x0200
+#define IEEE80211_CAPINFO_SHORT_SLOTTIME   0x0400
+#define IEEE80211_CAPINFO_APSD             0x0800
+
+/* bit 12 is reserved */
+
+#define IEEE80211_CAPINFO_DSSSOFDM         0x2000
+#define IEEE80211_CAPINFO_DELAYED_B_ACK    0x4000
+#define IEEE80211_CAPINFO_IMMEDIATE_B_ACK  0x8000
+#define IEEE80211_CAPINFO_BITS \
+    "\10\01ESS\02IBSS\03CF_POLLABLE\04CF_POLLREQ" \
+    "\05PRIVACY\06SHORT_PREAMBLE\07PBCC\10CHNL_AGILITY" \
+    "\11SPECTRUM_MGMT\12QOS\13SHORT_SLOTTIME\14APSD" \
+    "\16DSSSOFDM\17DELAYED_B_ACK\20IMMEDIATE_B_ACK"
+
+/* Block Ack Action field values (see Table 7-54). */
+
+#define IEEE80211_ACTION_ADDBA_REQ         0
+#define IEEE80211_ACTION_ADDBA_RESP        1
+#define IEEE80211_ACTION_DELBA             2
+
+/* SA Query Action field values (see Table 7-57l). */
+
+#define IEEE80211_ACTION_SA_QUERY_REQ      0
+#define IEEE80211_ACTION_SA_QUERY_RESP     1
+
+/* HT Action field values (see Table 7-57m). */
+
+#define IEEE80211_ACTION_NOTIFYCW          0
+
+#define IEEE80211_RATE_BASIC               0x80
+#define IEEE80211_RATE_VAL                 0x7f
+#define IEEE80211_RATE_SIZE                8    /* 802.11 standard */
+#define IEEE80211_RATE_MAXSIZE             15   /* max rates we'll handle */
+
+/* BlockAck/BlockAckReq Control field (see Figure 7-13). */
+
+#define IEEE80211_BA_ACK_POLICY            0x0001
+#define IEEE80211_BA_MULTI_TID             0x0002
+#define IEEE80211_BA_COMPRESSED            0x0004
+#define IEEE80211_BA_TID_INFO_MASK         0xf000
+#define IEEE80211_BA_TID_INFO_SHIFT        12
+
+/* DELBA Parameter Set field (see Figure 7-34). */
+
+#define IEEE80211_DELBA_INITIATOR          0x0800
+
+/* ERP information element (see 7.3.2.13). */
+
+#define IEEE80211_ERP_NON_ERP_PRESENT      0x01
+#define IEEE80211_ERP_USE_PROTECTION       0x02
+#define IEEE80211_ERP_BARKER_MODE          0x04
+
+/* RSN capabilities (see 7.3.2.25.3). */
+
+#define IEEE80211_RSNCAP_PREAUTH           0x0001
+#define IEEE80211_RSNCAP_NOPAIRWISE        0x0002
+#define IEEE80211_RSNCAP_PTKSA_RCNT_MASK   0x000c
+#define IEEE80211_RSNCAP_PTKSA_RCNT_SHIFT  2
+#define IEEE80211_RSNCAP_GTKSA_RCNT_MASK   0x0030
+#define IEEE80211_RSNCAP_GTKSA_RCNT_SHIFT  4
+#define IEEE80211_RSNCAP_RCNT1             0
+#define IEEE80211_RSNCAP_RCNT2             1
+#define IEEE80211_RSNCAP_RCNT4             2
+#define IEEE80211_RSNCAP_RCNT16            3
+#define IEEE80211_RSNCAP_MFPR              0x0040  /* 11w */
+#define IEEE80211_RSNCAP_MFPC              0x0080  /* 11w */
+#define IEEE80211_RSNCAP_PEERKEYENA        0x0200
+#define IEEE80211_RSNCAP_SPPAMSDUC         0x0400  /* 11n */
+#define IEEE80211_RSNCAP_SPPAMSDUR         0x0800  /* 11n */
+#define IEEE80211_RSNCAP_PBAC              0x1000  /* 11n */
+
+/* HT Capabilities Info (see 7.3.2.57.2). */
+
+#define IEEE80211_HTCAP_LDPC               0x00000001
+#define IEEE80211_HTCAP_CBW20_40           0x00000002
+#define IEEE80211_HTCAP_SMPS_MASK          0x0000000c
+#define IEEE80211_HTCAP_SMPS_SHIFT         2
+#define IEEE80211_HTCAP_SMPS_STA           0
+#define IEEE80211_HTCAP_SMPS_DYN           1
+#define IEEE80211_HTCAP_SMPS_DIS           3
+#define IEEE80211_HTCAP_GF                 0x00000010
+#define IEEE80211_HTCAP_SGI20              0x00000020
+#define IEEE80211_HTCAP_SGI40              0x00000040
+#define IEEE80211_HTCAP_TXSTBC             0x00000080
+#define IEEE80211_HTCAP_RXSTBC_MASK        0x00000300
+#define IEEE80211_HTCAP_RXSTBC_SHIFT       8
+#define IEEE80211_HTCAP_DELAYEDBA          0x00000400
+#define IEEE80211_HTCAP_AMSDU7935          0x00000800
+#define IEEE80211_HTCAP_DSSSCCK40          0x00001000
+#define IEEE80211_HTCAP_PSMP               0x00002000
+#define IEEE80211_HTCAP_40INTOLERANT       0x00004000
+#define IEEE80211_HTCAP_LSIGTXOPPROT       0x00008000
+
+/* HT Extended Capabilities (see 7.3.2.57.5).*/
+
+#define IEEE80211_HTXCAP_PCO               0x0001
+#define IEEE80211_HTXCAP_PCOTT_MASK        0x0006
+#define IEEE80211_HTXCAP_PCOTT_SHIFT       1
+#define IEEE80211_HTXCAP_PCOTT_400         1
+#define IEEE80211_HTXCAP_PCOTT_1500        2
+#define IEEE80211_HTXCAP_PCOTT_5000        3
+
+/* Bits 3-7 are reserved. */
+
+#define IEEE80211_HTXCAP_MFB_MASK          0x0300
+#define IEEE80211_HTXCAP_MFB_SHIFT         8
+#define IEEE80211_HTXCAP_MFB_NONE          0
+#define IEEE80211_HTXCAP_MFB_UNSOL         2
+#define IEEE80211_HTXCAP_MFB_BOTH          3
+#define IEEE80211_HTXCAP_HTC               0x0400
+#define IEEE80211_HTXCAP_RDRESP            0x0800
+
+/* Bits 12-15 are reserved. */
+
+/* Transmit Beamforming (TxBF) Capabilities (see 7.3.2.57.6). */
+
+#define IEEE80211_TXBFCAP_IMPLICIT_RX      0x00000001
+#define IEEE80211_TXBFCAP_RSSC             0x00000002
+#define IEEE80211_TXBFCAP_TSSC             0x00000004
+#define IEEE80211_TXBFCAP_RNDP             0x00000008
+#define IEEE80211_TXBFCAP_TNDP             0x00000010
+#define IEEE80211_TXBFCAP_IMPLICIT_TX      0x00000020
+#define IEEE80211_TXBFCAP_CALIB_MASK       0x000000c0
+#define IEEE80211_TXBFCAP_CALIB_SHIFT      6
+#define IEEE80211_TXBFCAP_TX_CSI           0x00000100
+
+/* Antenna Selection (ASEL) Capability (see 7.3.2.57.7). */
+
+#define IEEE80211_ASELCAP_ASEL             0x01
+#define IEEE80211_ASELCAP_CSIFB            0x02
+
+/* Bit 7 is reserved. */
+
+/* HT Operation element (see 7.3.2.58). */
+
+/* Byte 1. */
+
+#define IEEE80211_HTOP0_SCO_MASK           0x03
+#define IEEE80211_HTOP0_SCO_SHIFT          0
+#define IEEE80211_HTOP0_SCO_SCN            0
+#define IEEE80211_HTOP0_SCO_SCA            1
+#define IEEE80211_HTOP0_SCO_SCB            3
+#define IEEE80211_HTOP0_CHW                0x04
+#define IEEE80211_HTOP0_RIFS               0x08
+#define IEEE80211_HTOP0_SPSMP              0x10
+#define IEEE80211_HTOP0_SIG_MASK           0xe0
+#define IEEE80211_HTOP0_SIG_SHIFT          5
+
+/* Bytes 2-3. */
+
+#define IEEE80211_HTOP1_PROT_MASK          0x0003
+#define IEEE80211_HTOP1_PROT_SHIFT         0
+#define IEEE80211_HTOP1_NONGTSTA           0x0004
+
+/* Bit 3 is reserved. */
+
+#define IEEE80211_HTOP1_OBSS_NONHTSTA      0x0010
+
+/* Bits 5-15 are reserved. */
+
+/* Bytes 4-5. */
+
+/* Bits 0-5 are reserved. */
+
+#define IEEE80211_HTOP2_DUALBEACON         0x0040
+#define IEEE80211_HTOP2_DUALCTSPROT        0x0080
+#define IEEE80211_HTOP2_STBCBEACON         0x0100
+#define IEEE80211_HTOP2_LSIGTXOP           0x0200
+#define IEEE80211_HTOP2_PCOACTIVE          0x0400
+#define IEEE80211_HTOP2_PCOPHASE40         0x0800
+
+/* Bits 12-15 are reserved. */
+
+/* EDCA Access Categories. */
+
+#define EDCA_NUM_AC                        4
+
+/* Number of TID values (traffic identifier) */
+
+#define IEEE80211_NUM_TID                  16
+
+/* Atheros private advanced capabilities info */
+
+#define ATHEROS_CAP_TURBO_PRIME            0x01
+#define ATHEROS_CAP_COMPRESSION            0x02
+#define ATHEROS_CAP_FAST_FRAME             0x04
+
+/* bits 3-6 reserved */
+
+#define ATHEROS_CAP_BOOST                  0x80
+
+/* Organizationally Unique Identifiers.
+ * See http://standards.ieee.org/regauth/oui/oui.txt for a list.
+ */
+ 
+#define ATHEROS_OUI                        ((const uint8_t[]){ 0x00, 0x03, 0x7f })
+#define BROADCOM_OUI                       ((const uint8_t[]){ 0x00, 0x90, 0x4c })
+#define IEEE80211_OUI                      ((const uint8_t[]){ 0x00, 0x0f, 0xac })
+#define MICROSOFT_OUI                     ((const uint8_t[]){ 0x00, 0x50, 0xf2 })
+
+#define IEEE80211_AUTH_ALGORITHM(auth) \
+    ((auth)[0] | ((auth)[1] << 8))
+#define IEEE80211_AUTH_TRANSACTION(auth) \
+    ((auth)[2] | ((auth)[3] << 8))
+#define IEEE80211_AUTH_STATUS(auth) \
+    ((auth)[4] | ((auth)[5] << 8))
+
+/* Authentication Algorithm Number field (see 7.3.1.1). */
+
+#define IEEE80211_AUTH_ALG_OPEN            0x0000
+#define IEEE80211_AUTH_ALG_SHARED          0x0001
+#define IEEE80211_AUTH_ALG_LEAP            0x0080
+
+/* WEP */
+
+#define IEEE80211_WEP_KEYLEN               5   /* 40bit */
+#define IEEE80211_WEP_NKID                 4   /* number of key ids */
+#define IEEE80211_CHALLENGE_LEN            128
+
+/* WEP header constants */
+
+#define IEEE80211_WEP_IVLEN                3   /* 24bit */
+#define IEEE80211_WEP_KIDLEN               1   /* 1 octet */
+#define IEEE80211_WEP_CRCLEN               4   /* CRC-32 */
+#define IEEE80211_CRC_LEN                  4
+#define IEEE80211_WEP_TOTLEN \
+    (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN)
+
+/* 802.11i defines an extended IV for use with non-WEP ciphers.
+ * When the EXTIV bit is set in the key id byte an additional
+ * 4 bytes immediately follow the IV for TKIP.  For CCMP the
+ * EXTIV bit is likewise set but the 8 bytes represent the
+ * CCMP header rather than IV+extended-IV.
+ */
+
+#define IEEE80211_WEP_EXTIV                0x20
+#define IEEE80211_WEP_EXTIVLEN             4    /* extended IV length */
+#define IEEE80211_WEP_MICLEN               8    /* trailing MIC */
+
+/* Maximum acceptable MTU is:
+ *    IEEE80211_MAX_LEN - WEP overhead - CRC -
+ *        QoS overhead - RSN/WPA overhead
+ * Min is arbitrarily chosen > IEEE80211_MIN_LEN.  The default
+ * mtu is Ethernet-compatible.
+ */
+
+#define IEEE80211_MTU_MAX                  2290
+#define IEEE80211_MTU_MIN                  32
+
+#define IEEE80211_MAX_LEN \
+    (2300 + IEEE80211_CRC_LEN + \
+    (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN))
+#define IEEE80211_ACK_LEN \
+    (sizeof(struct ieee80211_frame_ack) + IEEE80211_CRC_LEN)
+#define IEEE80211_MIN_LEN \
+    (sizeof(struct ieee80211_frame_min) + IEEE80211_CRC_LEN)
+
+/* The 802.11 spec says at most 2007 stations may be
+ * associated at once.  For most AP's this is way more
+ * than is feasible so we use a default of 1800. This
+ * number may be overridden by the driver and/or by
+ * user configuration.
+ */
+
+#define IEEE80211_AID_MAX                  2007
+#define IEEE80211_AID_DEF                  1800
+#define IEEE80211_AID(b)                   ((b) &~ 0xc000)
+
+/* RTS frame length parameters.  The default is specified in
+ * the 802.11 spec.  The max may be wrong for jumbo frames.
+ */
+
+#define IEEE80211_RTS_DEFAULT              512
+#define IEEE80211_RTS_MIN                  1
+#define IEEE80211_RTS_MAX                  IEEE80211_MAX_LEN
+
+#define IEEE80211_PLCP_SERVICE             0x00
+#define IEEE80211_PLCP_SERVICE_PBCC        0x08   /* PBCC encoded */
+#define IEEE80211_PLCP_SERVICE_LENEXT      0x80 /* length extension bit */
+
+/* One Time Unit (TU) is 1Kus = 1024 microseconds. */
+
+#define IEEE80211_DUR_TU                   1024
+
+/* IEEE 802.11b durations for DSSS PHY in microseconds */
+
+#define IEEE80211_DUR_DS_LONG_PREAMBLE     144
+#define IEEE80211_DUR_DS_SHORT_PREAMBLE    72
+#define IEEE80211_DUR_DS_PREAMBLE_DIFFERENCE \
+    (IEEE80211_DUR_DS_LONG_PREAMBLE - IEEE80211_DUR_DS_SHORT_PREAMBLE)
+#define IEEE80211_DUR_DS_FAST_PLCPHDR      24
+#define IEEE80211_DUR_DS_SLOW_PLCPHDR      48
+#define IEEE80211_DUR_DS_PLCPHDR_DIFFERENCE \
+    (IEEE80211_DUR_DS_SLOW_PLCPHDR - IEEE80211_DUR_DS_FAST_PLCPHDR)
+#define IEEE80211_DUR_DS_SLOW_ACK          112
+#define IEEE80211_DUR_DS_FAST_ACK          56
+#define IEEE80211_DUR_DS_SLOW_CTS          112
+#define IEEE80211_DUR_DS_FAST_CTS          56
+#define IEEE80211_DUR_DS_SLOT              20
+#define IEEE80211_DUR_DS_SIFS              10
+#define IEEE80211_DUR_DS_PIFS \
+    (IEEE80211_DUR_DS_SIFS + IEEE80211_DUR_DS_SLOT)
+#define IEEE80211_DUR_DS_DIFS \
+    (IEEE80211_DUR_DS_SIFS + 2 * IEEE80211_DUR_DS_SLOT)
+#define IEEE80211_DUR_DS_EIFS    (IEEE80211_DUR_DS_SIFS + \
+    IEEE80211_DUR_DS_SLOW_ACK + \
+    IEEE80211_DUR_DS_LONG_PREAMBLE + \
+    IEEE80211_DUR_DS_SLOW_PLCPHDR + \
+    IEEE80211_DUR_DIFS)
+
+/* The RSNA key descriptor used by IEEE 802.11 does not use the IEEE 802.1X
+ * key descriptor.  Instead, it uses the key descriptor described in 8.5.2.
+ */
+
+#define EAPOL_KEY_NONCE_LEN                32
+#define EAPOL_KEY_IV_LEN                   16
+#define EAPOL_KEY_MIC_LEN                  16
+
+/* Pairwise Transient Key (see 8.5.1.2) */
+
+#define IEEE80211_PMKID_LEN    16
+#define IEEE80211_SMKID_LEN    16
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/* Generic definitions for IEEE 802.11 frames */
+
+begin_packed_struct struct ieee80211_frame
+{
+  uint8_t i_fc[2];
+  uint8_t i_dur[2];
+  uint8_t i_addr1[IEEE80211_ADDR_LEN];
+  uint8_t i_addr2[IEEE80211_ADDR_LEN];
+  uint8_t i_addr3[IEEE80211_ADDR_LEN];
+  uint8_t i_seq[2];
+} end_packed_struct;
+
+begin_packed_struct struct ieee80211_qosframe
+{
+  uint8_t i_fc[2];
+  uint8_t i_dur[2];
+  uint8_t i_addr1[IEEE80211_ADDR_LEN];
+  uint8_t i_addr2[IEEE80211_ADDR_LEN];
+  uint8_t i_addr3[IEEE80211_ADDR_LEN];
+  uint8_t i_seq[2];
+  uint8_t i_qos[2];
+} end_packet_struct;
+
+begin_packed_struct struct ieee80211_htframe  /* 11n */
+{
+  uint8_t i_fc[2];
+  uint8_t i_dur[2];
+  uint8_t i_addr1[IEEE80211_ADDR_LEN];
+  uint8_t i_addr2[IEEE80211_ADDR_LEN];
+  uint8_t i_addr3[IEEE80211_ADDR_LEN];
+  uint8_t i_seq[2];
+  uint8_t i_qos[2];
+  uint8_t i_ht[4];
+} end_packet_struct;
+
+begin_packed_struct struct ieee80211_frame_addr4
+{
+  uint8_t i_fc[2];
+  uint8_t i_dur[2];
+  uint8_t i_addr1[IEEE80211_ADDR_LEN];
+  uint8_t i_addr2[IEEE80211_ADDR_LEN];
+  uint8_t i_addr3[IEEE80211_ADDR_LEN];
+  uint8_t i_seq[2];
+  uint8_t i_addr4[IEEE80211_ADDR_LEN];
+} end_packet_struct;
+
+begin_packed_struct struct ieee80211_qosframe_addr4
+{
+  uint8_t i_fc[2];
+  uint8_t i_dur[2];
+  uint8_t i_addr1[IEEE80211_ADDR_LEN];
+  uint8_t i_addr2[IEEE80211_ADDR_LEN];
+  uint8_t i_addr3[IEEE80211_ADDR_LEN];
+  uint8_t i_seq[2];
+  uint8_t i_addr4[IEEE80211_ADDR_LEN];
+  uint8_t i_qos[2];
+} end_packet_struct;
+
+begin_packed_struct struct ieee80211_htframe_addr4  /* 11n */
+{
+  uint8_t i_fc[2];
+  uint8_t i_dur[2];
+  uint8_t i_addr1[IEEE80211_ADDR_LEN];
+  uint8_t i_addr2[IEEE80211_ADDR_LEN];
+  uint8_t i_addr3[IEEE80211_ADDR_LEN];
+  uint8_t i_seq[2];
+  uint8_t i_addr4[IEEE80211_ADDR_LEN];
+  uint8_t i_qos[2];
+  uint8_t i_ht[4];
+} end_packet_struct;
+
+/* Control frames. */
+
+begin_packed_struct struct ieee80211_frame_min
+{
+    uint8_t i_fc[2];
+    uint8_t i_dur[2];
+    uint8_t i_addr1[IEEE80211_ADDR_LEN];
+    uint8_t i_addr2[IEEE80211_ADDR_LEN];
+
+    /* FCS */
+
+} end_packet_struct;
+
+begin_packed_struct struct ieee80211_frame_rts
+{
+    uint8_t i_fc[2];
+    uint8_t i_dur[2];
+    uint8_t i_ra[IEEE80211_ADDR_LEN];
+    uint8_t i_ta[IEEE80211_ADDR_LEN];
+
+    /* FCS */
+
+} end_packet_struct;
+
+struct ieee80211_frame_cts
+{
+    uint8_t i_fc[2];
+    uint8_t i_dur[2];
+    uint8_t i_ra[IEEE80211_ADDR_LEN];
+
+    /* FCS */
+
+} end_packet_struct;
+
+struct ieee80211_frame_ack
+{
+    uint8_t i_fc[2];
+    uint8_t i_dur[2];
+    uint8_t i_ra[IEEE80211_ADDR_LEN];
+
+    /* FCS */
+
+} end_packet_struct;
+
+struct ieee80211_frame_pspoll
+{
+    uint8_t i_fc[2];
+    uint8_t i_aid[2];
+    uint8_t i_bssid[IEEE80211_ADDR_LEN];
+    uint8_t i_ta[IEEE80211_ADDR_LEN];
+
+    /* FCS */
+
+} end_packet_struct;
+
+struct ieee80211_frame_cfend
+{                             /* NB: also CF-End+CF-Ack */
+  uint8_t i_fc[2];
+  uint8_t i_dur[2];           /* should be zero */
+  uint8_t i_ra[IEEE80211_ADDR_LEN];
+  uint8_t i_bssid[IEEE80211_ADDR_LEN];
+
+  /* FCS */
+
+} end_packet_struct;
+
+/* Information elements (see Table 7-26). */
+
+enum
+{
+  IEEE80211_ELEMID_SSID      = 0,
+  IEEE80211_ELEMID_RATES     = 1,
+  IEEE80211_ELEMID_FHPARMS   = 2,
+  IEEE80211_ELEMID_DSPARMS   = 3,
+  IEEE80211_ELEMID_CFPARMS   = 4,
+  IEEE80211_ELEMID_TIM       = 5,
+  IEEE80211_ELEMID_IBSSPARMS = 6,
+  IEEE80211_ELEMID_COUNTRY   = 7,
+  IEEE80211_ELEMID_QBSS_LOAD = 11,
+  IEEE80211_ELEMID_EDCAPARMS = 12,
+  IEEE80211_ELEMID_CHALLENGE = 16,
+
+  /* 17-31 reserved for challenge text extension */
+
+  IEEE80211_ELEMID_ERP       = 42,
+  IEEE80211_ELEMID_HTCAPS    = 45,  /* 11n */
+  IEEE80211_ELEMID_QOS_CAP   = 46,
+  IEEE80211_ELEMID_RSN       = 48,
+  IEEE80211_ELEMID_XRATES    = 50,
+  IEEE80211_ELEMID_TIE       = 56,  /* 11r */
+  IEEE80211_ELEMID_HTOP      = 61,  /* 11n */
+  IEEE80211_ELEMID_MMIE      = 76,  /* 11w */
+  IEEE80211_ELEMID_TPC       = 150,
+  IEEE80211_ELEMID_CCKM      = 156,
+  IEEE80211_ELEMID_VENDOR    = 221  /* vendor private */
+};
+
+/* Action field category values (see Table 7-24). */
+
+enum
+{
+  IEEE80211_CATEG_SPECTRUM   = 0,
+  IEEE80211_CATEG_QOS        = 1,
+  IEEE80211_CATEG_DLS        = 2,
+  IEEE80211_CATEG_BA         = 3,
+  IEEE80211_CATEG_HT         = 7,  /* 11n */
+  IEEE80211_CATEG_SA_QUERY   = 8   /* 11w */
+};
+
+/* EDCA Access Categories. */
+
+enum ieee80211_edca_ac
+{
+  EDCA_AC_BK                 = 1,  /* Background */
+  EDCA_AC_BE                 = 0,  /* Best Effort */
+  EDCA_AC_VI                 = 2,  /* Video */
+  EDCA_AC_VO                 = 3   /* Voice */
+};
+
+/* Authentication Transaction Sequence Number field (see 7.3.1.2). */
+
+enum
+{
+  IEEE80211_AUTH_OPEN_REQUEST  = 1,
+  IEEE80211_AUTH_OPEN_RESPONSE = 2
+};
+
+enum
+{
+  IEEE80211_AUTH_SHARED_REQUEST   = 1,
+  IEEE80211_AUTH_SHARED_CHALLENGE = 2,
+  IEEE80211_AUTH_SHARED_RESPONSE  = 3,
+  IEEE80211_AUTH_SHARED_PASS      = 4
+};
+
+/* Reason codes (see Table 22). */
+
+enum
+{
+  IEEE80211_REASON_UNSPECIFIED         = 1,
+  IEEE80211_REASON_AUTH_EXPIRE         = 2,
+  IEEE80211_REASON_AUTH_LEAVE          = 3,
+  IEEE80211_REASON_ASSOC_EXPIRE        = 4,
+  IEEE80211_REASON_ASSOC_TOOMANY       = 5,
+  IEEE80211_REASON_NOT_AUTHED          = 6,
+  IEEE80211_REASON_NOT_ASSOCED         = 7,
+  IEEE80211_REASON_ASSOC_LEAVE         = 8,
+  IEEE80211_REASON_ASSOC_NOT_AUTHED    = 9,
+
+  /* XXX the following two reason codes are not correct */
+
+  IEEE80211_REASON_RSN_REQUIRED        = 11,
+  IEEE80211_REASON_RSN_INCONSISTENT    = 12,
+
+  IEEE80211_REASON_IE_INVALID          = 13,
+  IEEE80211_REASON_MIC_FAILURE         = 14,
+  IEEE80211_REASON_4WAY_TIMEOUT        = 15,
+  IEEE80211_REASON_GROUP_TIMEOUT       = 16,
+  IEEE80211_REASON_RSN_DIFFERENT_IE    = 17,
+  IEEE80211_REASON_BAD_GROUP_CIPHER    = 18,
+  IEEE80211_REASON_BAD_PAIRWISE_CIPHER = 19,
+  IEEE80211_REASON_BAD_AKMP            = 20,
+  IEEE80211_REASON_RSN_IE_VER_UNSUP    = 21,
+  IEEE80211_REASON_RSN_IE_BAD_CAP      = 22,
+
+  IEEE80211_REASON_CIPHER_REJ_POLICY   = 24,
+
+  IEEE80211_REASON_SETUP_REQUIRED      = 38,
+  IEEE80211_REASON_TIMEOUT             = 39
+};
+
+/* Status codes (see Table 23). */
+
+enum
+{
+  IEEE80211_STATUS_SUCCESS             = 0,
+  IEEE80211_STATUS_UNSPECIFIED         = 1,
+  IEEE80211_STATUS_CAPINFO             = 10,
+  IEEE80211_STATUS_NOT_ASSOCED         = 11,
+  IEEE80211_STATUS_OTHER               = 12,
+  IEEE80211_STATUS_ALG                 = 13,
+  IEEE80211_STATUS_SEQUENCE            = 14,
+  IEEE80211_STATUS_CHALLENGE           = 15,
+  IEEE80211_STATUS_TIMEOUT             = 16,
+  IEEE80211_STATUS_TOOMANY             = 17,
+  IEEE80211_STATUS_BASIC_RATE          = 18,
+  IEEE80211_STATUS_SP_REQUIRED         = 19,
+  IEEE80211_STATUS_PBCC_REQUIRED       = 20,
+  IEEE80211_STATUS_CA_REQUIRED         = 21,
+  IEEE80211_STATUS_TOO_MANY_STATIONS   = 22,
+  IEEE80211_STATUS_RATES               = 23,
+  IEEE80211_STATUS_SHORTSLOT_REQUIRED  = 25,
+  IEEE80211_STATUS_DSSSOFDM_REQUIRED   = 26,
+
+  IEEE80211_STATUS_TRY_AGAIN_LATER     = 30,
+  IEEE80211_STATUS_MFP_POLICY          = 31,
+
+  IEEE80211_STATUS_REFUSED             = 37,
+  IEEE80211_STATUS_INVALID_PARAM       = 38,
+
+  IEEE80211_STATUS_IE_INVALID          = 40,
+  IEEE80211_STATUS_BAD_GROUP_CIPHER    = 41,
+  IEEE80211_STATUS_BAD_PAIRWISE_CIPHER = 42,
+  IEEE80211_STATUS_BAD_AKMP            = 43,
+  IEEE80211_STATUS_RSN_IE_VER_UNSUP    = 44,
+
+  IEEE80211_STATUS_CIPHER_REJ_POLICY   = 46,
+};
+
+struct ieee80211_eapol_key
+{
+  uint8_t version;
+
+#define EAPOL_VERSION               1
+
+  uint8_t type;
+
+/* IEEE Std 802.1X-2004, 7.5.4 (only type EAPOL-Key is used here) */
+
+#define EAP_PACKET                  0
+#define EAPOL_START                 1
+#define EAPOL_LOGOFF                2
+#define EAPOL_KEY                   3
+#define EAPOL_ASF_ALERT             4
+
+  uint8_t len[2];
+  uint8_t desc;
+
+/* IEEE Std 802.1X-2004, 7.6.1 */
+
+#define EAPOL_KEY_DESC_RC4          1   /* Deprecated */
+#define EAPOL_KEY_DESC_IEEE80211    2
+#define EAPOL_KEY_DESC_WPA          254 /* Non-standard WPA */
+
+  uint8_t info[2];
+
+#define EAPOL_KEY_VERSION_MASK      0x7
+#define EAPOL_KEY_DESC_V1           1
+#define EAPOL_KEY_DESC_V2           2
+#define EAPOL_KEY_DESC_V3           3         /* 11r */
+#define EAPOL_KEY_PAIRWISE          (1 <<  3)
+#define EAPOL_KEY_INSTALL           (1 <<  6) /* I */
+#define EAPOL_KEY_KEYACK            (1 <<  7) /* A */
+#define EAPOL_KEY_KEYMIC            (1 <<  8) /* M */
+#define EAPOL_KEY_SECURE            (1 <<  9) /* S */
+#define EAPOL_KEY_ERROR             (1 << 10)
+#define EAPOL_KEY_REQUEST           (1 << 11)
+#define EAPOL_KEY_ENCRYPTED         (1 << 12)
+#define EAPOL_KEY_SMK               (1 << 13)
+
+/* WPA compatibility */
+
+#define EAPOL_KEY_WPA_KID_MASK      0x3
+#define EAPOL_KEY_WPA_KID_SHIFT     4
+#define EAPOL_KEY_WPA_TX            EAPOL_KEY_INSTALL
+
+  uint8_t keylen[2];
+  uint8_t replaycnt[8];
+  uint8_t nonce[EAPOL_KEY_NONCE_LEN];
+  uint8_t iv[EAPOL_KEY_IV_LEN];
+  uint8_t rsc[8];
+  uint8_t reserved[8];
+  uint8_t mic[EAPOL_KEY_MIC_LEN];
+  uint8_t paylen[2];
+} end_packet_struct;
+
+/* Pairwise Transient Key (see 8.5.1.2) */
+
+struct ieee80211_ptk
+{
+  uint8_t kck[16];            /* Key Confirmation Key */
+  uint8_t kek[16];            /* Key Encryption Key */
+  uint8_t tk[32];             /* Temporal Key */
+} end_packet_struct;
+
+/* Key Data Encapsulation (see Table 62) */
+
+enum
+{
+  IEEE80211_KDE_GTK        = 1,
+  IEEE80211_KDE_MACADDR    = 3,
+  IEEE80211_KDE_PMKID      = 4,
+  IEEE80211_KDE_SMK        = 5,
+  IEEE80211_KDE_NONCE      = 6,
+  IEEE80211_KDE_LIFETIME   = 7,
+  IEEE80211_KDE_ERROR      = 8,
+  IEEE80211_KDE_IGTK       = 9  /* 11w */
+};
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+static inline int ieee80211_has_seq(FAR const struct ieee80211_frame *wh)
+{
+  return (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL;
+}
+
+static inline int ieee80211_has_addr4(FAR const struct ieee80211_frame *wh)
+{
+  return (wh->i_fc[1] & IEEE80211_FC1_DIR_MASK) == IEEE80211_FC1_DIR_DSTODS;
+}
+
+static inline int ieee80211_has_qos(FAR const struct ieee80211_frame *wh)
+{
+  return (wh->i_fc[0] &
+          (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_QOS)) ==
+          (IEEE80211_FC0_TYPE_DATA | IEEE80211_FC0_SUBTYPE_QOS);
+}
+
+static inline int ieee80211_has_htc(FAR const struct ieee80211_frame *wh)
+{
+  return (wh->i_fc[1] & IEEE80211_FC1_ORDER) &&
+          (ieee80211_has_qos(wh) ||
+         (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_MGT);
+}
+
+static inline uint16_t ieee80211_get_qos(FAR const struct ieee80211_frame *wh)
+{
+  FAR const uint8_t *frm;
+
+  if (ieee80211_has_addr4(wh))
+    {
+      frm = ((FAR const struct ieee80211_qosframe_addr4 *)wh)->i_qos;
+    }
+  else
+    {
+      frm = ((FAR const struct ieee80211_qosframe *)wh)->i_qos;
+    }
+
+  return letoh16(*(FAR const uint16_t *)frm);
+}
+
+#endif /* __INCLUDE_NUTTX_WIRELESS_IEEE80211_IEEE80211_H */

include/nuttx/wireless/ieee80211/ieee80211_cypto.h

@@ -0,0 +1,119 @@
+/****************************************************************************
+ * net/ieee80211/ieee80211_crypto.h
+ * 802.11 protocol crypto-related definitions.
+ *
+ * Copyright (c) 2007,2008 Damien Bergamini <damien.bergamini@free.fr>
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ ****************************************************************************/
+
+#ifndef __NET_IEEE80211_IEEE80211_CRYPTO_H
+#define __NET_IEEE80211_IEEE80211_CRYPTO_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define IEEE80211_KEYBUF_SIZE    16
+
+#define IEEE80211_TKIP_HDRLEN    8
+#define IEEE80211_TKIP_MICLEN    8
+#define IEEE80211_TKIP_ICVLEN    4
+#define IEEE80211_CCMP_HDRLEN    8
+#define IEEE80211_CCMP_MICLEN    8
+
+#define IEEE80211_PMK_LEN    32
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/* 802.11 ciphers */
+
+enum ieee80211_cipher
+{
+  IEEE80211_CIPHER_NONE      = 0x00000000,
+  IEEE80211_CIPHER_USEGROUP  = 0x00000001,
+  IEEE80211_CIPHER_WEP40     = 0x00000002,
+  IEEE80211_CIPHER_TKIP      = 0x00000004,
+  IEEE80211_CIPHER_CCMP      = 0x00000008,
+  IEEE80211_CIPHER_WEP104    = 0x00000010,
+  IEEE80211_CIPHER_BIP       = 0x00000020   /* 11w */
+};
+
+/* 802.11 Authentication and Key Management Protocols */
+
+enum ieee80211_akm
+{
+  IEEE80211_AKM_NONE         = 0x00000000,
+  IEEE80211_AKM_8021X        = 0x00000001,
+  IEEE80211_AKM_PSK          = 0x00000002,
+  IEEE80211_AKM_SHA256_8021X = 0x00000004,  /* 11w */
+  IEEE80211_AKM_SHA256_PSK   = 0x00000008   /* 11w */
+};
+
+struct ieee80211_key
+{
+  uint8_t k_id;                             /* Identifier (0-5) */
+  enum ieee80211_cipher k_cipher;
+  unsigned int k_flags;
+
+#define IEEE80211_KEY_GROUP    0x00000001   /* Group data key */
+#define IEEE80211_KEY_TX       0x00000002   /* Tx+Rx */
+#define IEEE80211_KEY_IGTK     0x00000004   /* Integrity group key */
+
+  unsigned int k_len;
+  uint64_t k_rsc[IEEE80211_NUM_TID];
+  uint64_t k_mgmt_rsc;
+  uint64_t k_tsc;
+  uint8_t k_key[32];
+  FAR void *k_priv;
+};
+
+/* Entry in the PMKSA cache */
+
+struct ieee80211_pmk
+{
+  sq_entry_t pmk_next;
+  enum ieee80211_akm pmk_akm;
+  uint32_t pmk_lifetime;
+
+#define IEEE80211_PMK_INFINITE  0
+
+  uint8_t pmk_pmkid[IEEE80211_PMKID_LEN];
+  uint8_t pmk_macaddr[IEEE80211_ADDR_LEN];
+  uint8_t pmk_key[IEEE80211_PMK_LEN];
+};
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+static __inline int ieee80211_is_8021x_akm(enum ieee80211_akm akm)
+{
+  return akm == IEEE80211_AKM_8021X || akm == IEEE80211_AKM_SHA256_8021X;
+}
+
+static __inline int ieee80211_is_sha256_akm(enum ieee80211_akm akm)
+{
+  return akm == IEEE80211_AKM_SHA256_8021X || akm == IEEE80211_AKM_SHA256_PSK;
+}
+
+#endif /* __NET_IEEE80211_IEEE80211_CRYPTO_H */