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arch:rv64:fix 64bit data type and insn for FPU handlers.

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Signed-off-by: hotislandn <hotislandn@hotmail.com>
This commit is contained in:
hotislandn 2021-03-19 09:53:26 +08:00 committed by Xiang Xiao
parent a1d0360e5e
commit e452b667ef
1 changed files with 7 additions and 7 deletions
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14
arch/risc-v/src/rv64gc/riscv_fpu.S
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@ -95,7 +95,7 @@ up_fpuconfig:
* floating point registers. * floating point registers.
* *
* C Function Prototype: * C Function Prototype:
* void riscv_savefpu(uint32_t *regs); * void riscv_savefpu(uint64_t *regs);
* *
* Input Parameters: * Input Parameters:
* regs - A pointer to the register save area in which to save the floating point * regs - A pointer to the register save area in which to save the floating point
@ -109,7 +109,7 @@ up_fpuconfig:
.type riscv_savefpu, function .type riscv_savefpu, function
riscv_savefpu: riscv_savefpu:
lw t0, REG_INT_CTX(a0) ld t0, REG_INT_CTX(a0)
li t1, FS_MASK li t1, FS_MASK
and t2, t0, t1 and t2, t0, t1
li t1, FS_DIRTY li t1, FS_DIRTY
@ -118,7 +118,7 @@ riscv_savefpu:
and t0, t0, t1 and t0, t0, t1
li t1, FS_CLEAN li t1, FS_CLEAN
or t0, t0, t1 or t0, t0, t1
sw t0, REG_INT_CTX(a0) sd t0, REG_INT_CTX(a0)
/* Store all floating point registers */ /* Store all floating point registers */
@ -156,7 +156,7 @@ riscv_savefpu:
FSTORE f31, REG_F31(a0) FSTORE f31, REG_F31(a0)
frcsr t0 frcsr t0
sw t0, REG_FCSR(a0) sd t0, REG_FCSR(a0)
1: 1:
ret ret
@ -169,7 +169,7 @@ riscv_savefpu:
* floating point registers. * floating point registers.
* *
* C Function Prototype: * C Function Prototype:
* void riscv_restorefpu(const uint32_t *regs); * void riscv_restorefpu(const uint64_t *regs);
* *
* Input Parameters: * Input Parameters:
* regs - A pointer to the register save area containing the floating point * regs - A pointer to the register save area containing the floating point
@ -184,7 +184,7 @@ riscv_savefpu:
.type riscv_restorefpu, function .type riscv_restorefpu, function
riscv_restorefpu: riscv_restorefpu:
lw t0, REG_INT_CTX(a0) ld t0, REG_INT_CTX(a0)
li t1, FS_MASK li t1, FS_MASK
and t2, t0, t1 and t2, t0, t1
li t1, FS_INITIAL li t1, FS_INITIAL
@ -227,7 +227,7 @@ riscv_restorefpu:
/* Store the floating point control and status register */ /* Store the floating point control and status register */
lw t0, REG_FCSR(a0) ld t0, REG_FCSR(a0)
fscsr t0 fscsr t0
1: 1: