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This commit brings in support for the GAP8 architecture. The GAP8 is a 1+8-core DSP-like RISC-V MCU. Also included is support for the Gapuino GAP8 evaluation board.

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Squashed commit of the following:

Author: Gregory Nutt <gnutt@nuttx.org>

    Completes review of configs/gapuino.
    arch/risc-v/include/gap8/chip.h:  Replace the moved chip.h header file with a dummy chip.h header file just to keep the system happy.
    Move include/gap8/chip.h to src/gap8/chip.h.  Internal details should not be exposed outside of arch/ and configs/.  Review all headers files in src/gap8
    Review of arch/risc-v/include.

Author: hhuysqt <hyq9606@126.com>

    corrected author and email
    Add app initialization, add signal support, cleanup irq context and configs
    fix some warnings
    gapuino initial port
    GAP8 initial port
This commit is contained in:
Gregory Nutt 2018-10-30 09:38:50 -06:00
parent de764af9aa
commit e4562fc538
40 changed files with 6615 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
Documentation/README.html
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@ -8,7 +8,7 @@
<tr align="center" bgcolor="#e4e4e4">
<td>
<h1><big><font color="#3c34ec"><i>NuttX README Files</i></font></big></h1>
<p>Last Updated: October 17, 2018</p>
<p>Last Updated: October 30, 2018</p>
</td>
</tr>
</table>
@ -116,6 +116,8 @@ nuttx/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/freedom-kl25z/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| |- freedom-kl26z/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/freedom-kl26z/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| |- gapuino/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/gapuino/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| |- hymini-stm32v/
| | |- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/hymini-stm32v/RIDE/README.txt" target="_blank">RIDE/README.txt</a>
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/hymini-stm32v/README.txt" target="_blank"><b><i>README.txt</i></b></a>

2
README.txt
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@ -1791,6 +1791,8 @@ nuttx/
| | `- README.txt
| |- freedom-kl26z/
| | `- README.txt
| |- gapuino/
| | `- README.txt
| |- hymini-stm32v/
| | `- README.txt
| |- imxrt1050-evk

11
arch/risc-v/Kconfig
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@ -16,6 +16,13 @@ config ARCH_CHIP_NR5
---help---
NEXT RISC-V NR5Mxx architectures (RISC-V RV32IM cores).
config ARCH_CHIP_GAP8
bool "GreenwavesTechnologies GAP8"
select ARCH_RV32IM
---help---
GreenwavesTechnologies GAP8 features a 1+8-core RI5CY DSP-like
processor, which originally comes from the ETH PULP platform.
endchoice
config ARCH_RV32I
@ -33,6 +40,7 @@ config ARCH_FAMILY
config ARCH_CHIP
string
default "nr5m100" if ARCH_CHIP_NR5
default "gap8" if ARCH_CHIP_GAP8
config NR5_MPU
bool "MPU support"
@ -50,5 +58,8 @@ endif
if ARCH_CHIP_NR5
source arch/risc-v/src/nr5m100/Kconfig
endif
if ARCH_CHIP_GAP8
source arch/risc-v/src/gap8/Kconfig
endif
endif

61
arch/risc-v/include/gap8/chip.h Normal file
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@ -0,0 +1,61 @@
/****************************************************************************
* arch/risc-v/include/gap8/chip.h
* Gapuino chip features
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: hhuysqt <1020988872@qq.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through nuttx/irq.h
*/
#ifndef __ARCH_RISCV_INCLUDE_GAP8_CHIP_H
#define __ARCH_RISCV_INCLUDE_GAP8_CHIP_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Variables
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#endif /* __ARCH_RISCV_INCLUDE_GAP8_CHIP_H */

443
arch/risc-v/include/gap8/irq.h Normal file
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@ -0,0 +1,443 @@
/************************************************************************************
* arch/risc-v/include/gap8/irq.h
* GAP8 event system
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: hhuysqt <1020988872@qq.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/************************************************************************************
* GAP8 features a FC controller and a 8-core cluster. IRQ from peripherals have
* unique ID, which are dispatched to the FC or cluster by the SOC event unit, and
* then by the FC event unit or cluster event unit, and finally to FC or cluster.
* Peripherals share the same IRQ entry.
************************************************************************************/
#ifndef __ARCH_RISC_V_INCLUDE_GAP8_IRQ_H
#define __ARCH_RISC_V_INCLUDE_GAP8_IRQ_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <arch/irq.h>
#include <stdint.h>
/************************************************************************************
* Pre-Processor Definitions
************************************************************************************/
/* Unique ID in SOC domain */
/* uDMA data events.
* Each peripheral has a uDMA_ID.
* Each peripheral also has RX and TX event ID, which happen to be 2*uDMA_ID and
* 2*uDMA_ID+1.
*/
#define GAP8_EVENT_UDMA_LVDS_RX 0
#define GAP8_EVENT_UDMA_LVDS_TX 1
#define GAP8_EVENT_UDMA_SPIM0_RX 2
#define GAP8_EVENT_UDMA_SPIM0_TX 3
#define GAP8_EVENT_UDMA_SPIM1_RX 4
#define GAP8_EVENT_UDMA_SPIM1_TX 5
#define GAP8_EVENT_UDMA_HYPERBUS_RX 6
#define GAP8_EVENT_UDMA_HYPERBUS_TX 7
#define GAP8_EVENT_UDMA_UART_RX 8
#define GAP8_EVENT_UDMA_UART_TX 9
#define GAP8_EVENT_UDMA_I2C0_RX 10
#define GAP8_EVENT_UDMA_I2C0_TX 11
#define GAP8_EVENT_UDMA_I2C1_RX 12
#define GAP8_EVENT_UDMA_I2C1_TX 13
#define GAP8_EVENT_UDMA_TCDM_RX 14
#define GAP8_EVENT_UDMA_TCDM_TX 15
#define GAP8_EVENT_UDMA_SAI_CH0 16
#define GAP8_EVENT_UDMA_SAI_CH1 17
#define GAP8_EVENT_UDMA_CPI_RX 18
#define GAP8_UDMA_MAX_EVENT 18
/* Other events of uDMA peripherals */
#define GAP8_EVENT_LVDS_GEN0 20
#define GAP8_EVENT_LVDS_GEN1 21
#define GAP8_EVENT_SPIM0_EOT 22
#define GAP8_EVENT_SPIM1_EOT 23
#define GAP8_EVENT_HYPERBUS_RESERVED 24
#define GAP8_EVENT_UART_RESERVED 25
#define GAP8_EVENT_I2C0_ERROR 26
#define GAP8_EVENT_I2C1_ERROR 27
#define GAP8_EVENT_I2S_RESERVED 28
#define GAP8_EVENT_CAM_RESERVED 29
/* PMU events */
#define GAP8_EVENT_PMU_CLUSTER_POWER_ON 31
#define GAP8_EVENT_PMU_CLUSTER_RESERVED0 32
#define GAP8_EVENT_PMU_CLUSTER_RESERVED1 33
#define GAP8_EVENT_PMU_CLUSTER_RESERVED2 34
#define GAP8_EVENT_PMU_CLUSTER_CLOCK_GATING 35
#define GAP8_EVENT_PMU_DLC_BRIDGE_PICL_OK 36
#define GAP8_EVENT_PMU_DLC_BRIDGE_SCU_OK 37
/* Other SOC domain peripheral events */
#define GAP8_EVENT_PWM0 38
#define GAP8_EVENT_PWM1 39
#define GAP8_EVENT_PWM2 40
#define GAP8_EVENT_PWM3 41
#define GAP8_EVENT_GPIO 42 /* GPIO group interrupt */
#define GAP8_EVENT_RTC_APB 43
#define GAP8_EVENT_RTC 44
#define GAP8_EVENT_RESERVED0 45
#define GAP8_EVENT_RESERVED1 46
#define GAP8_EVENT_RESERVED2 47
#define GAP8_EVENT_SOC_SW_0 48 /* GAP8 SOC SW Event0 */
#define GAP8_EVENT_SOC_SW_1 49 /* GAP8 SOC SW Event1 */
#define GAP8_EVENT_SOC_SW_2 50 /* GAP8 SOC SW Event2 */
#define GAP8_EVENT_SOC_SW_3 51 /* GAP8 SOC SW Event3 */
#define GAP8_EVENT_SOC_SW_4 52 /* GAP8 SOC SW Event4 */
#define GAP8_EVENT_SOC_SW_5 53 /* GAP8 SOC SW Event5 */
#define GAP8_EVENT_SOC_SW_6 54 /* GAP8 SOC SW Event6 */
#define GAP8_EVENT_SOC_SW_7 55 /* GAP8 SOC SW Event7 */
#define GAP8_EVENT_REF32K_CLK_RISE 56 /* Reference 32K Clock event */
/* FC domain IRQ ID */
#define GAP8_IRQ_FC_SW_0 0
#define GAP8_IRQ_FC_SW_1 1
#define GAP8_IRQ_FC_SW_2 2
#define GAP8_IRQ_FC_SW_3 3
#define GAP8_IRQ_FC_SW_4 4
#define GAP8_IRQ_FC_SW_5 5
#define GAP8_IRQ_FC_SW_6 6
#define GAP8_IRQ_FC_SW_7 7
#define GAP8_IRQ_FC_TIMER_LO 10
#define GAP8_IRQ_FC_TIMER_HI 11
#define GAP8_IRQ_FC_UDMA 27
#define GAP8_IRQ_FC_MPU 28
#define GAP8_IRQ_FC_UDMA_ERR 29
#define GAP8_IRQ_FC_HP_0 30
#define GAP8_IRQ_FC_HP_1 31
#define GAP8_IRQ_RESERVED 60
/* Cluster domain IRQ ID */
// TODO
/* RISCY core exception vectors */
#define GAP8_IRQ_RST 32
#define GAP8_IRQ_ILLEGAL 33
#define GAP8_IRQ_SYSCALL 34
/* Total number of IRQs.
* 32 ISRs + reset-handler + illegal-instruction-handler + system-call-handler
*/
#define NR_IRQS 35
/************************************************************************************
* Public Types
************************************************************************************/
/* SOC_EU - SOC domain event unit */
typedef struct
{
volatile uint32_t EVENT; /* event register */
volatile uint32_t FC_MASK_MSB; /* fc mask MSB register */
volatile uint32_t FC_MASK_LSB; /* fc mask LSB register */
volatile uint32_t CL_MASK_MSB; /* cluster mask MSB register */
volatile uint32_t CL_MASK_LSB; /* cluster mask LSB register */
volatile uint32_t PR_MASK_MSB; /* propagate mask MSB register */
volatile uint32_t PR_MASK_LSB; /* propagate mask LSB register */
volatile uint32_t ERR_MASK_MSB; /* error mask MSB register */
volatile uint32_t ERR_MASK_LSB; /* error mask LSB register */
volatile uint32_t TIMER_SEL_HI; /* timer high register */
volatile uint32_t TIMER_SEL_LO; /* timer low register */
} SOC_EU_reg_t;
#define SOC_EU ((SOC_EU_reg_t *)0x1A106000U)
/* FCEU - FC domain event unit */
typedef struct
{
volatile uint32_t MASK; /* mask register */
volatile uint32_t MASK_AND; /* mask-and(clr) register */
volatile uint32_t MASK_OR; /* mask-or(set) register */
volatile uint32_t MASK_IRQ; /* irq mask register */
volatile uint32_t MASK_IRQ_AND; /* irq mask-and(clr) register */
volatile uint32_t MASK_IRQ_OR; /* irq mask-or(set) register */
volatile uint32_t STATUS; /* clock Status register */
volatile uint32_t BUFFER; /* irq pending register */
volatile uint32_t BUFFER_MASKED; /* buffer masked register */
volatile uint32_t BUFFER_IRQ_MASKED; /* buffer irq masked register */
volatile uint32_t BUFFER_CLEAR; /* clear irq pending */
volatile uint32_t SW_EVENTS_MASK; /* software event mask register */
volatile uint32_t SW_EVENTS_MASK_AND; /* software event mask and register */
volatile uint32_t SW_EVENTS_MASK_OR; /* software event mask or register */
volatile uint32_t EVENT_WAIT; /* event wait register */
volatile uint32_t EVENT_WAIT_CLEAR; /* event wait clear register */
volatile uint32_t MASK_SEC_IRQ; /* mask sec irq register */
} FCEU_reg_t;
#define FCEU ((FCEU_reg_t*)0x00204000U)
/* Current interrupt event ID */
typedef struct
{
volatile uint32_t CURRENT_EVENT; /* current event register */
} SOC_EVENT_reg_t;
#define SOC_EVENTS ((SOC_EVENT_reg_t*)0x00200F00UL)
/* event trigger and mask */
typedef struct
{
volatile uint32_t TRIGGER_SET[8]; /* trigger set register */
volatile uint32_t _reserved0[8]; /* Offset: 0x20 (R/W) Empty Registers */
volatile uint32_t TRIGGER_WAIT[8]; /* trigger wait register */
volatile uint32_t _reserved1[8]; /* Offset: 0x60 (R/W) Empty Registers */
volatile uint32_t TRIGGER_CLR[8]; /* trigger clear register */
} EU_SW_EVENTS_TRIGGER_reg_t;
#define EU_SW_EVNT_TRIG ((EU_SW_EVENTS_TRIGGER_reg_t*)0x00204100UL)
/************************************************************************************
* Inline Functions
************************************************************************************/
/****************************************************************************
* Name: up_disable_event
*
* Description:
* Disable the specific event. Note that setting 1 means to disable an event...
*
****************************************************************************/
static inline void up_disable_event(int event)
{
if (event >= 32)
{
SOC_EU->FC_MASK_MSB |= (1 << (event-32));
}
else
{
SOC_EU->FC_MASK_LSB |= (1 << event);
}
}
/****************************************************************************
* Name: up_enable_event
*
* Description:
* Enable the specific event. Note that setting 0 means to enable an event...
*
****************************************************************************/
static inline void up_enable_event(int event)
{
if (event >= 32)
{
SOC_EU->FC_MASK_MSB &= ~(1 << (event-32));
}
else
{
SOC_EU->FC_MASK_LSB &= ~(1 << event);
}
}
/****************************************************************************
* Name: up_disable_irq
*
* Description:
* Disable the IRQ specified by 'irq'. Mind the Machine privilege.
*
****************************************************************************/
static inline void up_disable_irq(int irq)
{
FCEU->MASK_IRQ_AND = (1UL << irq);
}
/****************************************************************************
* Name: up_enable_irq
*
* Description:
* Enable the IRQ specified by 'irq'. Mind the Machine privilege.
*
****************************************************************************/
static inline void up_enable_irq(int irq)
{
FCEU->MASK_IRQ_OR = (1 << irq);
}
/****************************************************************************
* Name: up_ack_irq
*
* Description:
* Acknowledge the IRQ
*
****************************************************************************/
static inline void up_ack_irq(int irq)
{
}
/****************************************************************************
* Name: _current_privilege
*
* Description:
* Get the current privilege mode. 0x0 for user mode, and 0x3 for machine
* mode.
*
****************************************************************************/
static inline uint32_t _current_privilege(void)
{
uint32_t result;
asm volatile ("csrr %0, 0xC10" : "=r" (result));
return result;
}
/****************************************************************************
* Name: up_irq_save
*
* Description:
* Disable interrupt and return the current interrupt state.
*
****************************************************************************/
static inline uint32_t up_irq_save(void)
{
uint32_t oldstat, newstat;
if (_current_privilege())
{
/* Machine mode: Unset MIE and UIE */
asm volatile ("csrr %0, 0x300": "=r" (oldstat));
newstat = oldstat & ~(0x9);
asm volatile("csrw 0x300, %0" : /* no output */ : "r" (newstat));
}
else
{
/* User mode: Unset UIE */
asm volatile ("csrr %0, 0x000": "=r" (oldstat));
newstat = oldstat & ~(1L << 0);
asm volatile("csrw 0x000, %0" : /* no output */ : "r" (newstat));
}
return oldstat;
}
/****************************************************************************
* Name: up_irq_restore
*
* Description:
* Restore previous IRQ mask state
*
****************************************************************************/
static inline void up_irq_restore(uint32_t pri)
{
if (_current_privilege())
{
/* Machine mode - mstatus */
asm volatile("csrw 0x300, %0" : /* no output */ : "r" (pri));
}
else
{
/* User mode - ustatus */
asm volatile("csrw 0x000, %0" : /* no output */ : "r" (pri));
}
}
/****************************************************************************
* Name: up_irq_enable
*
* Description:
* Return the current interrupt state and enable interrupts
*
****************************************************************************/
static inline uint32_t up_irq_enable(void)
{
uint32_t oldstat, newstat;
if (_current_privilege())
{
/* Machine mode: Set MIE and UIE */
asm volatile ("csrr %0, 0x300": "=r" (oldstat));
newstat = oldstat | (0x9);
asm volatile("csrw 0x300, %0" : /* no output */ : "r" (newstat));
}
else
{
/* User mode: Set UIE */
asm volatile ("csrr %0, 0x000": "=r" (oldstat));
newstat = oldstat | (1L << 0);
asm volatile("csrw 0x000, %0" : /* no output */ : "r" (newstat));
}
return oldstat;
}
/****************************************************************************
* Name: gap8_sleep_wait_sw_evnt
*
* Description:
* Sleep on specific event.
*
****************************************************************************/
static inline void gap8_sleep_wait_sw_evnt(uint32_t event_mask)
{
FCEU->MASK_OR = event_mask;
__builtin_pulp_event_unit_read((void *)&FCEU->EVENT_WAIT_CLEAR, 0);
FCEU->MASK_AND = event_mask;
}
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
#endif /* __ARCH_RISC_V_INCLUDE_GAP8_IRQ_H */

1
arch/risc-v/include/irq.h
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@ -76,4 +76,3 @@ irqstate_t irqsave(void);
void irqrestore(irqstate_t);
#endif /* __ARCH_RISCV_INCLUDE_IRQ_H */

2
arch/risc-v/include/limits.h
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@ -69,7 +69,7 @@
/* These change on 32-bit and 64-bit platforms */
#if defined(CONFIG_ARCH_32IM) || defined(CONFIG_ARCH_32I)
#if defined(CONFIG_ARCH_RV32IM) || defined(CONFIG_ARCH_RV32I)
#define LONG_MIN (-LONG_MAX - 1)
#define LONG_MAX 2147483647L

13
arch/risc-v/include/rv32im/irq.h
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@ -52,6 +52,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
/* If this is a kernel build, how many nested system calls should we support? */
@ -61,6 +62,7 @@
#endif
/* Processor PC */
#define REG_EPC_NDX 0
/* General pupose registers */
@ -127,7 +129,14 @@
#define REG_INT_CTX_NDX 32
#define XCPTCONTEXT_REGS 33
#ifdef CONFIG_ARCH_CHIP_GAP8
/* 31 registers, ePC, plus 6 loop registers */
# define XCPTCONTEXT_REGS (32 + 6)
#else
# define XCPTCONTEXT_REGS 33
#endif
#define XCPTCONTEXT_SIZE (4 * XCPTCONTEXT_REGS)
/* In assembly language, values have to be referenced as byte address
@ -333,7 +342,7 @@ struct xcptcontext
uint32_t regs[XCPTCONTEXT_REGS];
};
#endif /* __ASSEMBLY__ */
#endif /* __ASSEMBLY__ */
/****************************************************************************
* Public Variables

4
arch/risc-v/src/common/up_initialize.c
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@ -45,6 +45,8 @@
#include <nuttx/board.h>
#include <nuttx/mm/iob.h>
#include <nuttx/serial/pty.h>
#include <nuttx/syslog/syslog.h>
#include <nuttx/drivers/drivers.h>
#include <arch/board/board.h>
@ -154,7 +156,7 @@ void up_initialize(void)
#if defined(CONFIG_DEV_LOWCONSOLE)
lowconsole_init();
#elif defined(CONFIG_SYSLOG_CONSOLE)
#elif defined(CONFIG_CONSOLE_SYSLOG)
syslog_console_init();
#elif defined(CONFIG_RAMLOG_CONSOLE)
ramlog_consoleinit();

1
arch/risc-v/src/common/up_internal.h
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@ -146,6 +146,7 @@ void riscv_timer_initialize(void);
/* Low level serial output **************************************************/
void up_serialinit(void);
void up_lowputc(char ch);
void up_puts(const char *str);
void up_lowputs(const char *str);

13
arch/risc-v/src/gap8/Kconfig Normal file
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@ -0,0 +1,13 @@
#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#
comment "GAP8 configuration"
config CORE_CLOCK_FREQ
int "Core clock frequency"
range 150000000 250000000
default 200000000
---help---
The core clock in Hz. GAP8 is able to run up to 250MHz.

67
arch/risc-v/src/gap8/Make.defs Normal file
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@ -0,0 +1,67 @@
############################################################################
# arch/risc-v/src/gapuino/Make.defs
#
# Copyright (C) 2018 Gregory Nutt. All rights reserved.
# Author: hhuysqt <1020988872@qq.com>
#
# # Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in
# the documentation and/or other materials provided with the
# distribution.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
############################################################################
# Specify our HEAD assembly file. This will be linked as the first object
# file, so it will appear at address 0
HEAD_ASRC = startup_gap8.S
# Specify our general Assembly files
CHIP_ASRCS = up_syscall.S
# Override the arch to enable hardware MUL during assembly.
# This is to support our hardware mul test. For that test,
# we have to disable hardware mul for C code so the soft
# math libs will be used to compare software mul vs hw mul.
# But hw mul must be enabled to compile the .S file, or we
# will get an illegal instruction error.
ASARCHCPUFLAGS += -march=rv32imcxgap8 -mPE=8 -mFC=1 -D__riscv__ -D__pulp__ -D__GAP8__
# Specify C code within the common directory to be included
CMN_CSRCS += up_initialize.c up_swint.c
CMN_CSRCS += up_createstack.c up_dumpstate.c up_exit.c
CMN_CSRCS += up_assert.c up_blocktask.c up_copystate.c up_initialstate.c
CMN_CSRCS += up_interruptcontext.c up_releasepending.c up_reprioritizertr.c
CMN_CSRCS += up_releasestack.c up_stackframe.c up_sigdeliver.c
CMN_CSRCS += up_unblocktask.c up_usestack.c
ifeq ($(CONFIG_ARCH_HAVE_VFORK),y)
CMN_CSRCS += up_vfork.c
endif
# Specify our C code within this directory to be included
CHIP_CSRCS = gap8_allocateheap.c gap8_fll.c gap8_gpio.c gap8_interrupt.c
CHIP_CSRCS += gap8_tim.c gap8_uart.c gap8_udma.c gap8_idle.c gap8_schedulesigaction.c

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/****************************************************************************
* arch/risc-v/src/common/up_allocateheap.c
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>
#include <arch/board/board.h>
#include "up_arch.h"
#include "up_internal.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_allocate_heap
*
* Description:
* This function will be called to dynamically set aside the heap region.
*
* For the kernel build (CONFIG_BUILD_KERNEL=y) with both kernel- and
* user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the
* size of the unprotected, user-space heap.
*
* If a protected kernel-space heap is provided, the kernel heap must be
* allocated (and protected) by an analogous up_allocate_kheap().
*
****************************************************************************/
void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
{
/* These values come from GAP8.ld */
extern uint8_t *_heap_start, *_heap_end;
uint32_t hstart = (uint32_t)&_heap_start;
uint32_t hend = (uint32_t)&_heap_end;
*heap_start = &_heap_start;
*heap_size = hend - hstart;
}
/************************************************************************************
* Name: up_addregion
*
* Description:
* RAM may be added in non-contiguous chunks. This routine adds all chunks
* that may be used for heap.
*
************************************************************************************/
void up_addregion(void)
{
// TODO: add L1 memories
}

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/************************************************************************************
* arch/risc-v/src/gap8/gap8_fll.c
* GAP8 FLL clock generator
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: hhuysqt <1020988872@qq.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/************************************************************************************
* FC can run up to 250MHz@1.2V, and 150MHz@1.0V. While the default voltage of PMU
* is 1.2V, it's okay to boost up without considering PMU.
************************************************************************************/
/************************************************************************************
* Included Files
************************************************************************************/
#include "gap8_fll.h"
/************************************************************************************
* Pre-Processor Declarations
************************************************************************************/
/* Log2(FLL_REF_CLK=32768) */
#define LOG2_REFCLK 15
/************************************************************************************
* Public Function
************************************************************************************/
/****************************************************************************
* Name: gap8_setfreq
*
* Description:
* Set frequency up to 250MHz. Input frequency counted by Hz.
*
****************************************************************************/
void gap8_setfreq(uint32_t frequency)
{
uint32_t mult;
uint32_t mult_factor_diff;
/* FreqOut = Fref * mult/2^(div-1)
* With 16-bit mult and 4-bit div
* div = 1
*/
mult = frequency >> LOG2_REFCLK;
/* Gain : 2-1 - 2-10 (0x2-0xB)
* Return to close loop mode and give gain to feedback loop
*/
FLL_CTRL->SOC_CONF2 = FLL_CTRL_CONF2_LOOPGAIN(0x7) |
FLL_CTRL_CONF2_DEASSERT_CYCLES(0x10) |
FLL_CTRL_CONF2_ASSERT_CYCLES(0x10) |
FLL_CTRL_CONF2_LOCK_TOLERANCE(0x100) |
FLL_CTRL_CONF2_CONF_CLK_SEL(0x0) |
FLL_CTRL_CONF2_OPEN_LOOP(0x0) |
FLL_CTRL_CONF2_DITHERING(0x1);
/* Configure mult and div */
FLL_CTRL->SOC_CONF1 = FLL_CTRL_CONF1_MODE(1) |
FLL_CTRL_CONF1_MULTI_FACTOR(mult) |
FLL_CTRL_CONF1_CLK_OUT_DIV(1);
/* Check FLL converge by compare status register with multiply factor */
do
{
mult_factor_diff = __builtin_pulp_abs(FLL_CTRL->SOC_FLL_STATUS - mult);
}
while (mult_factor_diff > 0x10);
FLL_CTRL->SOC_CONF2 = FLL_CTRL_CONF2_LOOPGAIN(0xB) |
FLL_CTRL_CONF2_DEASSERT_CYCLES(0x10) |
FLL_CTRL_CONF2_ASSERT_CYCLES(0x10) |
FLL_CTRL_CONF2_LOCK_TOLERANCE(0x100) |
FLL_CTRL_CONF2_CONF_CLK_SEL(0x0) |
FLL_CTRL_CONF2_OPEN_LOOP(0x0) |
FLL_CTRL_CONF2_DITHERING(0x1);
}
/****************************************************************************
* Name: gap8_getfreq
*
* Description:
* Get current system clock frequency in Hz.
*
****************************************************************************/
uint32_t gap8_getfreq(void)
{
/* FreqOut = Fref * mult/2^(div-1), where div = 1 */
return FLL_REF_CLK * (FLL_CTRL->SOC_FLL_STATUS & 0xFFFF);
}

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/************************************************************************************
* arch/risc-v/src/gap8/gap8_fll.h
* GAP8 FLL clock generator
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: hhuysqt <1020988872@qq.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/************************************************************************************
* FC can run up to 250MHz@1.2V, and 150MHz@1.0V. While the default voltage of PMU
* is 1.2V, it's okay to boost up without considering PMU.
************************************************************************************/
#ifndef __ARCH_RISC_V_SRC_GAP8_FLL_H
#define __ARCH_RISC_V_SRC_GAP8_FLL_H
/************************************************************************************
* Included Files
************************************************************************************/
#include "chip.h"
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
/****************************************************************************
* Name: gap8_setfreq
*
* Description:
* Set frequency up to 250MHz. Input frequency in Hz.
*
****************************************************************************/
void gap8_setfreq(uint32_t frequency);
/****************************************************************************
* Name: gap8_getfreq
*
* Description:
* Get current system clock frequency in Hz.
*
****************************************************************************/
uint32_t gap8_getfreq(void);
#endif /* __ARCH_RISC_V_SRC_GAP8_FLL_H */

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/************************************************************************************
* arch/risc-v/src/gap8/gap8_gpio.c
* GAP8 FLL clock generator
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: hhuysqt <1020988872@qq.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/************************************************************************************
* GAP8 has only 1 port. Each pin could be configured to GPIO or alternative
* functions.
************************************************************************************/
#include "gap8_gpio.h"
/************************************************************************************
* Name: gap8_configpin
*
* Description:
* Configure a pin based on bit-encoded description of the pin.
*
* GPIO software abstraction: bitmap configuration of pins
*
* |31 18| 17 | 16 | 15 |14 10|9 8|7 0|
* | --- | drive | pull-up/OD | I/O | GPIOn | alt | pinnum |
* | --- | 1-bit | 1-bit | 1-b | 5-bit | 2-bit | 8-bit |
*
* Returned Value:
* OK on success
* ERROR on invalid pin.
*
************************************************************************************/
int gap8_configpin(uint32_t cfgset)
{
uint32_t pinnum = cfgset & 0xff;
uint32_t altfunc = (cfgset >> 8) & 0x3;
uint32_t pin_dr_pu = (cfgset >> 16) & 0x3;
uint32_t port_cfg_reg;
uint32_t pin_alt_reg;
int shiftcnt;
if (pinnum > MAX_PIN_NUM)
{
return ERROR;
}
/* Set pin drive strength (or pin speed in other words) and pulling
* If it's a GPIO, set input or output.
*
* Note that GPIO and non-GPIO uses different register sets...
* And all the GPIO functions are mapped to ALT-1, and ALT-1 contains
* only GPIO functions...
*/
port_cfg_reg = PORTA->PADCFG[pinnum >> 2];
shiftcnt = (pinnum & 0x3) << 3;
port_cfg_reg &= ~(0x3 << shiftcnt);
port_cfg_reg |= pin_dr_pu << shiftcnt;
PORTA->PADCFG[pinnum >> 2] = port_cfg_reg;
if (altfunc == 1)
{
uint32_t gpio_n = (cfgset >> 10) & 0x1f;
uint32_t gpio_dir = (cfgset >> 15) & 0x1;
uint32_t tmp;
/* It must be a GPIO */
GPIOA->EN |= (1L << gpio_n);
tmp = GPIOA->PADCFG[gpio_n >> 2];
shiftcnt = (gpio_n & 0x3) << 3;
tmp &= ~(0x3 << shiftcnt);
tmp |= pin_dr_pu << shiftcnt;
GPIOA->PADCFG[gpio_n >> 2] = tmp;
tmp = GPIOA->DIR;
tmp &= ~(1L << gpio_n);
tmp |= gpio_dir << gpio_n;
GPIOA->DIR = tmp;
}
/* Set pin alternative function */
pin_alt_reg = PORTA->PADFUN[pinnum >> 4];
shiftcnt = (pinnum & 0xf) << 1;
pin_alt_reg &= ~(0x3 << shiftcnt);
pin_alt_reg |= altfunc << shiftcnt;
PORTA->PADFUN[pinnum >> 4] = pin_alt_reg;
return OK;
}
/************************************************************************************
* Name: gap8_gpiowrite
*
* Description:
* Write one or zero to the selected GPIO pin
*
* Bit encoded pinset:
*
* |31 15|14 10|9 0|
* | --- | GPIOn | --- |
* | --- | 5-bit | --- |
*
************************************************************************************/
void gap8_gpiowrite(uint32_t pinset, bool value)
{
uint32_t gpio_n = (pinset >> 10) & 0x1f;
if (value)
{
GPIOA->OUT |= (1L << gpio_n);
}
else
{
GPIOA->OUT &= ~(1L << gpio_n);
}
}
/************************************************************************************
* Name: gap8_gpioread
*
* Description:
* Read one or zero from the selected GPIO pin
*
* Bit encoded pinset:
*
* |31 15|14 10|9 0|
* | --- | GPIOn | --- |
* | --- | 5-bit | --- |
*
************************************************************************************/
bool gap8_gpioread(uint32_t pinset)
{
uint32_t gpio_n = (pinset >> 10) & 0x1f;
return (GPIOA->IN >> gpio_n) & 0x1;
}
/************************************************************************************
* Name: gap8_gpioirqset
*
* Description:
* Enable or disable interrupt on GPIO
*
* Bit encoded pinset:
*
* |31 20|19 18|17 15|14 10|9 0|
* | --- | int-typ | --- | GPIOn | --- |
* | --- | 2-bit | --- | 5-bit | --- |
*
************************************************************************************/
void gap8_gpioirqset(uint32_t pinset, bool enable)
{
uint32_t gpio_n = (pinset >> 10) & 0x1f;
uint32_t int_type = (pinset >> 18) * 0x3;
uint32_t tmp, shitfcnt;
if (enable)
{
shitfcnt = (gpio_n & 0xf) << 1;
tmp = GPIOA->INTCFG[gpio_n >> 4];
tmp &= ~(0x3 << shitfcnt);
tmp |= int_type << shitfcnt;
GPIOA->INTCFG[gpio_n >> 4] = tmp;
GPIOA->INTEN |= (1L << gpio_n);
}
}

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/************************************************************************************
* arch/risc-v/src/gap8/gap8_gpio.h
* PIN driver for GAP8
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: hhuysqt <1020988872@qq.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/************************************************************************************
* GAP8 has only 1 port. Each pin could be configured to GPIO or alternative
* functions.
************************************************************************************/
#ifndef _ARCH_RISCV_SRC_GAP8_GPIO_H
#define _ARCH_RISCV_SRC_GAP8_GPIO_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include "chip.h"
/************************************************************************************
* Pre-Processor Definitions
************************************************************************************/
#define MAX_PIN_NUM 47
/* GPIO software abstraction: bitmap configuration of pins
*
* |31 20|19 18| 17 | 16 | 15 |14 10|9 8|7 0|
* | --- | int-typ | drive | pull-up/OD | I/O | GPIOn | alt | pinnum |
* | --- | 2-bit | 1-bit | 1-bit | 1-b | 5-bit | 2-bit | 8-bit |
*/
#define GAP8_GPIO_INT_FALLING (0L << 18)
#define GAP8_GPIO_INT_RISING (1L << 18)
#define GAP8_GPIO_INT_RISING_AND_FALLING (2L << 18)
#define GAP8_PIN_SPEED_HIGH (1L << 17)
#define GAP8_PIN_SPEED_LOW (0L << 17)
#define GAP8_PIN_PULL_UP (1L << 16)
#define GAP8_PIN_PULL_NONE (0L << 16)
#define GAP8_GPIO_INPUT (0L << 15)
#define GAP8_GPIO_OUTPUT (1L << 15)
#define GAP8_PIN_A4_SPIM1_MISO ((0L << 8) | 0)
#define GAP8_PIN_A4_GPIOA0 ((1L << 8) | (0L << 10) | 0)
#define GAP8_PIN_B3_SPIM1_MOSI ((0L << 8) | 1)
#define GAP8_PIN_B3_GPIOA1 ((1L << 8) | (1L << 10) | 1)
#define GAP8_PIN_A5_SPIM1_CS0 ((0L << 8) | 2)
#define GAP8_PIN_A5_GPIOA2 ((1L << 8) | (2L << 10) | 2)
#define GAP8_PIN_A5_I2C1_SDA ((2L << 8) | 2)
#define GAP8_PIN_B4_SPIM1_SCK ((0L << 8) | 3)
#define GAP8_PIN_B4_GPIOA3 ((1L << 8) | (3L << 10) | 3)
#define GAP8_PIN_B4_I2C1_SCL ((2L << 8) | 3)
#define GAP8_PIN_A3_ORCA_TXSYNC ((0L << 8) | 4)
#define GAP8_PIN_A3_GPIOA0 ((1L << 8) | (0L << 10) | 4)
#define GAP8_PIN_A3_SPIM1_CS0 ((2L << 8) | 4)
#define GAP8_PIN_B2_ORCA_RXSYNC ((0L << 8) | 5)
#define GAP8_PIN_B2_GPIOA1 ((1L << 8) | (1L << 10) | 5)
#define GAP8_PIN_B2_SPIM1_CS1 ((2L << 8) | 5)
#define GAP8_PIN_A2_ORCA_TX1 ((0L << 8) | 6)
#define GAP8_PIN_A2_GPIOA2 ((1L << 8) | (2L << 10) | 6)
#define GAP8_PIN_B1_ORCA_TXQ ((0L << 8) | 7)
#define GAP8_PIN_B1_GPIOA3 ((1L << 8) | (3L << 10) | 7)
#define GAP8_PIN_A44_ORCA_RXI ((0L << 8) | 8)
#define GAP8_PIN_A44_GPIOA4 ((1L << 8) | (4L << 10) | 8)
#define GAP8_PIN_A44_SPIS0_D0 ((2L << 8) | 8)
#define GAP8_PIN_A44_SPIS0_D2 ((3L << 8) | 8)
#define GAP8_PIN_B40_ORCA_RXQ ((0L << 8) | 9)
#define GAP8_PIN_B40_GPIOA5 ((1L << 8) | (5L << 10) | 9)
#define GAP8_PIN_B40_SPIS0_D1 ((2L << 8) | 9)
#define GAP8_PIN_B40_SPIS0_D3 ((3L << 8) | 9)
#define GAP8_PIN_A43_CAM_PCLK ((0L << 8) | 10)
#define GAP8_PIN_A43_GPIOA4 ((1L << 8) | (4L << 10) | 10)
#define GAP8_PIN_A43_TIM1_CH0 ((2L << 8) | 10)
#define GAP8_PIN_A37_CAM_HSYNC ((0L << 8) | 11)
#define GAP8_PIN_A37_GPIOA5 ((1L << 8) | (5L << 10) | 11)
#define GAP8_PIN_A37_TIM1_CH1 ((2L << 8) | 11)
#define GAP8_PIN_B39_CAM_D0 ((0L << 8) | 12)
#define GAP8_PIN_B39_GPIOA6 ((1L << 8) | (6L << 10) | 12)
#define GAP8_PIN_B39_TIM1_CH2 ((2L << 8) | 12)
#define GAP8_PIN_A42_CAM_D1 ((0L << 8) | 13)
#define GAP8_PIN_A42_GPIOA7 ((1L << 8) | (7L << 10) | 13)
#define GAP8_PIN_A42_TIM1_CH3 ((2L << 8) | 13)
#define GAP8_PIN_B38_CAM_D2 ((0L << 8) | 14)
#define GAP8_PIN_B38_GPIOA8 ((1L << 8) | (8L << 10) | 14)
#define GAP8_PIN_B38_TIM2_CH0 ((2L << 8) | 14)
#define GAP8_PIN_A41_CAM_D3 ((0L << 8) | 15)
#define GAP8_PIN_A41_GPIOA9 ((1L << 8) | (9L << 10) | 15)
#define GAP8_PIN_A41_TIM2_CH1 ((2L << 8) | 15)
#define GAP8_PIN_B37_CAM_D4 ((0L << 8) | 16)
#define GAP8_PIN_B37_GPIOA10 ((1L << 8) | (10L << 10) | 16)
#define GAP8_PIN_B37_TIM2_CH2 ((2L << 8) | 16)
#define GAP8_PIN_A40_CAM_D5 ((0L << 8) | 17)
#define GAP8_PIN_A40_GPIOA11 ((1L << 8) | (11L << 10) | 17)
#define GAP8_PIN_A40_TIM2_CH3 ((2L << 8) | 17)
#define GAP8_PIN_B36_CAM_D6 ((0L << 8) | 18)
#define GAP8_PIN_B36_GPIOA12 ((1L << 8) | (12L << 10) | 18)
#define GAP8_PIN_B36_TIM3_CH0 ((2L << 8) | 18)
#define GAP8_PIN_A38_CAM_D7 ((0L << 8) | 19)
#define GAP8_PIN_A38_GPIOA13 ((1L << 8) | (13L << 10) | 19)
#define GAP8_PIN_A38_TIM3_CH1 ((2L << 8) | 19)
#define GAP8_PIN_A36_CAM_VSYNC ((0L << 8) | 20)
#define GAP8_PIN_A36_GPIOA14 ((1L << 8) | (14L << 10) | 20)
#define GAP8_PIN_A36_TIM3_CH2 ((2L << 8) | 20)
#define GAP8_PIN_B34_I2C1_SDA ((0L << 8) | 21)
#define GAP8_PIN_B34_GPIOA15 ((1L << 8) | (15L << 10) | 21)
#define GAP8_PIN_B34_TIM3_CH3 ((2L << 8) | 21)
#define GAP8_PIN_D1_I2C1_SCL ((0L << 8) | 22)
#define GAP8_PIN_D1_GPIOA16 ((1L << 8) | (16L << 10) | 22)
#define GAP8_PIN_D1_ORCA_CLK ((2L << 8) | 22)
#define GAP8_PIN_B11_TIM0_CH0 ((0L << 8) | 23)
#define GAP8_PIN_B11_GPIOA17 ((1L << 8) | (17L << 10) | 23)
#define GAP8_PIN_A13_TIM0_CH1 ((0L << 8) | 24)
#define GAP8_PIN_A13_GPIOA18 ((1L << 8) | (18L << 10) | 24)
#define GAP8_PIN_A13_TIM1_CH0 ((2L << 8) | 24)
#define GAP8_PIN_B12_TIM0_CH2 ((0L << 8) | 25)
#define GAP8_PIN_B12_GPIOA19 ((1L << 8) | (19L << 10) | 25)
#define GAP8_PIN_B12_TIM2_CH0 ((2L << 8) | 25)
#define GAP8_PIN_A14_TIM0_CH3 ((0L << 8) | 26)
#define GAP8_PIN_A14_GPIOA20 ((1L << 8) | (20L << 10) | 26)
#define GAP8_PIN_A14_TIM3_CH0 ((2L << 8) | 26)
#define GAP8_PIN_B13_I2S1_SCK ((0L << 8) | 27)
#define GAP8_PIN_B13_GPIOA21 ((1L << 8) | (21L << 10) | 27)
#define GAP8_PIN_B13_SPIS0_SCK ((2L << 8) | 27)
#define GAP8_PIN_B13_I2S1_SDI ((3L << 8) | 27)
#define GAP8_PIN_A15_I2S1_WS ((0L << 8) | 28)
#define GAP8_PIN_A15_GPIOA22 ((1L << 8) | (22L << 10) | 28)
#define GAP8_PIN_A15_SPIS0_CS ((2L << 8) | 28)
#define GAP8_PIN_A15_HYPER_CKN ((3L << 8) | 28)
#define GAP8_PIN_B14_I2S1_SDI ((0L << 8) | 29)
#define GAP8_PIN_B14_GPIOA23 ((1L << 8) | (23L << 10) | 29)
#define GAP8_PIN_B14_SPIS0_D2 ((2L << 8) | 29)
#define GAP8_PIN_B14_HYPER_CK ((3L << 8) | 29)
#define GAP8_PIN_B6_UART_RX ((0L << 8) | 30)
#define GAP8_PIN_B6_GPIOA24 ((1L << 8) | (24L << 10) | 30)
#define GAP8_PIN_A7_UART_TX ((0L << 8) | 31)
#define GAP8_PIN_A7_GPIOA25 ((1L << 8) | (25L << 10) | 31)
#define GAP8_PIN_D2_SPIM0_D0 ((0L << 8) | 32)
#define GAP8_PIN_D2_HYPER_D0 ((3L << 8) | 32)
#define GAP8_PIN_A11_SPIM0_D1 ((0L << 8) | 33)
#define GAP8_PIN_A11_HYPER_D1 ((3L << 8) | 33)
#define GAP8_PIN_B10_SPIM0_D2 ((0L << 8) | 34)
#define GAP8_PIN_B10_GPIOA26 ((1L << 8) | (26L << 10) | 34)
#define GAP8_PIN_B10_I2C1_SDA ((2L << 8) | 34)
#define GAP8_PIN_B10_HYPER_D2 ((3L << 8) | 34)
#define GAP8_PIN_A10_SPIM0_D3 ((0L << 8) | 35)
#define GAP8_PIN_A10_GPIOA27 ((1L << 8) | (27L << 10) | 35)
#define GAP8_PIN_A10_I2C1_SCL ((2L << 8) | 35)
#define GAP8_PIN_A10_HYPER_D3 ((3L << 8) | 35)
#define GAP8_PIN_B8_SPIM0_CS0 ((0L << 8) | 36)
#define GAP8_PIN_B8_HYPER_D4 ((3L << 8) | 36)
#define GAP8_PIN_A8_SPIM0_CS1 ((0L << 8) | 37)
#define GAP8_PIN_A8_GPIOA28 ((1L << 8) | (28L << 10) | 37)
#define GAP8_PIN_A8_SPIS0_D3 ((2L << 8) | 37)
#define GAP8_PIN_A8_HYPER_D5 ((3L << 8) | 37)
#define GAP8_PIN_B7_SPIM0_SCK ((0L << 8) | 38)
#define GAP8_PIN_B7_HYPER_D6 ((3L << 8) | 38)
#define GAP8_PIN_A9_SPIS0_CS ((0L << 8) | 39)
#define GAP8_PIN_A9_GPIOA29 ((1L << 8) | (29L << 10) | 39)
#define GAP8_PIN_A9_SPIM1_CS0 ((2L << 8) | 39)
#define GAP8_PIN_A9_HYPER_D7 ((3L << 8) | 39)
#define GAP8_PIN_B15_SPIS0_D0 ((0L << 8) | 40)
#define GAP8_PIN_B15_GPIOA30 ((1L << 8) | (30L << 10) | 40)
#define GAP8_PIN_B15_SPIM1_CS1 ((2L << 8) | 40)
#define GAP8_PIN_B15_HYPER_CS0 ((3L << 8) | 40)
#define GAP8_PIN_A16_SPIS0_D1 ((0L << 8) | 41)
#define GAP8_PIN_A16_GPIOA31 ((1L << 8) | (31L << 10) | 41)
#define GAP8_PIN_A16_HYPER_CS1 ((3L << 8) | 41)
#define GAP8_PIN_B9_SPIS0_SCK ((0L << 8) | 42)
#define GAP8_PIN_B9_HYPER_RWDS ((3L << 8) | 42)
#define GAP8_PIN_B22_I2C0_SDA ((0L << 8) | 43)
#define GAP8_PIN_A25_I2C0_SCL ((0L << 8) | 44)
#define GAP8_PIN_A24_I2S0_SCK ((0L << 8) | 45)
#define GAP8_PIN_A26_I2S0_WS ((0L << 8) | 46)
#define GAP8_PIN_B23_I2S0_SDI ((0L << 8) | 47)
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
/************************************************************************************
* Name: gap8_configpin
*
* Description:
* Configure a pin based on bit-encoded description of the pin.
*
* Returned Value:
* OK on success
* ERROR on invalid port, or when pin is locked as ALT function.
*
************************************************************************************/
int gap8_configpin(uint32_t cfgset);
/************************************************************************************
* Name: gap8_gpiowrite
*
* Description:
* Write one or zero to the selected GPIO pin
*
************************************************************************************/
void gap8_gpiowrite(uint32_t pinset, bool value);
/************************************************************************************
* Name: gap8_gpioread
*
* Description:
* Read one or zero from the selected GPIO pin
*
************************************************************************************/
bool gap8_gpioread(uint32_t pinset);
/************************************************************************************
* Name: gap8_gpioirqset
*
* Description:
* Enable or disable interrupt on GPIO
*
************************************************************************************/
void gap8_gpioirqset(uint32_t pinset, bool enable);
#endif /* _ARCH_RISCV_SRC_GAP8_GPIO_H */

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/****************************************************************************
* arch/risc-v/src/common/up_idle.c
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include "up_internal.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_idle
*
* Description:
* up_idle() is the logic that will be executed when their is no other
* ready-to-run task. This is processor idle time and will continue until
* some interrupt occurs to cause a context switch from the idle task.
*
* Processing in this state may be processor-specific. e.g., this is where
* power management operations might be performed.
*
****************************************************************************/
void up_idle(void)
{
#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
/* If the system is idle and there are no timer interrupts, then process
* "fake" timer interrupts. Hopefully, something will wake up.
*/
sched_process_timer();
#else
/* GAP8 would sleep on software event #3, which would be triggered at
* gap8_dispatch_irq().
*/
gap8_sleep_wait_sw_evnt(1 << 3);
#ifdef CONFIG_SCHED_WORKQUEUE
irqstate_t flags = enter_critical_section();
leave_critical_section(flags);
#endif
#endif
}

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/************************************************************************************
* arch/risc-v/src/gap8/gap8_interrupt.c
* GAP8 event system
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: hhuysqt <1020988872@qq.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/************************************************************************************
* GAP8 features a FC controller and a 8-core cluster. IRQ from peripherals have
* unique ID, which are dispatched to the FC or cluster by the SOC event unit, and
* then by the FC event unit or cluster event unit, and finally to FC or cluster.
* Peripherals share the same IRQ entry.
************************************************************************************/
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <arch/chip/irq.h>
#include "gap8_udma.h"
#include "gap8_tim.h"
/****************************************************************************
* Public Data
****************************************************************************/
volatile uint32_t *g_current_regs;
/************************************************************************************
* Public Function
************************************************************************************/
/* Function exported to the Nuttx kernel */
void up_mdelay(unsigned int time)
{
while (time--)
{
volatile int dummy = 200000;
while (dummy--)
{
}
}
}
/****************************************************************************
* Name: up_get_newintctx
*
* Description:
* Return a value for EPIC. But GAP8 doesn't use EPIC for event control.
*
****************************************************************************/
uint32_t up_get_newintctx(void)
{
return 0;
}
/****************************************************************************
* Name: up_irqinitialize
*
* Description:
* Initialize the IRQ on FC.
*
****************************************************************************/
void up_irqinitialize(void)
{
/* Deactivate all the soc events */
SOC_EU->FC_MASK_MSB = 0xFFFFFFFF;
SOC_EU->FC_MASK_LSB = 0xFFFFFFFF;
/* enable soc peripheral interrupt */
irq_attach(GAP8_IRQ_FC_UDMA, gap8_udma_doirq, NULL);
up_enable_irq(GAP8_IRQ_FC_UDMA);
/* Attach system call handler */
extern int up_swint(int irq, FAR void *context, FAR void *arg);
irq_attach(GAP8_IRQ_SYSCALL, up_swint, NULL);
up_irq_enable();
}
/****************************************************************************
* Name: gap8_dispatch_irq
*
* Description:
* Called from IRQ vectors. Input vector id. Return SP pointer, modified
* or not.
*
****************************************************************************/
void *gap8_dispatch_irq(uint32_t vector, void *current_regs)
{
/* Clear pending bit and trigger a software event.
* GAP8 would sleep on sw event 3 on up_idle().
*/
FCEU->BUFFER_CLEAR = (1 << vector);
EU_SW_EVNT_TRIG->TRIGGER_SET[3] = 0;
/* Call nuttx kernel, which may change curr_regs, to perform
* a context switch
*/
g_current_regs = current_regs;
irq_dispatch(vector, current_regs);
current_regs = (void *)g_current_regs;
g_current_regs = NULL;
return current_regs;
}

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/****************************************************************************
* arch/risc-v/src/gapuino/gap8_schedulesigaction.c
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Modified for RISC-V:
*
* Author: hhuysqt <1020988872@qq.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <sched.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <arch/nr5m100/irq.h>
#include "sched/sched.h"
#include "up_internal.h"
#include "up_arch.h"
#ifndef CONFIG_DISABLE_SIGNALS
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_schedule_sigaction
*
* Description:
* This function is called by the OS when one or more
* signal handling actions have been queued for execution.
* The architecture specific code must configure things so
* that the 'sigdeliver' callback is executed on the thread
* specified by 'tcb' as soon as possible.
*
* This function may be called from interrupt handling logic.
*
* This operation should not cause the task to be unblocked
* nor should it cause any immediate execution of sigdeliver.
* Typically, a few cases need to be considered:
*
* (1) This function may be called from an interrupt handler
* During interrupt processing, all xcptcontext structures
* should be valid for all tasks. That structure should
* be modified to invoke sigdeliver() either on return
* from (this) interrupt or on some subsequent context
* switch to the recipient task.
* (2) If not in an interrupt handler and the tcb is NOT
* the currently executing task, then again just modify
* the saved xcptcontext structure for the recipient
* task so it will invoke sigdeliver when that task is
* later resumed.
* (3) If not in an interrupt handler and the tcb IS the
* currently executing task -- just call the signal
* handler now.
*
****************************************************************************/
void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
{
irqstate_t flags;
uint32_t int_ctx;
sinfo("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
/* Make sure that interrupts are disabled */
flags = enter_critical_section();
/* Refuse to handle nested signal actions */
if (!tcb->xcp.sigdeliver)
{
/* First, handle some special cases when the signal is
* being delivered to the currently executing task.
*/
sinfo("rtcb=0x%p g_current_regs=0x%p\n",
this_task(), g_current_regs);
if (tcb == this_task())
{
/* CASE 1: We are not in an interrupt handler and
* a task is signaling itself for some reason.
*/
if (!g_current_regs)
{
/* In this case just deliver the signal now. */
sigdeliver(tcb);
}
/* CASE 2: We are in an interrupt handler AND the
* interrupted task is the same as the one that
* must receive the signal, then we will have to modify
* the return state as well as the state in the TCB.
*
* Hmmm... there looks like a latent bug here: The following
* logic would fail in the strange case where we are in an
* interrupt handler, the thread is signaling itself, but
* a context switch to another task has occurred so that
* g_current_regs does not refer to the thread of this_task()!
*/
else
{
/* Save the return EPC and STATUS registers. These will be
* restored by the signal trampoline after the signals have
* been delivered.
*/
tcb->xcp.sigdeliver = sigdeliver;
tcb->xcp.saved_epc = g_current_regs[REG_EPC];
/* Then set up to vector to the trampoline with interrupts
* disabled
*/
g_current_regs[REG_EPC] = (uint32_t)up_sigdeliver;
/* And make sure that the saved context in the TCB
* is the same as the interrupt return context.
*/
up_savestate(tcb->xcp.regs);
sinfo("PC/STATUS Saved: %08x/%08x New: %08x/%08x\n",
tcb->xcp.saved_epc, tcb->xcp.saved_status,
g_current_regs[REG_EPC], g_current_regs[REG_STATUS]);
}
}
/* Otherwise, we are (1) signaling a task is not running
* from an interrupt handler or (2) we are not in an
* interrupt handler and the running task is signaling
* some non-running task.
*/
else
{
/* Save the return EPC and STATUS registers. These will be
* restored by the signal trampoline after the signals have
* been delivered.
*/
tcb->xcp.sigdeliver = sigdeliver;
tcb->xcp.saved_epc = tcb->xcp.regs[REG_EPC];
/* Then set up to vector to the trampoline with interrupts
* disabled
*/
tcb->xcp.regs[REG_EPC] = (uint32_t)up_sigdeliver;
sinfo("PC/STATUS Saved: %08x/%08x New: %08x/%08x\n",
tcb->xcp.saved_epc, tcb->xcp.saved_status,
tcb->xcp.regs[REG_EPC], tcb->xcp.regs[REG_STATUS]);
}
}
leave_critical_section(flags);
}
#endif /* !CONFIG_DISABLE_SIGNALS */

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/****************************************************************************
* arch/risc-v/src/gapuino/gap8_tim.c
* GAP8 basic timer
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: hhuysqt <1020988872@qq.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/************************************************************************************
* FC core has a 64-bit basic timer, able to split into 2 32-bit timers, with
* identicle memory map and 2 IRQ channels, for both FC core and cluster. We would
* use it as system timer.
************************************************************************************/
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <nuttx/arch.h>
#include <arch/chip/irq.h>
#include "gap8_tim.h"
/****************************************************************************
* Private Types
****************************************************************************/
struct gap8_tim_instance
{
BASIC_TIM_reg_t *reg;
uint32_t core_clock;
}
/****************************************************************************
* Private Data
****************************************************************************/
static struct gap8_tim_instance fc_basic_timer =
{
.reg = BASIC_TIM,
.core_clock = 200000000,
};
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: gap8_timisr
*
* Description:
* Timer ISR to perform RR context switch
*
****************************************************************************/
static int gap8_timisr(int irq, void *context, FAR void *arg)
{
sched_process_timer();
return 0;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: riscv_timer_initialize
*
* Description:
* Initialize the timer based on the frequency of source clock and ticks
* per second.
*
****************************************************************************/
void riscv_timer_initialize(void)
{
/* Set input clock to 1MHz. FC won't exceed 250MHz */
uint32_t prescaler = (fc_basic_timer.core_clock / 1000000) & 0xff;
uint32_t cmpval = CONFIG_USEC_PER_TICK;
/* Initialize timer registers */
fc_basic_timer.reg->CMP_LO = cmpval;
fc_basic_timer.reg->CFG_REG_LO = (prescaler << 8) |
BASIC_TIM_CLKSRC_FLL | BASIC_TIM_PRESC_ENABLE | BASIC_TIM_MODE_CYCL |
BASIC_TIM_IRQ_ENABLE | BASIC_TIM_RESET | BASIC_TIM_ENABLE;
fc_basic_timer.reg->VALUE_LO = 0;
irq_attach(GAP8_IRQ_FC_TIMER_LO, gap8_timisr, NULL);
up_enable_irq(GAP8_IRQ_FC_TIMER_LO);
}

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/************************************************************************************
* arch/risc-v/src/gap8/gap8_tim.h
* PIN driver for GAP8
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: hhuysqt <1020988872@qq.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/************************************************************************************
* GAP8 features a 64-bit basic timer, able to split into 2 32-bit timers, with
* identicle memory map and 2 IRQ channels, for both FC core and cluster. We would
* use it as system timer.
************************************************************************************/
#ifndef __ARCH_RISC_V_SRC_GAP8_TIM_H
#define __ARCH_RISC_V_SRC_GAP8_TIM_H
/************************************************************************************
* Included Files
************************************************************************************/
#include "chip.h"
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
/****************************************************************************
* Name: gap8_timer_initialize
*
* Description:
* Initialize the timer based on the frequency of source clock and ticks
* per second.
*
****************************************************************************/
void gap8_timer_initialize(uint32_t source_clock, uint32_t tick_per_second);
/****************************************************************************
* Name: gap8_register_timercallback
*
* Description:
* Register a callback function called on timer IRQ
*
****************************************************************************/
void gap8_register_timercallback(void (*on_timer)(void*arg), void *arg);
/****************************************************************************
* Name: gap8_timer_isr
*
* Description:
* ISR for timer
*
****************************************************************************/
void gap8_timer_isr(void);
#endif /* __ARCH_RISC_V_SRC_GAP8_TIM_H */

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/****************************************************************************
* arch/risc-v/src/gapuino/gap8_uart.c
* UART driver on uDMA subsystem for GAP8
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: hhuysqt <1020988872@qq.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/*****************************************************************************
* This UART IP has no flow control. So ioctl is limited.
* Note that here we don't use the uDMA to send multiple bytes, because
* Nuttx serial drivers don't have abstraction for puts().
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <unistd.h>
#include <semaphore.h>
#include <string.h>
#include <errno.h>
#include <debug.h>
#ifdef CONFIG_SERIAL_TERMIOS
# include <termios.h>
#endif
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <nuttx/serial/serial.h>
#include "gap8_uart.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Types
****************************************************************************/
/* Software abstraction
* inherit class _udma_peripheral
*/
struct gap8_uart_t
{
struct gap8_udma_peripheral udma;
/* Private */
uint32_t tx_gpio;
uint32_t rx_gpio;
uint32_t coreclock;
uint32_t baud;
uint8_t nr_bits;
uint8_t parity_enable;
uint8_t stop_bits;
uint8_t is_initialized;
/* IO buffer for uDMA */
uint8_t tx_buf[4];
uint8_t rx_buf[4];
int tx_cnt;
int rx_cnt;
};
/****************************************************************************
* Private Function prototype
****************************************************************************/
/* uart ISR routine */
static void uart_tx_isr(void *arg);
static void uart_rx_isr(void *arg);
/* Serial driver methods */
static int up_setup(struct uart_dev_s *dev);
static void up_shutdown(struct uart_dev_s *dev);
static int up_attach(struct uart_dev_s *dev);
static void up_detach(struct uart_dev_s *dev);
static int up_ioctl(struct file *filep, int cmd, unsigned long arg);
static int up_receive(struct uart_dev_s *dev, uint32_t *status);
static void up_rxint(struct uart_dev_s *dev, bool enable);
static bool up_rxavailable(struct uart_dev_s *dev);
static void up_send(struct uart_dev_s *dev, int ch);
static void up_txint(struct uart_dev_s *dev, bool enable);
static bool up_txready(struct uart_dev_s *dev);
static bool up_txempty(struct uart_dev_s *dev);
/****************************************************************************
* Private Data
****************************************************************************/
static uart_dev_t g_uart0port;
/* nuttx serial console operations */
static const struct uart_ops_s g_uart_ops =
{
.setup = up_setup,
.shutdown = up_shutdown,
.attach = up_attach,
.detach = up_detach,
.ioctl = up_ioctl,
.receive = up_receive,
.rxint = up_rxint,
.rxavailable = up_rxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = NULL,
#endif
.send = up_send,
.txint = up_txint,
.txready = up_txready,
.txempty = up_txempty,
};
/* instantiate the UART */
static struct gap8_uart_t gap8_uarts[GAP8_NR_UART] =
{
{
.udma =
{
.regs = (UDMA_reg_t *)UART,
.id = GAP8_UDMA_ID_UART,
.on_tx = uart_tx_isr,
.tx_arg = &g_uart0port,
.on_rx = uart_rx_isr,
.rx_arg = &g_uart0port,
.is_tx_continous = 0,
.is_rx_continous = 1,
},
.tx_gpio = GAP8_PIN_A7_UART_TX | GAP8_PIN_PULL_UP | GAP8_PIN_SPEED_HIGH,
.rx_gpio = GAP8_PIN_B6_UART_RX | GAP8_PIN_PULL_UP | GAP8_PIN_SPEED_HIGH,
.coreclock = CONFIG_CORE_CLOCK_FREQ, /* to be modified */
.baud = CONFIG_UART_BAUD,
.nr_bits = CONFIG_UART_BITS,
.parity_enable = CONFIG_UART_PARITY,
.stop_bits = CONFIG_UART_2STOP,
.is_initialized = 0,
}
};
/* IO buffers */
static char g_uart1rxbuffer[CONFIG_UART_RXBUFSIZE];
static char g_uart1txbuffer[CONFIG_UART_TXBUFSIZE];
/* Instantiate serial device */
static uart_dev_t g_uart0port =
{
.isconsole = 1,
.recv =
{
.size = CONFIG_UART_RXBUFSIZE,
.buffer = g_uart1rxbuffer,
},
.xmit =
{
.size = CONFIG_UART_TXBUFSIZE,
.buffer = g_uart1txbuffer,
},
.ops = &g_uart_ops,
.priv = &gap8_uarts[0],
};
/****************************************************************************
* Private Function prototype
****************************************************************************/
/****************************************************************************
* Name: uart_tx_isr & uart_rx_isr
*
* Description:
* These are the UART interrupt handler. It is called on uDMA ISR. It
* should call uart_transmitchars or uart_receivechar to invoke the Nuttx
* kernel.
*
****************************************************************************/
static void uart_tx_isr(void *arg)
{
uart_dev_t *dev = (uart_dev_t *)arg;
struct gap8_uart_t *the_uart = (struct gap8_uart_t *)dev->priv;
the_uart->tx_cnt = 0;
uart_xmitchars(dev);
}
static void uart_rx_isr(void *arg)
{
uart_dev_t *dev = (uart_dev_t *)arg;
struct gap8_uart_t *the_uart = (struct gap8_uart_t *)dev->priv;
the_uart->rx_cnt = 1;
uart_recvchars(dev);
}
/****************************************************************************
* Name: up_setup
*
* Description:
* Configure the UART baud, bits, parity, etc. This method is called the
* first time that the serial port is opened.
*
****************************************************************************/
static int up_setup(struct uart_dev_s *dev)
{
struct gap8_uart_t *the_uart = (struct gap8_uart_t *)dev->priv;
UART_reg_t *uartreg = (UART_reg_t *)the_uart->udma.regs;
uint32_t cfgreg = 0;
if (the_uart->is_initialized == 0)
{
uint16_t div = the_uart->coreclock / the_uart->baud;
gap8_udma_init(&the_uart->udma);
/* Setup baudrate etc. */
cfgreg = UART_SETUP_BIT_LENGTH(the_uart->nr_bits - 5) |
UART_SETUP_PARITY_ENA(the_uart->parity_enable) |
UART_SETUP_STOP_BITS(the_uart->stop_bits) |
UART_SETUP_TX_ENA(1) |
UART_SETUP_RX_ENA(1) |
UART_SETUP_CLKDIV(div);
uartreg->SETUP = cfgreg;
gap8_configpin(the_uart->tx_gpio);
gap8_configpin(the_uart->rx_gpio);
the_uart->tx_cnt = 0;
the_uart->rx_cnt = 0;
#if 0
/* Start continous rx */
gap8_udma_rx_start(&the_uart->udma, the_uart->rx_buf, 1, 1);
#endif
}
the_uart->is_initialized = 1;
return OK;
}
/****************************************************************************
* Name: up_shutdown
*
* Description:
* Disable the UART. This method is called when the serial
* port is closed
*
****************************************************************************/
static void up_shutdown(struct uart_dev_s *dev)
{
struct gap8_uart_t *the_uart = (struct gap8_uart_t *)dev->priv;
gap8_udma_deinit(&the_uart->udma);
the_uart->is_initialized = 0;
}
/****************************************************************************
* Name: up_attach
*
* Description:
* Configure the UART to operation in interrupt driven mode. This method is
* called when the serial port is opened. Normally, this is just after the
* the setup() method is called, however, the serial console may operate in
* a non-interrupt driven mode during the boot phase.
*
* RX and TX interrupts are not enabled by the attach method (unless the
* hardware supports multiple levels of interrupt enabling). The RX and TX
* interrupts are not enabled until the txint() and rxint() methods are called.
*
****************************************************************************/
static int up_attach(struct uart_dev_s *dev)
{
struct gap8_uart_t *the_uart = (struct gap8_uart_t *)dev->priv;
if (the_uart->is_initialized == 0)
{
up_setup(dev);
}
return OK;
}
/****************************************************************************
* Name: up_detach
*
* Description:
* Detach UART interrupts. This method is called when the serial port is
* closed normally just before the shutdown method is called. The exception
* is the serial console which is never shutdown.
*
****************************************************************************/
static void up_detach(struct uart_dev_s *dev)
{
struct gap8_uart_t *the_uart = (struct gap8_uart_t *)dev->priv;
gap8_udma_tx_setirq(&the_uart->udma, 0);
gap8_udma_rx_setirq(&the_uart->udma, 0);
}
/****************************************************************************
* Name: up_ioctl
*
* Description:
* All ioctl calls will be routed through this method
*
****************************************************************************/
static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
{
#ifdef CONFIG_SERIAL_TERMIOS
struct inode *inode;
struct uart_dev_s *dev;
struct gap8_uart_t *priv;
int ret = OK;
DEBUGASSERT(filep, filep->f_inode);
inode = filep->f_inode;
dev = inode->i_private;
DEBUGASSERT(dev, dev->priv);
priv = (struct gap8_uart_t *)dev->priv;
switch (cmd)
{
case TCGETS:
{
struct termios *termiosp = (struct termios *)arg;
if (!termiosp)
{
ret = -EINVAL;
break;
}
/* TODO: Other termios fields are not yet returned.
* Note that only cfsetospeed is not necessary because we have
* knowledge that only one speed is supported.
*/
cfsetispeed(termiosp, priv->baud);
}
break;
case TCSETS:
{
struct termios *termiosp = (struct termios *)arg;
if (!termiosp)
{
ret = -EINVAL;
break;
}
/* TODO: Handle other termios settings.
* Note that only cfgetispeed is used besued we have knowledge
* that only one speed is supported.
*/
priv->baud = cfgetispeed(termiosp);
#if 0
gap8_uartconfigure(priv->uartbase, priv->baud, priv->parity,
priv->bits, priv->stopbits2);
#endif
}
break;
default:
ret = -ENOTTY;
break;
}
return ret;
#else
return -ENOTTY;
#endif
}
/****************************************************************************
* Name: up_receive
*
* Description:
* Called (usually) from the interrupt level to receive one
* character from the UART. Error bits associated with the
* receipt are provided in the return 'status'.
*
****************************************************************************/
static int up_receive(struct uart_dev_s *dev, uint32_t *status)
{
struct gap8_uart_t *the_uart = (struct gap8_uart_t *)dev->priv;
uint8_t ch = the_uart->rx_buf[0];
the_uart->rx_cnt = 0;
if (status)
{
*status = 0; /* We are not yet tracking serial errors */
}
/* Then trigger another reception */
gap8_udma_rx_start(&the_uart->udma, the_uart->rx_buf, 1, 1);
return (int)ch;
}
/****************************************************************************
* Name: up_rxint
*
* Description:
* Call to enable or disable RX interrupts
*
****************************************************************************/
static void up_rxint(struct uart_dev_s *dev, bool enable)
{
struct gap8_uart_t *the_uart = (struct gap8_uart_t *)dev->priv;
irqstate_t flags;
flags = enter_critical_section();
if (enable)
{
gap8_udma_rx_setirq(&the_uart->udma, 1);
#if 0
if (the_uart->rx_cnt == 0)
#endif
{
gap8_udma_rx_start(&the_uart->udma, the_uart->rx_buf, 1, 1);
}
}
#if 0
else
{
gap8_udma_rx_setirq(&the_uart->udma, 0);
}
#endif
leave_critical_section(flags);
}
/****************************************************************************
* Name: up_rxavailable
*
* Description:
* Return true if the receive register is not empty
*
****************************************************************************/
static bool up_rxavailable(struct uart_dev_s *dev)
{
struct gap8_uart_t *the_uart = (struct gap8_uart_t *)dev->priv;
return the_uart->rx_cnt > 0;
}
/****************************************************************************
* Name: up_send
*
* Description:
* This method will send one byte on the UART.
*
****************************************************************************/
static void up_send(struct uart_dev_s *dev, int ch)
{
struct gap8_uart_t *the_uart = (struct gap8_uart_t *)dev->priv;
the_uart->tx_buf[0] = (uint8_t)ch;
the_uart->tx_buf[1] = 0;
the_uart->tx_cnt = 1;
gap8_udma_tx_start(&the_uart->udma, the_uart->tx_buf, 1, 1);
}
/****************************************************************************
* Name: up_txint
*
* Description:
* Call to enable or disable TX interrupts
*
****************************************************************************/
static void up_txint(struct uart_dev_s *dev, bool enable)
{
struct gap8_uart_t *the_uart = (struct gap8_uart_t *)dev->priv;
irqstate_t flags;
flags = enter_critical_section();
if (enable)
{
gap8_udma_tx_setirq(&the_uart->udma, 1);
/* Fake a TX interrupt here by just calling uart_xmitchars() with
* interrupts disabled (note this may recurse).
*/
uart_xmitchars(dev);
}
else
{
gap8_udma_tx_setirq(&the_uart->udma, 0);
}
leave_critical_section(flags);
}
/****************************************************************************
* Name: up_txready
*
* Description:
* Return true if the tranmsit data register is empty
*
****************************************************************************/
static bool up_txready(struct uart_dev_s *dev)
{
struct gap8_uart_t *the_uart = (struct gap8_uart_t *)dev->priv;
return (the_uart->tx_cnt == 0) ? true : false;
}
/****************************************************************************
* Name: up_txempty
*
* Description:
* Return true if the transmit data register is empty
*
****************************************************************************/
static bool up_txempty(struct uart_dev_s *dev)
{
struct gap8_uart_t *the_uart = (struct gap8_uart_t *)dev->priv;
return (the_uart->tx_cnt == 0) ? true : false;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_earlyserialinit
*
* Description:
* Performs the low level UART initialization early in debug so that the
* serial console will be available during bootup. This must be called
* before up_serialinit. NOTE: This function depends on GPIO pin
* configuration performed in up_consoleinit() and main clock iniialization
* performed in up_clkinitialize().
*
****************************************************************************/
void up_earlyserialinit(void)
{
/* Configuration whichever one is the console */
#ifdef CONFIG_UART_SERIAL_CONSOLE
g_uart0port.isconsole = true;
up_setup(&g_uart0port);
#endif
}
/****************************************************************************
* Name: up_serialinit
*
* Description:
* Register serial console and serial ports. This assumes
* that up_earlyserialinit was called previously.
*
****************************************************************************/
void up_serialinit(void)
{
#ifdef CONFIG_UART_SERIAL_CONSOLE
(void)uart_register("/dev/console", &g_uart0port);
#endif
(void)uart_register("/dev/ttyS0", &g_uart0port);
}
/****************************************************************************
* Name: up_putc
*
* Description:
* Provide priority, low-level access to support OS debug writes
*
****************************************************************************/
int up_putc(int ch)
{
#ifdef CONFIG_UART_SERIAL_CONSOLE
struct uart_dev_s *dev = (struct uart_dev_s *)&g_uart0port;
/* Check for LF */
if (ch == '\n')
{
/* Add CR */
up_putc('\r');
}
up_send(dev, ch);
#endif
return ch;
}

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/************************************************************************************
* arch/risc-v/src/gap8/gap8_uart.h
* UART driver on uDMA subsystem for GAP8
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: hhuysqt <1020988872@qq.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/************************************************************************************
* This UART IP has no flow control. So ioctl is limited.
************************************************************************************/
#ifndef _ARCH_RISCV_SRC_GAP8_UART_H
#define _ARCH_RISCV_SRC_GAP8_UART_H
/************************************************************************************
* Included Files
************************************************************************************/
#include "chip.h"
#include "gap8_udma.h"
#include "gap8_gpio.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
#define GAP8_NR_UART 1
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
void up_earlyserialinit(void);
void up_serialinit(void);
int up_putc(int ch);
#endif /* _ARCH_RISCV_SRC_GAP8_UART_H */

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/****************************************************************************
* arch/risc-v/src/gapuino/gap8_udma.c
* uDMA driver for GAP8
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: hhuysqt <1020988872@qq.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* GAP8 features a simple uDMA subsystem. Peripherals including UART, SPI,
* I2C, I2S, CPI, LVDS, Hyperbus, have config registers memory-mapped, but
* not data registers. The only way to send or receive data is using the
* uDMA. Those peripherals share the same uDMA ISR.
*
* Note that uDMA can only recognize L2 RAM. So data must not be stored at
* L1, which means that if you link the stack at L1, you cannot use local
* buffers as data src or destination.
*
* As for the UART driver, the SOC_EU may fire a redundant IRQ even if the
* uDMA hasn't finished its job. So I spin on TX channel and bypass on RX
* channel, if the IRQ is redundant.
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include "gap8_udma.h"
#include <stddef.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define CHECK_CHANNEL_ID(INSTANCE) \
if ((INSTANCE) == NULL || \
(INSTANCE)->id >= GAP8_UDMA_NR_CHANNELS) \
{ \
return ERROR; \
}
/****************************************************************************
* Private Data
****************************************************************************/
/* uDMA peripheral instances
* The peripheral driver instantiate it and register through _init()
*/
static struct gap8_udma_peripheral *_peripherals[GAP8_UDMA_NR_CHANNELS] = { 0 };
/****************************************************************************
* Private Functions
****************************************************************************/
static void _dma_txstart(struct gap8_udma_peripheral *the_peri)
{
the_peri->regs->TX_SADDR = (uint32_t)the_peri->tx.buff;
the_peri->regs->TX_SIZE = (uint32_t)the_peri->tx.block_size;
the_peri->regs->TX_CFG = UDMA_CFG_EN(1);
}
static void _dma_rxstart(struct gap8_udma_peripheral *the_peri)
{
the_peri->regs->RX_SADDR = (uint32_t)the_peri->rx.buff;
the_peri->regs->RX_SIZE = (uint32_t)the_peri->rx.block_size;
the_peri->regs->RX_CFG = UDMA_CFG_EN(1);
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: gap8_udma_init
*
* Description:
* Initialize (and enable) a udma peripheral.
*
* Input:
* instance: pointer to a peripheral instance connected to uDMA
*
****************************************************************************/
int gap8_udma_init(struct gap8_udma_peripheral *instance)
{
uint32_t id;
CHECK_CHANNEL_ID(instance)
id = instance->id;
_peripherals[id] = instance;
/* Enable clock gating */
UDMA_GC->CG |= (1L << id);
return OK;
}
/****************************************************************************
* Name: gap8_udma_deinit
*
* Description:
* Deinit a udma peripheral
*
****************************************************************************/
int gap8_udma_deinit(struct gap8_udma_peripheral *instance)
{
uint32_t id;
CHECK_CHANNEL_ID(instance)
id = instance->id;
_peripherals[id] = NULL;
/* Disable clock gating */
UDMA_GC->CG &= ~(1L << id);
return OK;
}
/****************************************************************************
* Name: gap8_udma_tx_setirq
*
* Description:
* Enable or disable the tx interrupt.
*
****************************************************************************/
int gap8_udma_tx_setirq(struct gap8_udma_peripheral *instance, bool enable)
{
CHECK_CHANNEL_ID(instance)
/* The irq enable bit happened to be 2*id + 1 */
if (enable)
{
up_enable_event(1 + (instance->id << 1));
}
else
{
up_disable_event(1 + (instance->id << 1));
#if 0
instance->regs->TX_CFG = UDMA_CFG_CLR(1);
#endif
}
return OK;
}
/****************************************************************************
* Name: gap8_udma_rx_setirq
*
* Description:
* Enable or disable the rx interrupt.
*
****************************************************************************/
int gap8_udma_rx_setirq(struct gap8_udma_peripheral *instance, bool enable)
{
CHECK_CHANNEL_ID(instance)
/* The irq enable bit happened to be 2*id */
if (enable)
{
up_enable_event(instance->id << 1);
}
else
{
up_disable_event(instance->id << 1);
#if 0
instance->regs->RX_CFG = UDMA_CFG_CLR(1);
#endif
}
return OK;
}
/****************************************************************************
* Name: gap8_udma_tx_start
*
* Description:
* Send size * count bytes non-blocking.
*
* This function may be called from ISR, so it cannot be blocked. The
* caller should manage the muxing.
*
****************************************************************************/
int gap8_udma_tx_start(struct gap8_udma_peripheral *instance,
uint8_t *buff, uint32_t size, int count)
{
CHECK_CHANNEL_ID(instance)
instance->tx.buff = buff;
instance->tx.block_size = size;
instance->tx.block_count = count;
_dma_txstart(instance);
return OK;
}
/****************************************************************************
* Name: gap8_udma_rx_start
*
* Description:
* Receive size * count bytes
*
* This function may be called from ISR, so it cannot be blocked. The
* caller should manage the muxing.
*
****************************************************************************/
int gap8_udma_rx_start(struct gap8_udma_peripheral *instance,
uint8_t *buff, uint32_t size, int count)
{
CHECK_CHANNEL_ID(instance)
instance->rx.buff = buff;
instance->rx.block_size = size;
instance->rx.block_count = count;
_dma_rxstart(instance);
return OK;
}
/****************************************************************************
* Name: gap8_udma_tx_poll
*
* Description:
* Return OK if the buffer is not in the tx pending list.
*
****************************************************************************/
int gap8_udma_tx_poll(struct gap8_udma_peripheral *instance)
{
CHECK_CHANNEL_ID(instance)
return instance->tx.block_count <= 0 ? OK : ERROR;
}
/****************************************************************************
* Name: gap8_udma_rx_poll
*
* Description:
* Return OK if the buffer is not in the rx pending list.
*
****************************************************************************/
int gap8_udma_rx_poll(struct gap8_udma_peripheral *instance)
{
CHECK_CHANNEL_ID(instance)
return instance->rx.block_count <= 0 ? OK : ERROR;
}
/****************************************************************************
* Name: gap8_udma_doirq
*
* Description:
* uDMA ISR
*
***************************************************************************/
int gap8_udma_doirq(int irq, void *context, FAR void *arg)
{
struct gap8_udma_peripheral *the_peripheral;
uint32_t event = SOC_EVENTS->CURRENT_EVENT & 0xff;
if (event > GAP8_UDMA_MAX_EVENT)
{
/* Bypass */
return OK;
}
/* Peripheral id happened to be half of event... */
the_peripheral = _peripherals[event >> 1];
if (the_peripheral == NULL)
{
return OK;
}
if (event & 0x1)
{
/* Tx channel */
if (the_peripheral->tx.block_count > 1)
{
the_peripheral->tx.block_count--;
the_peripheral->tx.buff += the_peripheral->tx.block_size;
_dma_txstart(the_peripheral);
}
else
{
/* The buffer is exhausted. Forward to peripheral's driver */
while (the_peripheral->regs->TX_SIZE != 0)
{
/* I don't know why but I have to spin here. SOC_EU would
* fire the IRQ even if uDMA hasn't finished the job.
* If I bypassed it, I would lose the finish event...
*/
}
the_peripheral->tx.block_count = 0;
if (the_peripheral->on_tx)
{
the_peripheral->on_tx(the_peripheral->tx_arg);
}
}
}
else
{
/* Rx channel */
if (the_peripheral->rx.block_count > 1)
{
the_peripheral->rx.block_count--;
the_peripheral->rx.buff += the_peripheral->rx.block_size;
_dma_rxstart(the_peripheral);
}
else if (!(the_peripheral->regs->RX_CFG & UDMA_CFG_CLR(1)))
{
/* The buffer is exhausted. Forward to peripheral's driver
*
* Again I don't know why but I have to test the PENDING bit of
* the uDMA, so as to avoid the redundant IRQ...
*/
the_peripheral->rx.block_count = 0;
if (the_peripheral->on_rx)
{
the_peripheral->on_rx(the_peripheral->rx_arg);
}
}
}
return OK;
}

225
arch/risc-v/src/gap8/gap8_udma.h Normal file
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@ -0,0 +1,225 @@
/************************************************************************************
* arch/risc-v/src/gap8/gap8_udma.h
* uDMA driver for GAP8
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: hhuysqt <1020988872@qq.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/************************************************************************************
* GAP8 features a simple uDMA subsystem. Peripherals including UART, SPI, I2C, I2S,
* CPI, LVDS, Hyperbus, have config registers memory-mapped, but not data registers.
* The only way to send or receive data is using the uDMA. These peripherals share
* the same uDMA ISR.
*
* uDMA sybsystem drivers are object oriented to some extend. Peripherals inherit
* the udma class, which handels all the data exchange stuff.
************************************************************************************/
#ifndef _ARCH_RISCV_SRC_GAP8_UDMA_H
#define _ARCH_RISCV_SRC_GAP8_UDMA_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <stdbool.h>
#include "chip.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* uDMA channel ID */
#define GAP8_UDMA_ID_LVDS 0
#define GAP8_UDMA_ID_SPIM0 1
#define GAP8_UDMA_ID_SPIM1 2
#define GAP8_UDMA_ID_HYPER 3
#define GAP8_UDMA_ID_UART 4
#define GAP8_UDMA_ID_I2C0 5
#define GAP8_UDMA_ID_I2C1 6
#define GAP8_UDMA_ID_TCDM 7 /* l2 to fc-l1 */
#define GAP8_UDMA_ID_I2S 8
#define GAP8_UDMA_ID_CPI 9
/* Total udma channels */
#define GAP8_UDMA_NR_CHANNELS 10
/************************************************************************************
* Public Types
************************************************************************************/
/* Software abstraction for uDMA */
/* One round of data exchange on one channel gathered into linked list because
* threads would request for data exchange simultaneously.
* Private for udma driver.
*/
struct __udma_queue
{
uint8_t *buff; /* Memory address. either TX or RX */
uint32_t block_size; /* Size of a data block in bytes */
int block_count; /* Number of blocks to send or recv */
};
/* This is the base class of uDMA subsystem. Peripherals connected to uDMA
* should inherited this class.
*/
struct gap8_udma_peripheral
{
/* Public */
UDMA_reg_t *regs; /* Hardware config regs */
uint32_t id; /* GAP8_UDMA_ID_x */
void (*on_tx)(void *arg); /* tx callback */
void (*on_rx)(void *arg); /* rx callback */
void *tx_arg; /* tx argument */
void *rx_arg; /* rx argument */
uint16_t is_tx_continous;
uint16_t is_rx_continous;
/* Private */
struct __udma_queue tx; /* TX queue */
struct __udma_queue rx; /* RX queue */
};
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
/************************************************************************************
* Name: gap8_udma_init
*
* Description:
* Initialize (and enable) a udma peripheral.
*
* Input:
* instance: pointer to a peripheral instance connected to uDMA
*
************************************************************************************/
int gap8_udma_init(struct gap8_udma_peripheral *instance);
/************************************************************************************
* Name: gap8_udma_deinit
*
* Description:
* Deinit a udma peripheral
*
************************************************************************************/
int gap8_udma_deinit(struct gap8_udma_peripheral *instance);
/************************************************************************************
* Name: gap8_udma_tx_setirq
*
* Description:
* Enable or disable the tx interrupt.
*
************************************************************************************/
int gap8_udma_tx_setirq(struct gap8_udma_peripheral *instance, bool enable);
/************************************************************************************
* Name: gap8_udma_rx_setirq
*
* Description:
* Enable or disable the rx interrupt.
*
************************************************************************************/
int gap8_udma_rx_setirq(struct gap8_udma_peripheral *instance, bool enable);
/************************************************************************************
* Name: gap8_udma_tx_start
*
* Description:
* Send size * count bytes non-blocking.
*
* Return ERROR if unable to send. The caller should poll on execution, or register
* a on_tx to get the signal.
*
************************************************************************************/
int gap8_udma_tx_start(struct gap8_udma_peripheral *instance,
uint8_t *buff, uint32_t size, int count);
/************************************************************************************
* Name: gap8_udma_rx_start
*
* Description:
* Receive size * count bytes
*
* Return ERROR if unable to send. The caller should poll on execution, or register
* a on_rx to get the signal.
*
************************************************************************************/
int gap8_udma_rx_start(struct gap8_udma_peripheral *instance,
uint8_t *buff, uint32_t size, int count);
/************************************************************************************
* Name: gap8_udma_tx_poll
*
* Description:
* Return OK if tx finished.
*
************************************************************************************/
int gap8_udma_tx_poll(struct gap8_udma_peripheral *instance);
/************************************************************************************
* Name: gap8_udma_rx_poll
*
* Description:
* Return OK if rx finished.
*
************************************************************************************/
int gap8_udma_rx_poll(struct gap8_udma_peripheral *instance);
/************************************************************************************
* Name: gap8_udma_doirq
*
* Description:
* uDMA ISR
*
************************************************************************************/
int gap8_udma_doirq(int irq, void *context, FAR void *arg);
#endif /* _ARCH_RISCV_SRC_GAP8_UDMA_H */

377
arch/risc-v/src/gap8/startup_gap8.S Normal file
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@ -0,0 +1,377 @@
/****************************************************************************
* arch/risc-v/src/gapuino/startup_gap8.S
* Startup file for FC of GAP8
* Interrupt vector and reset handler
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: hhuysqt <1020988872@qq.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Exception context size: EPC + 31 common regs + 6 loop regs */
#define EXCEPTION_STACK_SIZE 4*38
/****************************************************************************
* Assembler Macro Definitions
****************************************************************************/
/* save all the registers on interrupt entry */
.macro SAVE_REGS
addi sp, sp, -EXCEPTION_STACK_SIZE
sw x1, 1*4(sp) /* ra */
sw x3, 3*4(sp) /* gp */
sw x4, 4*4(sp) /* tp */
sw x5, 5*4(sp) /* t0 */
sw x6, 6*4(sp) /* t1 */
sw x7, 7*4(sp) /* t2 */
sw x8, 8*4(sp) /* s0 */
sw x9, 9*4(sp) /* s1 */
sw x10, 10*4(sp) /* a0 */
sw x11, 11*4(sp) /* a1 */
sw x12, 12*4(sp) /* a2 */
sw x13, 13*4(sp) /* a3 */
sw x14, 14*4(sp) /* a4 */
sw x15, 15*4(sp) /* a5 */
sw x16, 16*4(sp) /* a6 */
sw x17, 17*4(sp) /* a7 */
sw x18, 18*4(sp) /* s2 */
sw x19, 19*4(sp) /* s3 */
sw x20, 20*4(sp) /* s4 */
sw x21, 21*4(sp) /* s5 */
sw x22, 22*4(sp) /* s6 */
sw x23, 23*4(sp) /* s7 */
sw x24, 24*4(sp) /* s8 */
sw x25, 25*4(sp) /* s9 */
sw x26, 26*4(sp) /* s10 */
sw x27, 27*4(sp) /* s11 */
sw x28, 28*4(sp) /* t3 */
sw x29, 29*4(sp) /* t4 */
sw x30, 30*4(sp) /* t5 */
sw x31, 31*4(sp) /* t6 */
csrr x28, 0x7B0
csrr x29, 0x7B1
csrr x30, 0x7B2
sw x28, 32*4(sp) /* lpstart[0] */
sw x29, 33*4(sp) /* lpend[0] */
sw x30, 34*4(sp) /* lpcount[0] */
csrr x28, 0x7B4
csrr x29, 0x7B5
csrr x30, 0x7B6
sw x28, 35*4(sp) /* lpstart[1] */
sw x29, 36*4(sp) /* lpend[1] */
sw x30, 37*4(sp) /* lpcount[1] */
addi s0, sp, EXCEPTION_STACK_SIZE
sw s0, 2*4(sp) /* original SP */
.endm
/* restore regs and `mret` */
.macro RESTORE_REGS
lw x28, 35*4(sp) /* lpstart[1] */
lw x29, 36*4(sp) /* lpend[1] */
lw x30, 37*4(sp) /* lpcount[1] */
csrrw x0, 0x7B4, x28
csrrw x0, 0x7B5, x29
csrrw x0, 0x7B6, x30
lw x28, 32*4(sp) /* lpstart[0] */
lw x29, 33*4(sp) /* lpend[0] */
lw x30, 34*4(sp) /* lpcount[0] */
csrrw x0, 0x7B0, x28
csrrw x0, 0x7B1, x29
csrrw x0, 0x7B2, x30
li s0, 0x1890 /* machine mode, UPIE & MPIE enabled */
csrrw x0, mstatus, s0
lw x3, 3*4(sp) /* gp */
lw x4, 4*4(sp) /* tp */
lw x5, 5*4(sp) /* t0 */
lw x6, 6*4(sp) /* t1 */
lw x7, 7*4(sp) /* t2 */
lw x8, 8*4(sp) /* s0 */
lw x9, 9*4(sp) /* s1 */
lw x10, 10*4(sp) /* a0 */
lw x11, 11*4(sp) /* a1 */
lw x12, 12*4(sp) /* a2 */
lw x13, 13*4(sp) /* a3 */
lw x14, 14*4(sp) /* a4 */
lw x15, 15*4(sp) /* a5 */
lw x16, 16*4(sp) /* a6 */
lw x17, 17*4(sp) /* a7 */
lw x18, 18*4(sp) /* s2 */
lw x19, 19*4(sp) /* s3 */
lw x20, 20*4(sp) /* s4 */
lw x21, 21*4(sp) /* s5 */
lw x22, 22*4(sp) /* s6 */
lw x23, 23*4(sp) /* s7 */
lw x24, 24*4(sp) /* s8 */
lw x25, 25*4(sp) /* s9 */
lw x26, 26*4(sp) /* s10 */
lw x27, 27*4(sp) /* s11 */
lw x28, 28*4(sp) /* t3 */
lw x29, 29*4(sp) /* t4 */
lw x30, 30*4(sp) /* t5 */
lw x31, 31*4(sp) /* t6 */
lw x1, 1*4(sp) /* ra */
lw sp, 2*4(sp) /* restore original sp */
.endm
/* wrapper for IRQ vector */
.macro WRAP_IRQ Routine, IRQn
wrap_irq_\Routine :
SAVE_REGS
csrr s0, mepc
sw s0, 0(sp) /* exception PC */
li a0, \IRQn /* irq = IRQn */
mv a1, sp /* context = sp */
jal x1, gap8_dispatch_irq
/* If context switch is needed, return
* a new sp
*/
mv sp, a0
lw s0, 0(sp) /* restore ePC */
csrw mepc, s0
RESTORE_REGS
mret
.endm
/*******************************************************************************
* External Variables and Functions
*******************************************************************************/
.extern _sbss
.extern _ebss
.extern _idle_stack_end
.extern gap8_dispatch_irq
.extern os_start
.extern gapuino_sysinit
/*******************************************************************************
* Reset handler
*******************************************************************************/
reset_handler:
#if 0
csrr a0, 0xf14 /* Cluster ID */
srli a0, a0, 5
#endif
li a0, 0x1800 /* Set MSTATUS : Machine Mode */
csrw mstatus, a0
li a0, 0x1C000000 /* Set MTVEC */
csrw mtvec, a0
/* stack initilization */
la x2, _idle_stack_end
/* clear BSS */
la x26, _sbss
la x27, _ebss
bge x26, x27, zero_loop_end
zero_loop:
sw x0, 0(x26)
addi x26, x26, 4
ble x26, x27, zero_loop
zero_loop_end:
/* TODO: initialize data section */
#if 0
/* Run global initialization functions */
call __libc_init_array
#endif
/* Initialize cache and clock */
jal x1, gapuino_sysinit
/* Directly call Nuttx os_start() */
jal x1, os_start
/* If it ever returns, spin here forever... */
dead_loop:
jal x0, dead_loop
/* IRQ wrappers
* IRQn are identical to gap8_interrupt.h
*/
WRAP_IRQ sw_evt0, 0
WRAP_IRQ sw_evt1, 1
WRAP_IRQ sw_evt2, 2
WRAP_IRQ sw_evt3, 3
WRAP_IRQ sw_evt4, 4
WRAP_IRQ sw_evt5, 5
WRAP_IRQ sw_evt6, 6
WRAP_IRQ sw_evt7, 7
WRAP_IRQ timer_lo, 10
WRAP_IRQ timer_hi, 11
WRAP_IRQ udma, 27
WRAP_IRQ mpu, 28
WRAP_IRQ udma_err, 29
WRAP_IRQ fc_hp0, 30
WRAP_IRQ fc_hp1, 31
WRAP_IRQ reserved, 60
/* RISCV exceptions */
illegal_insn_handler:
csrr s0, mepc
sw s0, 0*4(sp) /* exception PC */
/* Spin here so that debugger would read `s0` */
1:
j 1b
/* Systemcall handler */
ecall_insn_handler:
SAVE_REGS
/* Point to the next instruction of `ecall` */
csrr s0, mepc
addi s0, s0, 4
sw s0, 0(sp) /* exception PC */
li a0, 34 /* irq = 34 */
mv a1, sp /* context = sp */
jal x1, gap8_dispatch_irq
/* If context switch is needed, return
* a new sp
*/
mv sp, a0
lw s0, 0(sp) /* restore ePC */
csrw mepc, s0
RESTORE_REGS
mret
/*******************************************************************************
* INTERRUPT VECTOR TABLE
*******************************************************************************/
/* This section has to be down here, since we have to disable rvc for it */
.section .vectors_M, "ax"
.option norvc;
j wrap_irq_sw_evt0 /* 0 */
j wrap_irq_sw_evt1 /* 1 */
j wrap_irq_sw_evt2 /* 2 */
j wrap_irq_sw_evt3 /* 3 */
j wrap_irq_sw_evt4 /* 4 */
j wrap_irq_sw_evt5 /* 5 */
j wrap_irq_sw_evt6 /* 6 */
j wrap_irq_sw_evt7 /* 7 */
j wrap_irq_reserved /* 8 */
j wrap_irq_reserved /* 9 */
j wrap_irq_timer_lo /* 10 */
j wrap_irq_timer_hi /* 11 */
j wrap_irq_reserved /* 12 */
j wrap_irq_reserved /* 13 */
j wrap_irq_reserved /* 14 */
j wrap_irq_reserved /* 15 */
j wrap_irq_reserved /* 16 */
j wrap_irq_reserved /* 17 */
j wrap_irq_reserved /* 18 */
j wrap_irq_reserved /* 19 */
j wrap_irq_reserved /* 20 */
j wrap_irq_reserved /* 21 */
j wrap_irq_reserved /* 22 */
j wrap_irq_reserved /* 23 */
j wrap_irq_reserved /* 24 */
j wrap_irq_reserved /* 25 */
j wrap_irq_reserved /* 26 */
j wrap_irq_udma /* 27 */
j wrap_irq_mpu /* 28 */
j wrap_irq_udma_err /* 29 */
j wrap_irq_fc_hp0 /* 30 */
j wrap_irq_fc_hp1 /* 31 */
j reset_handler /* 32 */
j illegal_insn_handler/* 33 */
j ecall_insn_handler /* 34 */
/****************************************************************************
* This variable is pointed to the structure containing all information
* exchanged with the platform loader. It is using a fixed address so that
* the loader can also find it and then knows the address of the debug
* structure.
****************************************************************************/
.section .dbg_struct, "ax"
.option norvc;
.org 0x90
.global __rt_debug_struct_ptr
__rt_debug_struct_ptr:
.word Debug_Struct
/****************************************************************************
* This global variable is unsigned int g_idle_topstack and is exported here
* only because of its coupling to idle thread stack.
****************************************************************************/
.section .data
.global g_idle_topstack
g_idle_topstack:
.word _idle_stack_end

9
arch/risc-v/src/rv32im/Kconfig
View File

@ -25,6 +25,15 @@ config RV32IM_TOOLCHAIN_GNU_RVGW
This option should work for any modern GNU toolchain (GCC 5.2 or newer)
configured for riscv32-unknown-elf.
config RI5CY_GAP8_TOOLCHAIN
bool "toolchain from gap_riscv_toolchain"
select ARCH_TOOLCHAIN_GNU
---help---
Choose the toolchain of riscv32-unknown-elf with full support
for PULP extensions. gap_sdk also uses it.
https://github.com/GreenWaves-Technologies/gap_riscv_toolchain/
endchoice
config RV32IM_HW_MULDIV

11
arch/risc-v/src/rv32im/Toolchain.defs
View File

@ -52,6 +52,10 @@ ifeq ($(filter y, $(CONFIG_RV32IM_TOOLCHAIN_GNU_RVGW)),y)
CONFIG_RISCV_TOOLCHAIN ?= GNU_RVGW
endif
ifeq ($(filter y, $(CONFIG_RI5CY_GAP8_TOOLCHAIN)),y)
CONFIG_RISCV_TOOLCHAIN ?= GNU_RISCY
endif
#
# Supported toolchains
#
@ -95,10 +99,15 @@ else
endif
endif
ifeq ($(CONFIG_RISCV_TOOLCHAIN),GNU_RISCY)
CROSSDEV ?= riscv32-unknown-elf-
ARCROSSDEV ?= riscv32-unknown-elf-
ARCHCPUFLAGS = -march=rv32imcxgap8 -mPE=8 -mFC=1 -D__riscv__ -D__pulp__ -D__GAP8__
endif
# Individual tools may limit the optimizatin level but, by default, the
# optimization level will be set to to -Os
ifeq ($(CONFIG_DEBUG_SYMBOLS),)
MAXOPTIMIZATION ?= -Os
endif

11
configs/Kconfig
View File

@ -272,6 +272,13 @@ config ARCH_BOARD_FREEDOM_KL26Z
This is the configuration for the NXP/FreeScale Freedom KL26Z board. This
board has the K26Z128VLH4 chip with a built-in SDA debugger.
config ARCH_BOARD_GAPUINO
bool "GWT gapuino board"
depends on ARCH_CHIP_GAP8
select UART_SERIALDRIVER
---help---
Nuttx port for gapuino, a GAP8 evaluation board.
config ARCH_BOARD_HYMINI_STM32V
bool "HY-Mini STM32v board"
depends on ARCH_CHIP_STM32F103VC
@ -1698,6 +1705,7 @@ config ARCH_BOARD
default "freedom-k66f" if ARCH_BOARD_FREEDOM_K66F
default "freedom-kl25z" if ARCH_BOARD_FREEDOM_KL25Z
default "freedom-kl26z" if ARCH_BOARD_FREEDOM_KL26Z
default "gapuino" if ARCH_BOARD_GAPUINO
default "hymini-stm32v" if ARCH_BOARD_HYMINI_STM32V
default "imxrt1050-evk" if ARCH_BOARD_IMXRT1050_EVK
default "kwikstik-k40" if ARCH_BOARD_KWIKSTIK_K40
@ -1945,6 +1953,9 @@ endif
if ARCH_BOARD_FREEDOM_KL26Z
source "configs/freedom-kl26z/Kconfig"
endif
if ARCH_BOARD_GAPUINO
source "configs/gapuino/Kconfig"
endif
if ARCH_BOARD_HYMINI_STM32V
source "configs/hymini-stm32v/Kconfig"
endif

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#
# For a description of the syntax of this configuration file,
# see misc/tools/kconfig-language.txt.
#
if ARCH_BOARD_GAPUINO
endif

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README
======
gapuino is an evaluation board for GAP8, a 1+8-core DSP-like RISC-V
MCU. GAP8 features a RI5CY core called Fabric Controller(FC), and a
cluster of 8 RI5CY cores that runs at a bit slower speed. GAP8 is an
implementation of the opensource PULP platform, a Parallel-Ultra-Low-
Power design.
The port is currently very minimal, though additional support may be
added in the future to address more of the board peripherals.
Supported:
- USB UART (console port)
- uDMA on SOC domain
- FLL clock scaling
Not supported:
- SPI, I2C, I2S, CPI, LVDS, Hyper-bus on the uDMA subsystem
- the sensor board
- the 8-core cluster
- the Hardware convolution engine
See also:
gapuino board and the sensor board:
https://gwt-website-files.s3.amazonaws.com/gapuino_um.pdf
https://gwt-website-files.s3.amazonaws.com/gapuino_multisensor_um.pdf
GAP8 datasheet:
https://gwt-website-files.s3.amazonaws.com/gap8_datasheet.pdf
Contents
========
- Environment Setup
- Configurations
- Execute
Environment Setup
=================
First, setup the gap_sdk from GreenwavesTechnologies' github repo.
Follow the README to setup the toolchain and environment.
https://github.com/GreenWaves-Technologies/gap_sdk/
Configurations
==============
Each gapuino configuration is maintained in a sub-directory and can
be selected as follow:
tools/configure.sh gapuino/<subdir>
Where <subdir> is one of the following:
nsh
---
This is an NSH example that uses the UART connected to FT2232 as
the console. Default UART settings are 115200, 8N1.
Execute
=======
You may download the ELF to the board by `plpbridge` in gap_sdk.
Remember to first `cd` to the gap_sdk/ and `source sourceme.sh`, so
that you have the $GAP_SDK_HOME environment varible.
Use the following command to download and run the ELF through JTAG:
$GAP_SDK_HOME/install/workstation/bin/plpbridge \
--cable=ftdi@digilent --boot-mode=jtag --chip=gap \
--binary=nuttx \
load ioloop reqloop start wait
As for debugging, the following command download the ELF and opens
a gdbserver on port 1234:
$GAP_SDK_HOME/install/workstation/bin/plpbridge \
--cable=ftdi@digilent --boot-mode=jtag --chip=gap \
--binary=nuttx \
load ioloop gdb wait
And then launch the gdb on another terminal:
riscv32-unknown-elf-gdb nuttx
...
(gdb) target remote :1234
Remote debugging using :1234
IRQ_U_Vector_Base () at chip/startup_gap8.S:293
293 j reset_handler /* 32 */
(gdb)
And then enjoy yourself debugging with the CLI gdb :-)

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/************************************************************************************
* configs/gapuino/include/board.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: hhuysqt <1020988872@qq.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __CONFIG_GAPUINO_INCLUDE_BOARD_H
#define __CONFIG_GAPUINO_INCLUDE_BOARD_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#ifndef __ASSEMBLY__
# include <stdint.h>
#endif
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __CONFIG_NR5M100_NEXYS4_INCLUDE_BOARD_H */

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# CONFIG_NSH_DISABLE_LOSMART is not set
# CONFIG_STANDARD_SERIAL is not set
CONFIG_ARCH="risc-v"
CONFIG_ARCH_BOARD="gapuino"
CONFIG_ARCH_BOARD_GAPUINO=y
CONFIG_ARCH_CHIP_GAP8=y
CONFIG_ARCH_RISCV=y
CONFIG_ARCH_STACKDUMP=y
CONFIG_BOARD_LOOPSPERMSEC=15000
CONFIG_BUILTIN=y
CONFIG_DEBUG_FULLOPT=y
CONFIG_DEBUG_SYMBOLS=y
CONFIG_DEV_ZERO=y
CONFIG_DISABLE_POLL=y
CONFIG_FS_PROCFS=y
CONFIG_FS_WRITABLE=y
CONFIG_IDLETHREAD_STACKSIZE=2048
CONFIG_INTELHEX_BINARY=y
CONFIG_LIBC_PERROR_STDOUT=y
CONFIG_LIBC_STRERROR=y
CONFIG_MAX_TASKS=16
CONFIG_MAX_WDOGPARMS=2
CONFIG_NFILE_DESCRIPTORS=8
CONFIG_NFILE_STREAMS=8
CONFIG_NSH_ARCHINIT=y
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_DISABLE_IFUPDOWN=y
CONFIG_NSH_DISABLE_MKRD=y
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_LINELEN=64
CONFIG_NSH_READLINE=y
CONFIG_NSH_STRERROR=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=4
CONFIG_RAM_SIZE=524288
CONFIG_RAM_START=0x1C000000
CONFIG_RAW_BINARY=y
CONFIG_RI5CY_GAP8_TOOLCHAIN=y
CONFIG_RR_INTERVAL=200
CONFIG_RV32IM_HW_MULDIV=y
CONFIG_RV32IM_SYSTEM_CSRRS_SUPPORT=y
CONFIG_START_DAY=27
CONFIG_START_YEAR=2013
CONFIG_SYSTEM_NSH=y
CONFIG_TASK_NAME_SIZE=0
CONFIG_UART_SERIAL_CONSOLE=y
CONFIG_USER_ENTRYPOINT="nsh_main"
CONFIG_WDOG_INTRESERVE=0

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############################################################################
# configs/gapuino/scripts/Make.defs
#
# Copyright (C) 2018 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <gnutt@nuttx.org>
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in
# the documentation and/or other materials provided with the
# distribution.
# 3. Neither the name NuttX nor the names of its contributors may be
# used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
############################################################################
include ${TOPDIR}/.config
include ${TOPDIR}/tools/Config.mk
include ${TOPDIR}/arch/risc-v/src/rv32im/Toolchain.defs
LDSCRIPT = ld.script
ifeq ($(WINTOOL),y)
# Windows-native toolchains
DIRLINK = $(TOPDIR)/tools/copydir.sh
DIRUNLINK = $(TOPDIR)/tools/unlink.sh
MKDEP = $(TOPDIR)/tools/mkwindeps.sh
ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}"
ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}"
else
# Linux/Cygwin-native toolchain
MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT)
ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)
endif
CC = $(CROSSDEV)gcc
CXX = $(CROSSDEV)g++
CPP = $(CROSSDEV)gcc -E
LD = $(CROSSDEV)ld
STRIP = $(CROSSDEV)strip --strip-unneeded
AR = $(ARCROSSDEV)ar rcs
NM = $(ARCROSSDEV)nm
OBJCOPY = $(CROSSDEV)objcopy
OBJDUMP = $(CROSSDEV)objdump
ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'}
ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1}
ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
ARCHOPTIMIZATION = -g
ASARCHCPUFLAGS += -Wa,-g
endif
ifneq ($(CONFIG_DEBUG_NOOPT),y)
ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer
endif
ARCHCFLAGS = -fno-builtin
ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti
ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef
ARCHWARNINGSXX = -Wall -Wshadow -Wundef
ARCHDEFINES =
ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES)
AFLAGS += $(CFLAGS) -D__ASSEMBLY__ $(ASARCHCPUFLAGS)
NXFLATLDFLAGS1 = -r -d -warn-common
NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
LDNXFLATFLAGS = -e main -s 2048
ASMEXT = .S
OBJEXT = .o
LIBEXT = .a
EXEEXT =
ifneq ($(CROSSDEV),arm-nuttx-elf-)
LDFLAGS += -nostartfiles -nodefaultlibs -melf32lriscv
endif
ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
LDFLAGS += -g -melf32lriscv
endif
HOSTCC = gcc
HOSTINCLUDES = -I.
HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe
HOSTLDFLAGS =

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/****************************************************************************
* configs/gapduino/scripts/ld.script
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: hhuysqt <1020988872@qq.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* Not needed, but we need separate linker scripts anyway */
OUTPUT_ARCH(riscv)
SEARCH_DIR(.)
__DYNAMIC = 0;
MEMORY
{
L2 : ORIGIN = 0x1C000000, LENGTH = 0x80000
FC_tcdm : ORIGIN = 0x1B000004, LENGTH = 0x3ffc
FC_tcdm_aliased : ORIGIN = 0x00000004, LENGTH = 0x3ffc
}
__L1_STACK_SIZE = 0x400;
__FC_STACK_SIZE = 0x1000;
/* We have to align each sector to word boundaries as our current s19->slm
* conversion scripts are not able to handle non-word aligned sections.
*/
SECTIONS
{
.vectors_M :
{
. = ALIGN(4);
IRQ_U_Vector_Base = .;
KEEP(*(.vectors_M))
} > L2
.dbg_struct :
{
. = ALIGN(4);
IRQ_M_Vector_Base = .;
KEEP(*(.dbg_struct))
} > L2
.text : {
. = ALIGN(4);
_stext = .;
*(.text.reset)
*(.text)
*(.text.*)
_etext = .;
*(.lit)
*(.shdata)
_endtext = .;
} > L2
.ctors :
{
. = ALIGN(4);
__CTOR_LIST__ = .;
/* gcc uses crtbegin.o to find the start of
* the constructors, so we make sure it is
* first. Because this is a wildcard, it
* doesn't matter if the user does not
* actually link against crtbegin.o; the
* linker won't look for a file to match a
* wildcard. The wildcard also means that it
* doesn't matter which directory crtbegin.o
* is in.
*/
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
* from the crtend.o file until after the sorted ctors.
* The .ctor section from the crtend file contains the
* end of ctors marker and it must be last
*/
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__CTOR_END__ = .;
} > L2
.dtors : {
. = ALIGN(4);
__DTOR_LIST__ = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
__DTOR_END__ = .;
} > L2
/*--------------------------------------------------------------------*/
/* Global constructor/destructor segement */
/*--------------------------------------------------------------------*/
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} > L2
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} > L2
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} > L2
.rodata : {
/* Due to limitations on FPGA loader, loadable sections must have
* base and size aligned on 4 bytes
*/
. = ALIGN(4);
*(.rodata);
*(.rodata.*)
. = ALIGN(4);
} > L2
.gnu.offload_funcs :
/* GCC Offload table of offloaded functions and variables */
{
. = ALIGN(4);
KEEP(*(.gnu.offload_funcs))
} > L2
.gnu.offload_vars :
{
. = ALIGN(4);
KEEP(*(.gnu.offload_vars))
} > L2
.data : {
. = ALIGN(4);
__DATA_RAM = .;
__data_start__ = .; /* create a global symbol at data start */
*(.data);
*(.data.*)
KEEP(*(.jcr*))
. = ALIGN(4);
__data_end__ = .; /* define a global symbol at data end */
} > L2
.bss :
{
. = ALIGN(4);
_sbss = .;
__bss_start__ = .;
*(.bss)
*(.bss.*)
*(.sbss)
*(.sbss.*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
_ebss = .;
} > L2
/* Heap would exhaust the L2 RAM */
_heap_start = .;
_heap_end = ORIGIN(L2) + LENGTH(L2);
/* Idle stack is on FC tdcm */
_idle_stack_start = ORIGIN(FC_tcdm);
_idle_stack_end = ORIGIN(FC_tcdm) + LENGTH(FC_tcdm);
.stab 0 (NOLOAD) :
{
[ .stab ]
}
.stabstr 0 (NOLOAD) :
{
[ .stabstr ]
}
}

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-include $(TOPDIR)/Make.defs
ASRCS =
AOBJS = $(ASRCS:.S=$(OBJEXT))
CSRCS = gapuino_appinit.c gapuino_sysinit.c
COBJS = $(CSRCS:.c=$(OBJEXT))
SRCS = $(ASRCS) $(CSRCS)
OBJS = $(AOBJS) $(COBJS)
ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src
ifeq ($(CONFIG_WINDOWS_NATIVE),y)
CFLAGS += -I$(ARCH_SRCDIR) -I$(ARCH_SRCDIR)\common -I$(ARCH_SRCDIR)\rv32im
else
ifeq ($(WINTOOL),y)
CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}" \
-I "${shell cygpath -w $(ARCH_SRCDIR)/common}"
else
CFLAGS += -I$(ARCH_SRCDIR)/$(CONFIG_ARCH_CHIP) -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/rv32im
endif
endif
all: libboard$(LIBEXT)
$(AOBJS): %$(OBJEXT): %.S
$(call ASSEMBLE, $<, $@)
$(COBJS) $(LINKOBJS): %$(OBJEXT): %.c
$(call COMPILE, $<, $@)
libboard$(LIBEXT): $(OBJS)
$(call ARCHIVE, $@, $(OBJS))
.depend: Makefile $(SRCS)
$(Q) $(MKDEP) $(CC) -- $(CFLAGS) -- $(SRCS) >Make.dep
$(Q) touch $@
depend: .depend
clean:
$(call DELFILE, libboard$(LIBEXT))
$(call CLEAN)
distclean: clean
$(call DELFILE, Make.dep)
$(call DELFILE, .depend)
-include Make.dep

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/****************************************************************************
* configs/gapduino/src/gapduino_appinit.c
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: hhuysqt <1020988872@qq.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/mount.h>
#include <stdbool.h>
#include <stdio.h>
#include <syslog.h>
#include <errno.h>
#include <nuttx/board.h>
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: board_app_initialize
*
* Description:
* Perform architecture specific initialization
*
* Input Parameters:
* arg - The boardctl() argument is passed to the board_app_initialize()
* implementation without modification. The argument has no
* meaning to NuttX; the meaning of the argument is a contract
* between the board-specific initalization logic and the
* matching application logic. The value cold be such things as a
* mode enumeration value, a set of DIP switch switch settings, a
* pointer to configuration data read from a file or serial FLASH,
* or whatever you would like to do with it. Every implementation
* should accept zero/NULL as a default configuration.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned on
* any failure to indicate the nature of the failure.
*
****************************************************************************/
int board_app_initialize(uintptr_t arg)
{
int ret = OK;
#ifdef CONFIG_FS_PROCFS
/* Mount the proc filesystem */
ret = mount(NULL, CONFIG_NSH_PROC_MOUNTPOINT, "procfs", 0, NULL);
if (ret < 0)
{
syslog(LOG_ERR,
"ERROR: Failed to mount the PROC filesystem: %d (%d)\n",
ret, errno);
return ret;
}
#endif
return ret;
}

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/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <stdio.h>
#include <syslog.h>
#include <errno.h>
#include "chip.h"
#include "gap8_fll.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Types
****************************************************************************/
/* Used to communicate with plpbridge */
struct _debug_struct
{
/* Used by external debug bridge to get exit status when using the board */
uint32_t exitStatus;
/* Printf */
uint32_t useInternalPrintf;
uint32_t putcharPending;
uint32_t putcharCurrent;
uint8_t putcharBuffer[128];
/* Debug step, used for showing progress to host loader */
uint32_t debugStep;
uint32_t debugStepPending;
/* Requests */
uint32_t firstReq;
uint32_t lastReq;
uint32_t firstBridgeReq;
uint32_t notifReqAddr;
uint32_t notifReqValue;
uint32_t bridgeConnected;
};
/****************************************************************************
* Private Data
****************************************************************************/
/* Place a dummy debug struct */
struct _debug_struct Debug_Struct =
{
.useInternalPrintf = 1,
};
uint32_t g_current_freq = 0;
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: gapuino_sysinit
*
* Description:
* Initialize cache, clock, etc.
*
****************************************************************************/
void gapuino_sysinit(void)
{
SCBC->ICACHE_ENABLE = 0xFFFFFFFF;
gap8_setfreq(CONFIG_CORE_CLOCK_FREQ);
/* For debug usage */
g_current_freq = gap8_getfreq();
}