S32K1xx arch: Add (optional) support for SPI native/hardware chip select
This commit is contained in:
Jari van Ewijk
Xiang Xiao
parent
0a1b3c1331
commit
e4752fbaee
@ -624,6 +624,10 @@ menu "LPSPI Configuration"
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config S32K1XX_LPSPI_DWORD
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bool "DWORD up to 64 bit transfer support"
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default n
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config S32K1XX_LPSPI_HWPCS
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bool "Use native hardware peripheral chip selects instead of GPIO pins"
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default n
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endmenu # LPSPI Configuration
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@ -299,6 +299,7 @@
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# define LPSPI_TCR_MSBF (0 << 23) /* MSB First */
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#define LPSPI_TCR_PCS_SHIFT (24) /* Bits 24-25: Peripheral Chip Select */
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#define LPSPI_TCR_PCS_MASK (3 << LPSPI_TCR_PCS_SHIFT)
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# define LPSPI_TCR_PCS(n) (((n) << LPSPI_TCR_PCS_SHIFT) & LPSPI_TCR_PCS_MASK)
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# define LPSPI_TCR_PCS_0 (0 << LPSPI_TCR_PCS_SHIFT) /* Transfer using LPSPI_PCS[0] */
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# define LPSPI_TCR_PCS_1 (1 << LPSPI_TCR_PCS_SHIFT) /* Transfer using LPSPI_PCS[1] */
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# define LPSPI_TCR_PCS_2 (2 << LPSPI_TCR_PCS_SHIFT) /* Transfer using LPSPI_PCS[2] */
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@ -19,19 +19,19 @@
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****************************************************************************/
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/****************************************************************************
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* The external functions, s32k1xx_lpspi0/1/2select and
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* s32k1xx_lpspi0/1/2status must be provided by board-specific logic. They
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* are implementations of the select and status methods of the SPI interface
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* defined by struct s32k1xx_lpspi_ops_s (see include/nuttx/spi/spi.h).
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* All other methods (including s32k1xx_lpspibus_initialize()) are provided
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* by common S32K1XX logic. To use this common SPI logic on your board:
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* The external functions, s32k1xx_lpspiNselect* and s32k1xx_lpspiNstatus
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* must be provided by board-specific logic. They are implementations of the
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* select and status methods of the SPI interface defined by struct
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* s32k1xx_lpspi_ops_s (see include/nuttx/spi/spi.h). All other methods
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* (including s32k1xx_lpspibus_initialize()) are provided by common S32K1XX
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* logic. To use this common SPI logic on your board:
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*
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* 1. Provide logic in s32k1xx_boardinitialize() to configure SPI chip
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* select pins.
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* 2. Provide s32k1xx_lpspi0/1/2select() and s32k1xx_lpspi0/1/2status()
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* functions in your board-specific logic. These functions will perform
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* chip selection and status operations using GPIOs in the way your
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* board is configured.
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* 2. Provide s32k1xx_lpspiNselect() and s32k1xx_lpspiNstatus() functions
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* in your board-specific logic. These functions will perform chip
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* selection and status operations using GPIOs in the way your board is
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* configured.
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* 3. Add a calls to s32k1xx_lpspibus_initialize() in your low level
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* application initialization logic
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* 4. The handle returned by s32k1xx_lpspibus_initialize() may then be
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@ -39,6 +39,12 @@
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* mmcsd_lpspislotinitialize(), for example, will bind the SPI driver
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* to the SPI MMC/SD driver).
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*
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* NOTE*: If CONFIG_S32K1XX_LPSPI_HWPCS is selected, s32k1xx_lpspiNselect()
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* does NOT need to provided by board-specific logic. In this case a
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* generic implementation is used that switches between native
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* hardware chip select pins. It is important that all pins are
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* configured when the SPI bus is initialized.
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*
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****************************************************************************/
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/****************************************************************************
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@ -135,6 +141,9 @@ struct s32k1xx_lpspidev_s
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uint32_t actual; /* Actual clock frequency */
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int8_t nbits; /* Width of word in bits */
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uint8_t mode; /* Mode 0,1,2,3 */
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#ifdef CONFIG_S32K1XX_LPSPI_HWPCS
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uint32_t pcs; /* Peripheral Chip Select currently used */
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#endif
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};
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enum s32k1xx_delay_e
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@ -176,6 +185,10 @@ void s32k1xx_lpspi_set_delay_scaler(FAR struct s32k1xx_lpspidev_s *priv,
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/* SPI methods */
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static int s32k1xx_lpspi_lock(FAR struct spi_dev_s *dev, bool lock);
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#ifdef CONFIG_S32K1XX_LPSPI_HWPCS
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static void s32k1xx_lpspi_select(FAR struct spi_dev_s *dev, uint32_t devid,
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bool selected);
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#endif
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static uint32_t s32k1xx_lpspi_setfrequency(FAR struct spi_dev_s *dev,
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uint32_t frequency);
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static void s32k1xx_lpspi_setmode(FAR struct spi_dev_s *dev,
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@ -216,7 +229,11 @@ s32k1xx_lpspi_bus_initialize(FAR struct s32k1xx_lpspidev_s *priv);
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static const struct spi_ops_s g_spi0ops =
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{
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.lock = s32k1xx_lpspi_lock,
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#ifdef CONFIG_S32K1XX_LPSPI_HWPCS
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.select = s32k1xx_lpspi_select,
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#else
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.select = s32k1xx_lpspi0select,
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#endif
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.setfrequency = s32k1xx_lpspi_setfrequency,
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.setmode = s32k1xx_lpspi_setmode,
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.setbits = s32k1xx_lpspi_setbits,
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@ -262,7 +279,11 @@ static struct s32k1xx_lpspidev_s g_lpspi0dev =
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static const struct spi_ops_s g_spi1ops =
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{
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.lock = s32k1xx_lpspi_lock,
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#ifdef CONFIG_S32K1XX_LPSPI_HWPCS
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.select = s32k1xx_lpspi_select,
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#else
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.select = s32k1xx_lpspi1select,
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#endif
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.setfrequency = s32k1xx_lpspi_setfrequency,
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.setmode = s32k1xx_lpspi_setmode,
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.setbits = s32k1xx_lpspi_setbits,
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@ -308,7 +329,11 @@ static struct s32k1xx_lpspidev_s g_lpspi1dev =
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static const struct spi_ops_s g_spi2ops =
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{
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.lock = s32k1xx_lpspi_lock,
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#ifdef CONFIG_S32K1XX_LPSPI_HWPCS
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.select = s32k1xx_lpspi_select,
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#else
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.select = s32k1xx_lpspi2select,
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#endif
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.setfrequency = s32k1xx_lpspi_setfrequency,
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.setmode = s32k1xx_lpspi_setmode,
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.setbits = s32k1xx_lpspi_setbits,
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@ -944,6 +969,48 @@ static int s32k1xx_lpspi_lock(FAR struct spi_dev_s *dev, bool lock)
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return ret;
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}
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#ifdef CONFIG_S32K1XX_LPSPI_HWPCS
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/****************************************************************************
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* Name: s32k1xx_lpspi_select
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*
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* Description:
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* Change to another SPI chip select (hardware/native, not emulated with
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* GPIO) to select another device. The hardware itself controls when
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* the chip select is enabled or disabled.
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*
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* Input Parameters:
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* dev - Device-specific state data
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* devid - Identifies the device to select
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* selected - Ignored, selection is controlled by hardware
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static void s32k1xx_lpspi_select(FAR struct spi_dev_s *dev, uint32_t devid,
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bool selected)
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{
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FAR struct s32k1xx_lpspidev_s *priv = (FAR struct s32k1xx_lpspidev_s *)dev;
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/* LPSPI on S32K1XX supports PCS 0-3 */
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DEBUGASSERT(SPIDEVID_INDEX(devid) <= 3);
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/* Has the Peripheral Chip Select changed? */
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if (devid != priv->pcs)
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{
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s32k1xx_lpspi_modifyreg32(priv, S32K1XX_LPSPI_TCR_OFFSET,
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LPSPI_TCR_PCS_MASK,
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LPSPI_TCR_PCS(SPIDEVID_INDEX(devid)));
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priv->pcs = devid;
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}
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spiinfo("devid: %" PRId32 ", CS: hardware-controlled\n", devid);
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}
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#endif /* CONFIG_S32K1XX_LPSPI HWPCS */
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/****************************************************************************
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* Name: s32k1xx_lpspi_setfrequency
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*
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@ -1071,7 +1138,7 @@ static uint32_t s32k1xx_lpspi_setfrequency(FAR struct spi_dev_s *dev,
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* mode - The SPI mode requested
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*
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* Returned Value:
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* Returns the actual frequency selected
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* none
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*
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****************************************************************************/
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