diff --git a/arch/risc-v/src/bl602/Make.defs b/arch/risc-v/src/bl602/Make.defs index 4196ba7d8c..b3a2b284dd 100644 --- a/arch/risc-v/src/bl602/Make.defs +++ b/arch/risc-v/src/bl602/Make.defs @@ -20,21 +20,21 @@ # Specify our HEAD assembly file. This will be linked as # the first object file, so it will appear at address 0 -HEAD_ASRC = bl602_vectors.S +HEAD_ASRC = bl602_entry.S # Specify our general Assembly files -CHIP_ASRCS = bl602_head.S bl602_entry.S +CHIP_ASRCS = bl602_head.S -CMN_ASRCS += riscv_testset.S +CMN_ASRCS += riscv_vectors.S riscv_testset.S # Specify C code within the common directory to be included -CMN_CSRCS += riscv_initialize.c riscv_swint.c -CMN_CSRCS += riscv_createstack.c riscv_exit.c -CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c -CMN_CSRCS += riscv_interruptcontext.c riscv_modifyreg32.c riscv_puts.c riscv_mdelay.c -CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c riscv_copyfullstate.c -CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c -CMN_CSRCS += riscv_sigdeliver.c riscv_udelay.c riscv_unblocktask.c riscv_usestack.c +CMN_CSRCS += riscv_initialize.c riscv_swint.c +CMN_CSRCS += riscv_createstack.c riscv_exit.c +CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c +CMN_CSRCS += riscv_interruptcontext.c riscv_modifyreg32.c riscv_puts.c riscv_mdelay.c +CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c riscv_copyfullstate.c +CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c +CMN_CSRCS += riscv_sigdeliver.c riscv_udelay.c riscv_unblocktask.c riscv_usestack.c ifeq ($(CONFIG_SCHED_BACKTRACE),y) CMN_CSRCS += riscv_backtrace.c diff --git a/arch/risc-v/src/bl602/bl602_vectors.S b/arch/risc-v/src/bl602/bl602_vectors.S deleted file mode 100644 index 2c09068533..0000000000 --- a/arch/risc-v/src/bl602/bl602_vectors.S +++ /dev/null @@ -1,42 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/bl602/bl602_vectors.S - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/************************************************************************************ - * Included Files - ************************************************************************************/ - - .section .init - .global __reset_vec - .global __trap_vec - -/**************************************************************************** - * Name: __reset_vec - ****************************************************************************/ - -__reset_vec: - jal __start - -/**************************************************************************** - * Name: exception_common - ****************************************************************************/ - -__trap_vec: - j exception_common - nop diff --git a/arch/risc-v/src/c906/Make.defs b/arch/risc-v/src/c906/Make.defs index 421392baf1..bd93b6041d 100644 --- a/arch/risc-v/src/c906/Make.defs +++ b/arch/risc-v/src/c906/Make.defs @@ -20,22 +20,20 @@ # Specify our HEAD assembly file. This will be linked as # the first object file, so it will appear at address 0 -HEAD_ASRC = c906_vectors.S +HEAD_ASRC = c906_head.S # Specify our general Assembly files -CHIP_ASRCS = c906_head.S - -CMN_ASRCS += riscv_testset.S +CMN_ASRCS += riscv_vectors.S riscv_testset.S # Specify C code within the common directory to be included -CMN_CSRCS += riscv_initialize.c riscv_swint.c -CMN_CSRCS += riscv_createstack.c riscv_exit.c riscv_fault.c -CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c -CMN_CSRCS += riscv_interruptcontext.c riscv_modifyreg32.c riscv_puts.c -CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c -CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c -CMN_CSRCS += riscv_sigdeliver.c riscv_unblocktask.c riscv_usestack.c -CMN_CSRCS += riscv_mdelay.c riscv_copyfullstate.c +CMN_CSRCS += riscv_initialize.c riscv_swint.c +CMN_CSRCS += riscv_createstack.c riscv_exit.c riscv_fault.c +CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c +CMN_CSRCS += riscv_interruptcontext.c riscv_modifyreg32.c riscv_puts.c +CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c +CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c +CMN_CSRCS += riscv_sigdeliver.c riscv_unblocktask.c riscv_usestack.c +CMN_CSRCS += riscv_mdelay.c riscv_copyfullstate.c ifeq ($(CONFIG_SCHED_BACKTRACE),y) CMN_CSRCS += riscv_backtrace.c diff --git a/arch/risc-v/src/c906/c906_vectors.S b/arch/risc-v/src/c906/c906_vectors.S deleted file mode 100644 index 724717a88d..0000000000 --- a/arch/risc-v/src/c906/c906_vectors.S +++ /dev/null @@ -1,46 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/c906/c906_vectors.S - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - - .section .text.vec - .global __reset_vec - .global __trap_vec - -/**************************************************************************** - * Name: __reset_vec - ****************************************************************************/ - -__reset_vec: - jal __start - -/**************************************************************************** - * Name: exception_common - * - * Description: - * All exceptions and interrupts will be handled from here. - * - ****************************************************************************/ - -__trap_vec: - j exception_common - nop diff --git a/arch/risc-v/src/qemu-rv32/qemu_rv32_vectors.S b/arch/risc-v/src/common/riscv_vectors.S similarity index 95% rename from arch/risc-v/src/qemu-rv32/qemu_rv32_vectors.S rename to arch/risc-v/src/common/riscv_vectors.S index 27fb8ac3bc..f44b706f55 100644 --- a/arch/risc-v/src/qemu-rv32/qemu_rv32_vectors.S +++ b/arch/risc-v/src/common/riscv_vectors.S @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/fe310/fe310_vectors.S + * arch/risc-v/src/common/riscv_vectors.S * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -22,7 +22,7 @@ * Included Files ****************************************************************************/ - .section .text.vec + .section .text .global __trap_vec /**************************************************************************** diff --git a/arch/risc-v/src/fe310/Make.defs b/arch/risc-v/src/fe310/Make.defs index 241bccee81..9bb3eed3e3 100644 --- a/arch/risc-v/src/fe310/Make.defs +++ b/arch/risc-v/src/fe310/Make.defs @@ -20,21 +20,19 @@ # Specify our HEAD assembly file. This will be linked as # the first object file, so it will appear at address 0 -HEAD_ASRC = fe310_vectors.S +HEAD_ASRC = fe310_head.S # Specify our general Assembly files -CHIP_ASRCS = fe310_head.S - -CMN_ASRCS += riscv_testset.S +CMN_ASRCS += riscv_vectors.S riscv_testset.S # Specify C code within the common directory to be included -CMN_CSRCS += riscv_initialize.c riscv_swint.c -CMN_CSRCS += riscv_allocateheap.c riscv_createstack.c riscv_exit.c -CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c -CMN_CSRCS += riscv_interruptcontext.c riscv_modifyreg32.c riscv_puts.c riscv_mdelay.c -CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c riscv_copyfullstate.c -CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c -CMN_CSRCS += riscv_sigdeliver.c riscv_udelay.c riscv_unblocktask.c riscv_usestack.c +CMN_CSRCS += riscv_initialize.c riscv_swint.c +CMN_CSRCS += riscv_allocateheap.c riscv_createstack.c riscv_exit.c +CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c +CMN_CSRCS += riscv_interruptcontext.c riscv_modifyreg32.c riscv_puts.c riscv_mdelay.c +CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c riscv_copyfullstate.c +CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c +CMN_CSRCS += riscv_sigdeliver.c riscv_udelay.c riscv_unblocktask.c riscv_usestack.c ifeq ($(CONFIG_SCHED_BACKTRACE),y) CMN_CSRCS += riscv_backtrace.c @@ -45,7 +43,7 @@ CMN_CSRCS += riscv_checkstack.c endif ifeq ($(CONFIG_ARCH_HAVE_VFORK),y) -CMN_CSRCS += riscv_vfork.c +CMN_CSRCS += riscv_vfork.c endif # Specify our C code within this directory to be included diff --git a/arch/risc-v/src/fe310/fe310_vectors.S b/arch/risc-v/src/fe310/fe310_vectors.S deleted file mode 100644 index 1b57ae29d4..0000000000 --- a/arch/risc-v/src/fe310/fe310_vectors.S +++ /dev/null @@ -1,42 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/fe310/fe310_vectors.S - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - - .section .text.vec - .global __reset_vec - .global __trap_vec - -/**************************************************************************** - * Name: __reset_vec - ****************************************************************************/ - -__reset_vec: - jal __start - -/**************************************************************************** - * Name: exception_common - ****************************************************************************/ - -__trap_vec: - j exception_common - nop diff --git a/arch/risc-v/src/k210/Make.defs b/arch/risc-v/src/k210/Make.defs index 4f69c5291a..9fe6d700d0 100644 --- a/arch/risc-v/src/k210/Make.defs +++ b/arch/risc-v/src/k210/Make.defs @@ -20,22 +20,20 @@ # Specify our HEAD assembly file. This will be linked as # the first object file, so it will appear at address 0 -HEAD_ASRC = k210_vectors.S +HEAD_ASRC = k210_head.S # Specify our general Assembly files -CHIP_ASRCS = k210_head.S - -CMN_ASRCS += riscv_testset.S +CMN_ASRCS += riscv_vectors.S riscv_testset.S # Specify C code within the common directory to be included -CMN_CSRCS += riscv_initialize.c riscv_swint.c -CMN_CSRCS += riscv_createstack.c riscv_exit.c riscv_fault.c -CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c -CMN_CSRCS += riscv_interruptcontext.c riscv_modifyreg32.c riscv_puts.c -CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c -CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c -CMN_CSRCS += riscv_sigdeliver.c riscv_unblocktask.c riscv_usestack.c -CMN_CSRCS += riscv_mdelay.c riscv_copyfullstate.c +CMN_CSRCS += riscv_initialize.c riscv_swint.c +CMN_CSRCS += riscv_createstack.c riscv_exit.c riscv_fault.c +CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c +CMN_CSRCS += riscv_interruptcontext.c riscv_modifyreg32.c riscv_puts.c +CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c +CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c +CMN_CSRCS += riscv_sigdeliver.c riscv_unblocktask.c riscv_usestack.c +CMN_CSRCS += riscv_mdelay.c riscv_copyfullstate.c ifeq ($(CONFIG_SCHED_BACKTRACE),y) CMN_CSRCS += riscv_backtrace.c @@ -46,7 +44,7 @@ CMN_CSRCS += riscv_checkstack.c endif ifeq ($(CONFIG_ARCH_HAVE_VFORK),y) -CMN_CSRCS += riscv_vfork.c +CMN_CSRCS += riscv_vfork.c endif # Specify our C code within this directory to be included diff --git a/arch/risc-v/src/k210/k210_vectors.S b/arch/risc-v/src/k210/k210_vectors.S deleted file mode 100644 index abc4784ebb..0000000000 --- a/arch/risc-v/src/k210/k210_vectors.S +++ /dev/null @@ -1,42 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/k210/k210_vectors.S - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - - .section .text.vec - .global __reset_vec - .global __trap_vec - -/**************************************************************************** - * Name: __reset_vec - ****************************************************************************/ - -__reset_vec: - jal __start - -/**************************************************************************** - * Name: exception_common - ****************************************************************************/ - -__trap_vec: - j exception_common - nop diff --git a/arch/risc-v/src/litex/Make.defs b/arch/risc-v/src/litex/Make.defs index 05eb9aedcd..65307e84e7 100644 --- a/arch/risc-v/src/litex/Make.defs +++ b/arch/risc-v/src/litex/Make.defs @@ -20,21 +20,19 @@ # Specify our HEAD assembly file. This will be linked as # the first object file, so it will appear at address 0 -HEAD_ASRC = litex_vectors.S +HEAD_ASRC = litex_head.S # Specify our general Assembly files -CHIP_ASRCS = litex_head.S - -CMN_ASRCS += riscv_testset.S +CMN_ASRCS += riscv_vectors.S riscv_testset.S # Specify C code within the common directory to be included -CMN_CSRCS += riscv_initialize.c riscv_swint.c -CMN_CSRCS += riscv_allocateheap.c riscv_createstack.c riscv_exit.c -CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c -CMN_CSRCS += riscv_interruptcontext.c riscv_modifyreg32.c riscv_puts.c riscv_mdelay.c -CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c riscv_copyfullstate.c -CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c -CMN_CSRCS += riscv_sigdeliver.c riscv_udelay.c riscv_unblocktask.c riscv_usestack.c +CMN_CSRCS += riscv_initialize.c riscv_swint.c +CMN_CSRCS += riscv_allocateheap.c riscv_createstack.c riscv_exit.c +CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c +CMN_CSRCS += riscv_interruptcontext.c riscv_modifyreg32.c riscv_puts.c riscv_mdelay.c +CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c riscv_copyfullstate.c +CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c +CMN_CSRCS += riscv_sigdeliver.c riscv_udelay.c riscv_unblocktask.c riscv_usestack.c ifeq ($(CONFIG_SCHED_BACKTRACE),y) CMN_CSRCS += riscv_backtrace.c diff --git a/arch/risc-v/src/litex/litex_vectors.S b/arch/risc-v/src/litex/litex_vectors.S deleted file mode 100644 index da77137632..0000000000 --- a/arch/risc-v/src/litex/litex_vectors.S +++ /dev/null @@ -1,42 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/litex/litex_vectors.S - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/************************************************************************************ - * Included Files - ************************************************************************************/ - - .section .text.vec - .global __reset_vec - .global __trap_vec - -/**************************************************************************** - * Name: __reset_vec - ****************************************************************************/ - -__reset_vec: - jal __start - -/**************************************************************************** - * Name: exception_common - ****************************************************************************/ - -__trap_vec: - j exception_common - nop diff --git a/arch/risc-v/src/mpfs/Make.defs b/arch/risc-v/src/mpfs/Make.defs index 2f4be0882c..3824facb29 100755 --- a/arch/risc-v/src/mpfs/Make.defs +++ b/arch/risc-v/src/mpfs/Make.defs @@ -20,22 +20,21 @@ # Specify our HEAD assembly file. This will be linked as # the first object file, so it will appear at address 0 -HEAD_ASRC = mpfs_vectors.S +HEAD_ASRC = mpfs_head.S # Specify our general Assembly files -CHIP_ASRCS = mpfs_head.S -CMN_ASRCS += riscv_testset.S +CMN_ASRCS += riscv_vectors.S riscv_testset.S # Specify C code within the common directory to be included -CMN_CSRCS += riscv_initialize.c riscv_swint.c -CMN_CSRCS += riscv_createstack.c riscv_exit.c riscv_fault.c -CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c -CMN_CSRCS += riscv_interruptcontext.c riscv_modifyreg32.c riscv_puts.c -CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c -CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c -CMN_CSRCS += riscv_sigdeliver.c riscv_unblocktask.c riscv_usestack.c -CMN_CSRCS += riscv_mdelay.c riscv_udelay.c riscv_copyfullstate.c +CMN_CSRCS += riscv_initialize.c riscv_swint.c +CMN_CSRCS += riscv_createstack.c riscv_exit.c riscv_fault.c +CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c +CMN_CSRCS += riscv_interruptcontext.c riscv_modifyreg32.c riscv_puts.c +CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c +CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c +CMN_CSRCS += riscv_sigdeliver.c riscv_unblocktask.c riscv_usestack.c +CMN_CSRCS += riscv_mdelay.c riscv_udelay.c riscv_copyfullstate.c ifeq ($(CONFIG_SCHED_BACKTRACE),y) CMN_CSRCS += riscv_backtrace.c @@ -46,11 +45,11 @@ CMN_CSRCS += riscv_checkstack.c endif ifeq ($(CONFIG_ARCH_FPU),y) -CMN_ASRCS += riscv_fpu.S +CMN_ASRCS += riscv_fpu.S endif ifeq ($(CONFIG_ARCH_HAVE_VFORK),y) -CMN_CSRCS += riscv_vfork.c +CMN_CSRCS += riscv_vfork.c endif # Specify our C code within this directory to be included @@ -61,7 +60,7 @@ CHIP_CSRCS += mpfs_start.c mpfs_timerisr.c CHIP_CSRCS += mpfs_gpio.c mpfs_systemreset.c ifeq ($(CONFIG_MPFS_DMA),y) -CHIP_CSRCS += mpfs_dma.c +CHIP_CSRCS += mpfs_dma.c endif ifeq ($(CONFIG_BUILD_PROTECTED),y) diff --git a/arch/risc-v/src/mpfs/mpfs_head.S b/arch/risc-v/src/mpfs/mpfs_head.S index 0a0ef0cb17..61516316ac 100755 --- a/arch/risc-v/src/mpfs/mpfs_head.S +++ b/arch/risc-v/src/mpfs/mpfs_head.S @@ -41,9 +41,9 @@ .extern __trap_vec .section .text - .global __start_mpfs + .global __start -__start_mpfs: +__start: /* Disable all interrupts (i.e. timer, external) in mie */ diff --git a/arch/risc-v/src/mpfs/mpfs_vectors.S b/arch/risc-v/src/mpfs/mpfs_vectors.S deleted file mode 100755 index 94a7173fc6..0000000000 --- a/arch/risc-v/src/mpfs/mpfs_vectors.S +++ /dev/null @@ -1,53 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/mpfs/mpfs_vectors.S - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - - .section .text.vec - .global __reset_vec - .global __trap_vec - .global __start - -/**************************************************************************** - * Name: __reset_vec - * - * Description: - * Also __start symbol is defined to be on start of image. This is expected - * by some of Microchip tools, which can be used to e.g. flash the image - * - ****************************************************************************/ - -__start: -__reset_vec: - j __start_mpfs - -/**************************************************************************** - * Name: exception_common - * - * Description: - * All exceptions and interrupts will be handled from here. - * - ****************************************************************************/ - -__trap_vec: - j exception_common - nop diff --git a/arch/risc-v/src/qemu-rv32/Make.defs b/arch/risc-v/src/qemu-rv32/Make.defs index 23d53bd35c..f1626dd347 100644 --- a/arch/risc-v/src/qemu-rv32/Make.defs +++ b/arch/risc-v/src/qemu-rv32/Make.defs @@ -23,18 +23,16 @@ HEAD_ASRC = qemu_rv32_head.S # Specify our general Assembly files -CHIP_ASRCS = qemu_rv32_vectors.S - -CMN_ASRCS += riscv_testset.S +CMN_ASRCS += riscv_vectors.S riscv_testset.S # Specify C code within the common directory to be included -CMN_CSRCS += riscv_initialize.c riscv_swint.c -CMN_CSRCS += riscv_allocateheap.c riscv_createstack.c riscv_exit.c -CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c -CMN_CSRCS += riscv_interruptcontext.c riscv_modifyreg32.c riscv_puts.c -CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c riscv_copyfullstate.c -CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c -CMN_CSRCS += riscv_sigdeliver.c riscv_unblocktask.c riscv_usestack.c +CMN_CSRCS += riscv_initialize.c riscv_swint.c +CMN_CSRCS += riscv_allocateheap.c riscv_createstack.c riscv_exit.c +CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c +CMN_CSRCS += riscv_interruptcontext.c riscv_modifyreg32.c riscv_puts.c +CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c riscv_copyfullstate.c +CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c +CMN_CSRCS += riscv_sigdeliver.c riscv_unblocktask.c riscv_usestack.c ifeq ($(CONFIG_SCHED_BACKTRACE),y) CMN_CSRCS += riscv_backtrace.c diff --git a/arch/risc-v/src/rv32m1/Make.defs b/arch/risc-v/src/rv32m1/Make.defs index e777e99142..d65ef333da 100644 --- a/arch/risc-v/src/rv32m1/Make.defs +++ b/arch/risc-v/src/rv32m1/Make.defs @@ -20,19 +20,19 @@ # Specify our HEAD assembly file. This will be linked as # the first object file, so it will appear at address 0 -HEAD_ASRC = rv32m1_vectors.S +HEAD_ASRC = rv32m1_head.S # Specify our general Assembly files -CHIP_ASRCS = rv32m1_head.S +CMN_ASRCS = riscv_vectors.S # Specify C code within the common directory to be included -CMN_CSRCS += riscv_initialize.c riscv_swint.c -CMN_CSRCS += riscv_allocateheap.c riscv_createstack.c riscv_exit.c -CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c -CMN_CSRCS += riscv_interruptcontext.c riscv_modifyreg32.c riscv_puts.c -CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c riscv_copyfullstate.c -CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c -CMN_CSRCS += riscv_sigdeliver.c riscv_unblocktask.c riscv_usestack.c +CMN_CSRCS += riscv_initialize.c riscv_swint.c +CMN_CSRCS += riscv_allocateheap.c riscv_createstack.c riscv_exit.c +CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c +CMN_CSRCS += riscv_interruptcontext.c riscv_modifyreg32.c riscv_puts.c +CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c riscv_copyfullstate.c +CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c +CMN_CSRCS += riscv_sigdeliver.c riscv_unblocktask.c riscv_usestack.c ifeq ($(CONFIG_SCHED_BACKTRACE),y) CMN_CSRCS += riscv_backtrace.c @@ -43,7 +43,7 @@ CMN_CSRCS += riscv_checkstack.c endif ifeq ($(CONFIG_ARCH_HAVE_VFORK),y) -CMN_CSRCS += riscv_vfork.c +CMN_CSRCS += riscv_vfork.c endif # Specify our C code within this directory to be included