STM32F33: Add OPAMP support
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raiden00pl
parent
b688d41516
commit
e4d47d61cc
@ -221,6 +221,10 @@ ifeq ($(CONFIG_COMP),y)
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CHIP_CSRCS += stm32_comp.c
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endif
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ifeq ($(CONFIG_OPAMP),y)
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CHIP_CSRCS += stm32_opamp.c
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endif
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ifeq ($(CONFIG_STM32_1WIREDRIVER),y)
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CHIP_CSRCS += stm32_1wire.c
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endif
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@ -54,7 +54,7 @@
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/* Register Addresses *******************************************************************************/
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#define STM32_OPAMP2_CSR (STM32_OPAMP2_BASE+STM32_OPAMP2_CSR_OFFSET)
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#define STM32_OPAMP2_CSR (STM32_OPAMP_BASE+STM32_OPAMP2_CSR_OFFSET)
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/* Register Bitfield Definitions ****************************************************/
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@ -66,7 +66,7 @@
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#define OPAMP_CSR_VPSEL_SHIFT (3) /* Bits 2-3: OPAMP non inverting input selection */
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#define OPAMP_CSR_VPSEL_MASK (3 << OPAMP_CSR_VPSEL_SHIFT)
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/* 00: Reserved */
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# define OPAMP_CSR_VPSEL_PB13 (1 << OPAMP_CSR_VPSEL_SHIFT) /* 01: PB14 */
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# define OPAMP_CSR_VPSEL_PB14 (1 << OPAMP_CSR_VPSEL_SHIFT) /* 01: PB14 */
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# define OPAMP_CSR_VPSEL_PB0 (2 << OPAMP_CSR_VPSEL_SHIFT) /* 10: PB0 */
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# define OPAMP_CSR_VPSEL_PA7 (3 << OPAMP_CSR_VPSEL_SHIFT) /* 11: PA7 */
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/* Bit 4: Reserved */
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@ -74,7 +74,7 @@
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#define OPAMP_CSR_VMSEL_MASK (3 << OPAMP_CSR_VMSEL_SHIFT)
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# define OPAMP_CSR_VMSEL_PC5 (0 << OPAMP_CSR_VMSEL_SHIFT) /* 00: PC5 */
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# define OPAMP_CSR_VMSEL_PA5 (1 << OPAMP_CSR_VMSEL_SHIFT) /* 01: PA5 */
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# define OPAMP_CSR_VMSEL_RESISTOR (2 << OPAMP_CSR_VMSEL_SHIFT) /* 10: Resistor feedback output */
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# define OPAMP_CSR_VMSEL_PGA (2 << OPAMP_CSR_VMSEL_SHIFT) /* 10: Resistor feedback output (PGA mode)*/
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# define OPAMP_CSR_VMSEL_FOLLOWER (3 << OPAMP_CSR_VMSEL_SHIFT) /* 11: Follower mode */
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#define OPAMP_CSR_TCMEN (1 << 7) /* Bit 7: Timer controlled Mux mode enable */
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#define OPAMP_CSR_VMSSEL (1 << 8) /* Bit 8: OPAMP inverting input secondary selection */
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@ -337,9 +337,10 @@
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#define GPIO_OPAMP2_VINM_1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5)
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#define GPIO_OPAMP2_VINM_2 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN5)
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#define GPIO_OPAMP2_VOUT (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN6)
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#define GPIO_OPAMP2_VINP_1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN7)
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#define GPIO_OPAMP2_VINP_2 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0)
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#define GPIO_OPAMP2_VINP_3 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN14)
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#undef GPIO_OPAMP2_VINP_1 /* not supported in F33XX */
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#define GPIO_OPAMP2_VINP_2 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN7)
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#define GPIO_OPAMP2_VINP_3 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0)
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#define GPIO_OPAMP2_VINP_4 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN14)
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/* TSC */
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@ -69,6 +69,7 @@
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#include "stm32_gpio.h"
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#include "stm32_i2c.h"
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#include "stm32_ltdc.h"
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#include "stm32_opamp.h"
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#include "stm32_pwr.h"
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#include "stm32_rcc.h"
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#include "stm32_rtc.h"
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1418
arch/arm/src/stm32/stm32_opamp.c
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1418
arch/arm/src/stm32/stm32_opamp.c
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File diff suppressed because it is too large
Load Diff
231
arch/arm/src/stm32/stm32_opamp.h
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231
arch/arm/src/stm32/stm32_opamp.h
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@ -0,0 +1,231 @@
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/************************************************************************************
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* arch/arm/src/stm32/stm32_opamp.h
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*
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* Copyright (C) 2017 Gregory Nutt. All rights reserved.
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* Author: Mateusz Szafoni <raiden00@railab.me>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32_STM32_OPAMP_H
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#define __ARCH_ARM_SRC_STM32_STM32_OPAMP_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#ifdef CONFIG_STM32_OPAMP
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#if defined(CONFIG_STM32_STM32F30XX)
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# error "OPAMP support for STM32F30XX not implemented yet"
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#elif defined(CONFIG_STM32_STM32F33XX)
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# include "chip/stm32f33xxx_opamp.h"
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#endif
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#include <nuttx/analog/opamp.h>
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/************************************************************************************
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* Pre-processor definitions
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************************************************************************************/
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/* OPAMP operation mode */
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#define OPAMP_MODE_STANDALONE 0
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#define OPAMP_MODE_FOLLOWER 1
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#define OPAMP_MODE_PGA 2
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/* Timer controlled Mux mode */
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#define OPAMP_MUX_DISABLE 0
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#define OPAMP_MUX_ENABLE 1
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/* User callibration */
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#define OPAMP_USERCAL_DISABLE 0
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#define OPAMP_USERCAL_ENABLE 1
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/* Default configuration */
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#define OPAMP_MODE_DEFAULT OPAMP_MODE_STANDALONE /* Standalone mode */
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#define OPAMP_MUX_DEFAULT OPAMP_MUX_DISABLE /* MUX disabled */
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#define OPAMP_USERCAL_DEFAULT OPAMP_USERCAL_DISABLE /* User calibration disabled */
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#define OPAMP_GAIN_DEFAULT OPAMP_GAIN_2 /* Gain in PGA mode = 2 */
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#define OPAMP_LOCK_DEFAULT OPAMP_LOCK_RW /* Do not lock CSR register */
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/* CSR register lock state */
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enum stm32_opamp_lock_e
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{
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OPAMP_LOCK_RW,
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OPAMP_LOCK_RO
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};
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/* Gain in PGA mode */
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enum stm32_opamp_gain_e
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{
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OPAMP_GAIN_2,
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OPAMP_GAIN_4,
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OPAMP_GAIN_8,
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OPAMP_GAIN_2_VM0,
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OPAMP_GAIN_4_VM0,
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OPAMP_GAIN_8_VM0,
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OPAMP_GAIN_16_VM0,
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OPAMP_GAIN_2_VM1,
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OPAMP_GAIN_4_VM1,
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OPAMP_GAIN_8_VM1,
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OPAMP_GAIN_16_VM1
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};
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/* Input selection and secondary input selection use the same GPIOs */
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#ifdef CONFIG_STM32_OPAMP1
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enum stm32_opamp1_vpsel_e
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{
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OPAMP1_VPSEL_PA7,
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OPAMP1_VPSEL_PA5,
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OPAMP1_VPSEL_PA3,
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OPAMP1_VPSEL_PA1
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};
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enum stm32_opamp1_vmsel_e
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{
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OPAMP1_VMSEL_PC5,
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OPAMP1_VMSEL_PA3,
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OPAMP1_VMSEL_PGAMODE,
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OPAMP1_VMSEL_FOLLOWER,
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};
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#endif
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#ifdef CONFIG_STM32_OPAMP2
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enum stm32_opamp2_vpsel_e
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{
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#ifndef CONFIG_STM32_STM32F33XX
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/* TODO: STM32F303xB/C and STM32F358C devices only */
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OPAMP2_VPSEL_PD14,
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#endif
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OPAMP2_VPSEL_PB14,
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OPAMP2_VPSEL_PB0,
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OPAMP2_VPSEL_PA7
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};
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enum stm32_opamp2_vmsel_e
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{
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OPAMP2_VMSEL_PC5,
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OPAMP2_VMSEL_PA5,
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OPAMP2_VMSEL_PGAMODE,
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OPAMP2_VMSEL_FOLLOWER
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};
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#endif
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#ifdef CONFIG_STM32_OPAMP3
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enum stm32_opamp3_vpsel_e
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{
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OPAMP3_VPSEL_PB13,
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OPAMP3_VPSEL_PA5,
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OPAMP3_VPSEL_PA1,
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OPAMP3_VPSEL_PB0
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};
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enum stm32_opamp3_vmsel_e
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{
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OPAMP3_VMSEL_PB10,
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OPAMP3_VMSEL_PB2,
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OPAMP3_VMSEL_PGAMODE,
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OPAMP3_VMSEL_FOLLOWER
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};
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#endif
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#ifdef CONFIG_STM32_OPAMP4
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enum stm32_opamp4_vpsel_e
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{
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OPAMP4_VPSEL_PD11,
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OPAMP4_VPSEL_PB11,
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OPAMP4_VPSEL_PA4,
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OPAMP4_VPSEL_PB13
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};
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enum stm32_opamp4_vmsel_e
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{
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OPAMP4_VMSEL_PB10,
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OPAMP4_VMSEL_PD8,
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OPAMP4_VMSEL_PGAMODE,
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OPAMP4_VMSEL_FOLLOWER
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};
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#endif
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/************************************************************************************
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* Public Function Prototypes
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************************************************************************************/
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Name: stm32_opampinitialize
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*
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* Description:
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* Initialize the OPAMP.
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*
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* Input Parameters:
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* intf - The OPAMP interface number.
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*
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* Returned Value:
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* Valid OPAMP device structure reference on succcess; a NULL on failure.
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*
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* Assumptions:
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* 1. Clock to the OPAMP block has enabled,
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* 2. Board-specific logic has already configured
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*
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****************************************************************************/
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FAR struct opamp_dev_s* stm32_opampinitialize(int intf);
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* CONFIG_STM32_OPAMP */
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#endif /* __ARCH_ARM_SRC_STM32_STM32_OPAMP_H */
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