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arch/armv7-a: Update the macro definition in gic.h

Browse Source 
https://developer.arm.com/documentation/ihi0048/b

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
This commit is contained in:
Xiang Xiao 2023-08-13 01:01:02 +08:00 committed by Alan Carvalho de Assis
parent 98985f48dd
commit e4dea90725
4 changed files with 73 additions and 95 deletions
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12
arch/arm/src/armv7-a/arm_gicv2.c
View File

@ -145,7 +145,7 @@ void arm_gic_initialize(void)
/* Registers with 1-bit per interrupt */
putreg32(0x00000000, GIC_ICDISR(0)); /* SGIs and PPIs secure */
putreg32(0xf8000000, GIC_ICDICER(0)); /* PPIs disabled */
putreg32(0xfe000000, GIC_ICDICER(0)); /* PPIs disabled */
/* Registers with 8-bits per interrupt */
@ -153,7 +153,7 @@ void arm_gic_initialize(void)
putreg32(0x80808080, GIC_ICDIPR(4)); /* SGI[4:7] priority */
putreg32(0x80808080, GIC_ICDIPR(8)); /* SGI[8:11] priority */
putreg32(0x80808080, GIC_ICDIPR(12)); /* SGI[12:15] priority */
putreg32(0x80000000, GIC_ICDIPR(24)); /* PPI[0] priority */
putreg32(0x80808000, GIC_ICDIPR(24)); /* PPI[0] priority */
putreg32(0x80808080, GIC_ICDIPR(28)); /* PPI[1:4] priority */
/* Set the binary point register.
@ -501,10 +501,10 @@ int up_prioritize_irq(int irq, int priority)
* distributor Interrupt Priority Register (GIC_ICDIPR).
*/
regaddr = GIC_ICDIPR(irq);
regval = getreg32(regaddr);
regval &= ~GIC_ICDIPR_ID_MASK(irq);
regval |= GIC_ICDIPR_ID(irq, priority);
regaddr = GIC_ICDIPR(irq);
regval = getreg32(regaddr);
regval &= ~GIC_ICDIPR_ID_MASK(irq);
regval |= GIC_ICDIPR_ID(irq, priority);
putreg32(regval, regaddr);
arm_gic_dump("Exit up_prioritize_irq", false, irq);

2
arch/arm/src/armv7-a/arm_gicv2_dump.c
View File

@ -226,7 +226,7 @@ static inline void arm_gic_dump_distributor(bool all, int irq, int nlines)
arm_gic_dump4("IPTR", GIC_ICDIPTR(0), nlines);
arm_gic_dump16("ICFR", GIC_ICDICFR(0), nlines);
arm_gic_dump32("PPSIR/SPISR", GIC_ICDPPISR, nlines);
arm_gic_dump32("NSACR", GIC_ICDNSACR(0), nlines);
arm_gic_dump16("NSACR", GIC_ICDNSACR(0), nlines);
arm_gic_dump8("SCPR/SSPR", GIC_ICDSCPR(0), nlines);
}
else

4
arch/arm/src/armv7-a/arm_timer.c
View File

@ -279,8 +279,8 @@ struct oneshot_lowerhalf_s *arm_timer_initialize(unsigned int freq)
arm_timer_set_ctrl(ctrl);
#if defined(CONFIG_ARCH_TRUSTZONE_SECURE) || defined(CONFIG_ARCH_TRUSTZONE_BOTH)
irq_attach(GIC_IRQ_SEPTM, arm_timer_interrupt, lower);
up_enable_irq(GIC_IRQ_SEPTM);
irq_attach(GIC_IRQ_STM, arm_timer_interrupt, lower);
up_enable_irq(GIC_IRQ_STM);
#else
irq_attach(GIC_IRQ_PTM, arm_timer_interrupt, lower);
up_enable_irq(GIC_IRQ_PTM);

150
arch/arm/src/armv7-a/gic.h
View File

@ -188,17 +188,13 @@
/* Non-secure Access Control Registers, optional: 00xe00-0x0efc */
#define GIC_ICDNSACR_OFFSET(n) (0x0e00 + GIC_OFFSET32(n))
#define GIC_ICDNSACR_OFFSET(n) (0x0e00 + GIC_OFFSET16(n))
/* Software Generated Interrupt Register: 0x0f00 */
#define GIC_ICDSGIR_OFFSET 0x0f00 /* Software Generated Interrupt Register */
/* 0x0f0c-0x0f0c: Reserved */
/* Peripheral Identification Registers: 0x0fd0-0xfe8 */
#define GIC_ICDPIDR_OFFSET(n) (0x0fd0 + ((n) << 2))
/* 0x0f04-0x0f0c: Reserved */
/* SGI Clear-Pending Registers: 0x0f10-0x0f1c */
@ -212,12 +208,14 @@
/* 0x0fd0-0x0ffc: Implementation defined */
/* Peripheral Identification Registers: 0x0fd0-0xfe8 */
#define GIC_ICDPIDR_OFFSET(n) (0x0fd0 + ((n) << 2))
/* Component Identification Registers: 0x0ff0-0x0ffc */
#define GIC_ICDCIDR_OFFSET(n) (0x0ff0 + ((n) << 2))
/* 0x0f04-0x0ffc: Reserved */
/* GIC Register Addresses ***************************************************/
/* The Interrupt Controller is a single functional unit that is located in a
@ -269,9 +267,9 @@
#define GIC_ICDSPISR(n) (MPCORE_ICD_VBASE+GIC_ICDSPISR_OFFSET(n))
#define GIC_ICDNSACR(n) (MPCORE_ICD_VBASE+GIC_ICDNSACR_OFFSET(n))
#define GIC_ICDSGIR (MPCORE_ICD_VBASE+GIC_ICDSGIR_OFFSET)
#define GIC_ICDPIDR(n) (MPCORE_ICD_VBASE+GIC_ICDPIDR_OFFSET(n))
#define GIC_ICDSCPR(n) (MPCORE_ICD_VBASE+GIC_ICDSCPR_OFFSET(n))
#define GIC_ICDSSPR(n) (MPCORE_ICD_VBASE+GIC_ICDSSPR_OFFSET(n))
#define GIC_ICDPIDR(n) (MPCORE_ICD_VBASE+GIC_ICDPIDR_OFFSET(n))
#define GIC_ICDCIDR(n) (MPCORE_ICD_VBASE+GIC_ICDCIDR_OFFSET(n))
/* GIC Register Bit Definitions *********************************************/
@ -332,8 +330,8 @@
#define GIC_ICCBPR_MASK (7 << GIC_ICCBPR_SHIFT)
# define GIC_ICCBPR_1_7 (0 << GIC_ICCBPR_SHIFT) /* Priority bits [7:1] compared for pre-emption */
# define GIC_ICCBPR_2_7 (1 << GIC_ICCBPR_SHIFT) /* Priority bits [7:2] compared for pre-emption */
# define GIC_ICCBPR_3_7 (2 << GIC_ICCBPR_SHIFT) /* Priority bits [7:2] compared for pre-emption */
# define GIC_ICCBPR_4_7 (3 << GIC_ICCBPR_SHIFT) /* Priority bits [7:2] compared for pre-emption */
# define GIC_ICCBPR_3_7 (2 << GIC_ICCBPR_SHIFT) /* Priority bits [7:3] compared for pre-emption */
# define GIC_ICCBPR_4_7 (3 << GIC_ICCBPR_SHIFT) /* Priority bits [7:4] compared for pre-emption */
# define GIC_ICCBPR_5_7 (4 << GIC_ICCBPR_SHIFT) /* Priority bits [7:5] compared for pre-emption */
# define GIC_ICCBPR_6_7 (5 << GIC_ICCBPR_SHIFT) /* Priority bits [7:6] compared for pre-emption */
# define GIC_ICCBPR_7_7 (6 << GIC_ICCBPR_SHIFT) /* Priority bit [7] compared for pre-emption */
@ -354,6 +352,7 @@
/* End of Interrupt Register */
#define GIC_ICCEOIR_SPURIOUSNS (0x3fe)
#define GIC_ICCEOIR_SPURIOUS (0x3ff)
#define GIC_ICCEOIR_INTID_SHIFT (0) /* Bits 0-9: Interrupt ID */
@ -367,9 +366,8 @@
/* Running Interrupt Register */
/* Bits 0-3: Reserved */
#define GIC_ICCRPR_PRIO_SHIFT (4) /* Bits 4-7: Priority mask */
#define GIC_ICCRPR_PRIO_MASK (15 << GIC_ICCRPR_PRIO_SHIFT)
#define GIC_ICCRPR_PRIO_SHIFT (0) /* Bits 0-7: Priority mask */
#define GIC_ICCRPR_PRIO_MASK (0xff << GIC_ICCRPR_PRIO_SHIFT)
# define GIC_ICCRPR_PRIO_VALUE(n) ((uint32_t)(n) << GIC_ICCRPR_PRIO_SHIFT)
/* Bits 8-31: Reserved */
@ -385,39 +383,6 @@
/* Bits 13-31: Reserved */
/* Aliased Interrupt Acknowledge Register */
#define GIC_ICCAIAR_
/* Aliased End of Interrupt Register */
#define GIC_ICCAEOIR_
/* Aliased Highest Priority Pending Interrupt Register */
#define GIC_ICCAHPIR_
/* Active Priorities Register 1 */
#define GIC_ICCAPR1_
/* Active Priorities Register 2 */
#define GIC_ICCAPR2_
/* Active Priorities Register 3 */
#define GIC_ICCAPR3_
/* Active Priorities Register 4 */
#define GIC_ICCAPR4_
/* Non-secure Active Priorities Register 1 */
#define GIC_ICCNSAPR1_
/* Non-secure Active Priorities Register 2 */
#define GIC_ICCNSAPR2_
/* Non-secure Active Priorities Register 3 */
#define GIC_ICCNSAPR3_
/* Non-secure Active Priorities Register 4 */
#define GIC_ICCNSAPR4_
/* CPU Interface Implementer ID Register */
#define GIC_ICCIDR_IMPL_SHIFT (0) /* Bits 0-11: Implementer */
@ -430,7 +395,13 @@
#define GIC_ICCIDR_PARTNO_MASK (0xfff << GIC_ICCIDR_PARTNO_SHIFT)
/* Deactivate Interrupt Register */
#define GIC_ICCDIR_
#define GIC_ICCDIR_INTID_SHIFT (0) /* Bits 0-9: Interrupt ID */
#define GIC_ICCDIR_INTID_MASK (0x3ff << GIC_ICCHPIR_INTID_SHIFT)
# define GIC_ICCDIR_INTID(n) ((uint32_t)(n) << GIC_ICCHPIR_INTID_SHIFT)
#define GIC_ICCDIR_CPUSRC_SHIFT (10) /* Bits 10-12: CPU source ID */
#define GIC_ICCDIR_CPUSRC_MASK (7 << GIC_ICCHPIR_CPUSRC_SHIFT)
# define GIC_ICCDIR_CPUSRC(n) ((uint32_t)(n) << GIC_ICCHPIR_CPUSRC_SHIFT)
/* Distributor Registers */
@ -461,10 +432,13 @@
#define GIC_ICDIIDR_IMPL_SHIFT (0) /* Bits 0-11: Implementer */
#define GIC_ICDIIDR_IMPL_MASK (0xfff << GIC_ICDIIDR_IMPL_SHIFT)
#define GIC_ICDIIDR_REVISION_SHIFT (12) /* Bits 12-23: Revision number */
#define GIC_ICDIIDR_REVISION_MASK (0xfff << GIC_ICDIIDR_REVISION_SHIFT)
#define GIC_ICDIIDR_VERSION_SHIFT (24) /* Bits 24-31: Iimplementer version */
#define GIC_ICDIIDR_VERSION_MASK (0xff << GIC_ICDIIDR_VERSION_SHIFT)
#define GIC_ICDIIDR_REVISION_SHIFT (12) /* Bits 12-15: Revision number */
#define GIC_ICDIIDR_REVISION_MASK (0xf << GIC_ICDIIDR_REVISION_SHIFT)
#define GIC_ICDIIDR_VARIANT_SHIFT (16) /* Bits 16-19 Variant number */
#define GIC_ICDIIDR_VARIANT_MASK (0xf << GIC_ICDIIDR_VARIANT_SHIFT)
/* Bits 20-23: Reserved */
#define GIC_ICDIIDR_PRODUCTID_SHIFT (24) /* Bits 24-31: Product id */
#define GIC_ICDIIDR_PRODUCTID_MASK (0xff << GIC_ICDIIDR_PRODUCTID_SHIFT)
/* Interrupt Security Registers: 0x0080-0x009c */
@ -548,29 +522,31 @@
/* Non-secure Access Control Registers, optional */
#define GIC_ICDNSACR_INT(n) GIC_MASK32(n)
#define GIC_ICDNSACR_NONE 0
#define GIC_ICDNSACR_SET 1
#define GIC_ICDNSACR_CLEAR 2
#define GIC_ICDNSACR_ROUTE 3
#define GIC_ICDNSACR_ID_SHIFT(n) GIC_SHIFT16(n)
#define GIC_ICDNSACR_ID_MASK(n) GIC_MASK16(n)
# define GIC_ICDNSACR_ID(n,p) ((uint32_t)(p) << GIC_SHIFT16(n))
/* Software Generated Interrupt Register */
#define GIC_ICDSGIR_INTID_SHIFT (0) /* Bits 0-9: Interrupt ID */
#define GIC_ICDSGIR_INTID_MASK (0x3ff << GIC_ICDSGIR_INTID_SHIFT)
# define GIC_ICDSGIR_INTID(n) ((uint32_t)(n) << GIC_ICDSGIR_INTID_SHIFT)
/* Bits 10-15: Reserved */
/* Bits 10-14: Reserved */
#define GIC_ICDSGIR_NSATT (1 << 15)
#define GIC_ICDSGIR_CPUTARGET_SHIFT (16) /* Bits 16-23: CPU target */
#define GIC_ICDSGIR_CPUTARGET_MASK (0xff << GIC_ICDSGIR_CPUTARGET_SHIFT)
# define GIC_ICDSGIR_CPUTARGET(n) ((uint32_t)(n) << GIC_ICDSGIR_CPUTARGET_SHIFT)
/* Bits 26-31: Reserved */
#define GIC_ICDSGIR_TGTFILTER_SHIFT (24) /* Bits 24-25: Target filter */
#define GIC_ICDSGIR_TGTFILTER_MASK (3 << GIC_ICDSGIR_TGTFILTER_SHIFT)
# define GIC_ICDSGIR_TGTFILTER_LIST (0 << GIC_ICDSGIR_TGTFILTER_SHIFT) /* Interrupt sent to CPUs CPU target list */
# define GIC_ICDSGIR_TGTFILTER_OTHER (1 << GIC_ICDSGIR_TGTFILTER_SHIFT) /* Interrupt is sent to all but requesting CPU */
# define GIC_ICDSGIR_TGTFILTER_THIS (2 << GIC_ICDSGIR_TGTFILTER_SHIFT) /* Interrupt is sent to requesting CPU only */
/* SGI Clear-Pending Registers */
#define GIC_ICDSCPR_
/* SGI Set-Pending Registers */
#define GIC_ICDSSPR_
/* Bits 26-31: Reserved */
/* Interrupt IDs ************************************************************/
@ -593,7 +569,7 @@
/* Each Cortex-A9 processor has private interrupts, ID0-ID15, that can only
* be triggered by software. These interrupts are aliased so that there is
* no requirement for a requesting Cortex-A9 processor to determine its own
* CPU ID when it deals with SGIs. The priority of an SGI depends on the
* CPU ID when it deals with SGIs. The priority of an SGI depends on the
* value set by the receiving Cortex-A9 processor in the banked SGI priority
* registers, not the priority set by the sending Cortex-A9 processor.
*
@ -601,32 +577,34 @@
* task management.
*/
#define GIC_IRQ_SGI0 0 /* Software Generated Interrupt (SGI) 0 */
#define GIC_IRQ_SGI1 1 /* Software Generated Interrupt (SGI) 1 */
#define GIC_IRQ_SGI2 2 /* Software Generated Interrupt (SGI) 2 */
#define GIC_IRQ_SGI3 3 /* Software Generated Interrupt (SGI) 3 */
#define GIC_IRQ_SGI4 4 /* Software Generated Interrupt (SGI) 4 */
#define GIC_IRQ_SGI5 5 /* Software Generated Interrupt (SGI) 5 */
#define GIC_IRQ_SGI6 6 /* Software Generated Interrupt (SGI) 6 */
#define GIC_IRQ_SGI7 7 /* Software Generated Interrupt (SGI) 7 */
#define GIC_IRQ_SGI8 8 /* Software Generated Interrupt (SGI) 8 */
#define GIC_IRQ_SGI9 9 /* Software Generated Interrupt (SGI) 9 */
#define GIC_IRQ_SGI10 10 /* Software Generated Interrupt (SGI) 10 */
#define GIC_IRQ_SGI11 11 /* Software Generated Interrupt (SGI) 11 */
#define GIC_IRQ_SGI12 12 /* Software Generated Interrupt (SGI) 12 */
#define GIC_IRQ_SGI13 13 /* Software Generated Interrupt (SGI) 13 */
#define GIC_IRQ_SGI14 14 /* Software Generated Interrupt (SGI) 14 */
#define GIC_IRQ_SGI15 15 /* Software Generated Interrupt (SGI) 15 */
#define GIC_IRQ_SGI0 0 /* Software Generated Interrupt (SGI) 0 */
#define GIC_IRQ_SGI1 1 /* Software Generated Interrupt (SGI) 1 */
#define GIC_IRQ_SGI2 2 /* Software Generated Interrupt (SGI) 2 */
#define GIC_IRQ_SGI3 3 /* Software Generated Interrupt (SGI) 3 */
#define GIC_IRQ_SGI4 4 /* Software Generated Interrupt (SGI) 4 */
#define GIC_IRQ_SGI5 5 /* Software Generated Interrupt (SGI) 5 */
#define GIC_IRQ_SGI6 6 /* Software Generated Interrupt (SGI) 6 */
#define GIC_IRQ_SGI7 7 /* Software Generated Interrupt (SGI) 7 */
#define GIC_IRQ_SGI8 8 /* Software Generated Interrupt (SGI) 8 */
#define GIC_IRQ_SGI9 9 /* Software Generated Interrupt (SGI) 9 */
#define GIC_IRQ_SGI10 10 /* Software Generated Interrupt (SGI) 10 */
#define GIC_IRQ_SGI11 11 /* Software Generated Interrupt (SGI) 11 */
#define GIC_IRQ_SGI12 12 /* Software Generated Interrupt (SGI) 12 */
#define GIC_IRQ_SGI13 13 /* Software Generated Interrupt (SGI) 13 */
#define GIC_IRQ_SGI14 14 /* Software Generated Interrupt (SGI) 14 */
#define GIC_IRQ_SGI15 15 /* Software Generated Interrupt (SGI) 15 */
#define GIC_IRQ_GTM 27 /* Global Timer (GTM) PPI(0) */
#define GIC_IRQ_FIQ 28 /* Fast Interrupt Request (nFIQ) PPI(1) */
#define GIC_IRQ_PTM 29 /* Private Timer (PTM) PPI(2) */
#define GIC_IRQ_WDT 30 /* Watchdog Timer (WDT) PPI(3) */
#define GIC_IRQ_IRQ 31 /* Interrupt Request (nIRQ) PPI(4) */
#define GIC_IRQ_VM 25 /* Virtual Maintenance Interrupt (VM) PPI(6) */
#define GIC_IRQ_HTM 26 /* Hypervisor Timer (HTM) PPI(5) */
#define GIC_IRQ_VTM 27 /* Virtual Timer (VTM) PPI(4) */
#define GIC_IRQ_FIQ 28 /* Fast Interrupt Request (nFIQ) PPI(0) */
#define GIC_IRQ_STM 29 /* Secure Physical Timer (STM) PPI(1) */
#define GIC_IRQ_PTM 30 /* Non-secure Physical Timer (PTM) PPI(2) */
#define GIC_IRQ_IRQ 31 /* Interrupt Request (nIRQ) PPI(3) */
/* Shared Peripheral Interrupts (SPI) follow */
#define GIC_IRQ_SPI 32 /* First SPI interrupt ID */
#define GIC_IRQ_SPI 32 /* First SPI interrupt ID */
/****************************************************************************
* Inline Functions
@ -686,10 +664,10 @@ static inline void arm_cpu_sgi(int sgi, unsigned int cpuset)
uint32_t regval;
#ifdef CONFIG_SMP
regval = GIC_ICDSGIR_INTID(sgi) | GIC_ICDSGIR_CPUTARGET(cpuset) |
regval = GIC_ICDSGIR_INTID(sgi) | GIC_ICDSGIR_CPUTARGET(cpuset) |
GIC_ICDSGIR_TGTFILTER_LIST;
#else
regval = GIC_ICDSGIR_INTID(sgi) | GIC_ICDSGIR_CPUTARGET(0) |
regval = GIC_ICDSGIR_INTID(sgi) | GIC_ICDSGIR_CPUTARGET(0) |
GIC_ICDSGIR_TGTFILTER_THIS;
#endif