Port STM32L4 SAI driver from MDK.
This commit is contained in:
Gregory Nutt
parent
377fadc816
commit
e4e7528b1a
@ -49,6 +49,8 @@ config STM32L4_STM32L476XX
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select STM32L4_HAVE_USART3
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select STM32L4_HAVE_UART4
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select STM32L4_HAVE_UART5
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select STM32L4_HAVE_SAI1
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select STM32L4_HAVE_SAI2
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config STM32L4_STM32L486XX
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bool
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@ -62,6 +64,8 @@ config STM32L4_STM32L486XX
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select STM32L4_HAVE_USART3
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select STM32L4_HAVE_UART4
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select STM32L4_HAVE_UART5
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select STM32L4_HAVE_SAI1
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select STM32L4_HAVE_SAI2
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select STM32L4_FLASH_1024KB
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choice
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@ -118,6 +122,14 @@ config STM32L4_HAVE_LTDC
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bool
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default n
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config STM32L4_HAVE_SAI1
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bool
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default n
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config STM32L4_HAVE_SAI2
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bool
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default n
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# These "hidden" settings are the OR of individual peripheral selections
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# indicating that the general capability is required.
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@ -212,6 +224,38 @@ config STM32L4_RNG
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default n
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select ARCH_HAVE_RNG
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config STM32L4_SAI1_A
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bool "SAI1 Block A"
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default n
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select AUDIO
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select I2S
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select SCHED_WORKQUEUE
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select STM32L4_SAI
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config STM32L4_SAI1_B
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bool "SAI1 Block B"
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default n
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select AUDIO
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select I2S
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select SCHED_WORKQUEUE
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select STM32L4_SAI
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config STM32L4_SAI2_A
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bool "SAI2 Block A"
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default n
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select AUDIO
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select I2S
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select SCHED_WORKQUEUE
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select STM32L4_SAI
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config STM32L4_SAI2_B
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bool "SAI2 Block B"
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default n
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select AUDIO
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select I2S
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select SCHED_WORKQUEUE
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select STM32L4_SAI
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comment "AHB3 Peripherals"
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config STM32L4_FMC
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@ -556,12 +600,10 @@ config STM32L4_TIM17
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config STM32L4_SAI1
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bool "SAI1"
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default n
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select STM32L4_SAI
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config STM32L4_SAI2
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bool "SAI2"
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default n
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select STM32L4_SAI
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config STM32L4_DFSDM
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bool "DFSDM"
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@ -2996,4 +3038,68 @@ endchoice
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endmenu
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menu "SAI Configuration"
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depends on STM32L4_SAI
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choice
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prompt "Operation mode"
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default STM32L4_SAI_DMA
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---help---
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Select the operation mode the SAI driver should use.
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config STM32L4_SAI_POLLING
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bool "Polling"
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---help---
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The SAI registers are polled for events.
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config STM32L4_SAI_INTERRUPTS
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bool "Interrupt"
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---help---
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Select to enable interrupt driven SAI support.
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config STM32L4_SAI_DMA
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bool "DMA"
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---help---
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Use DMA to improve SAI transfer performance.
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endchoice # Operation mode
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choice
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prompt "SAI1 synchronization enable"
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default STM32L4_SAI1_BOTH_ASYNC
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depends on STM32L4_SAI1_A && STM32L4_SAI1_B
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---help---
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Select the synchronization mode of the SAI sub-blocks
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config STM32L4_SAI1_BOTH_ASYNC
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bool "Both asynchronous"
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config STM32L4_SAI1_A_SYNC_WITH_B
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bool "Block A is synchronous with Block B"
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config STM32L4_SAI1_B_SYNC_WITH_A
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bool "Block B is synchronous with Block A"
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endchoice # SAI1 synchronization enable
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choice
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prompt "SAI2 synchronization enable"
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default STM32L4_SAI2_BOTH_ASYNC
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depends on STM32L4_SAI2_A && STM32L4_SAI2_B
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---help---
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Select the synchronization mode of the SAI sub-blocks
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config STM32L4_SAI2_BOTH_ASYNC
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bool "Both asynchronous"
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config STM32L4_SAI2_A_SYNC_WITH_B
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bool "Block A is synchronous with Block B"
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config STM32L4_SAI2_B_SYNC_WITH_A
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bool "Block B is synchronous with Block A"
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endchoice # SAI2 synchronization enable
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endmenu
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endif # ARCH_CHIP_STM32L4
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@ -1,6 +1,7 @@
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############################################################################
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# arch/arm/src/stm32l4/Make.defs
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#
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# Copyright (C) 2017 Gregory Nutt. All rights reserved.
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# Copyright (C) 2015-2016 Sebastien Lorquet. All rights reserved.
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# Author: Sebastien Lorquet <sebastien@lorquet.fr>
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#
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@ -181,6 +182,10 @@ ifeq ($(CONFIG_STM32L4_RNG),y)
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CHIP_CSRCS += stm32l4_rng.c
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endif
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ifeq ($(CONFIG_STM32L4_SAI),y)
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CHIP_CSRCS += stm32l4_sai.c
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endif
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ifeq ($(CONFIG_PWM),y)
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CHIP_CSRCS += stm32l4_pwm.c
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endif
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@ -51,65 +51,65 @@
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#define STM32L4_SAI_GCR_OFFSET 0x0000 /* SAI Global Configuration Register */
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#define STM32L4_SAI_ACR1_OFFSET 0x0004 /* SAI Configuration Register 1 A */
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#define STM32L4_SAI_ACR2_OFFSET 0x0008 /* SAI Configuration Register 2 A */
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#define STM32L4_SAI_AFRCR_OFFSET 0x000c /* SAI Frame Configuration Register A */
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#define STM32L4_SAI_ASLOTR_OFFSET 0x0010 /* SAI Slot Register A */
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#define STM32L4_SAI_AIM_OFFSET 0x0014 /* SAI Interrupt Mask Register 2 A */
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#define STM32L4_SAI_ASR_OFFSET 0x0018 /* SAI Status Register A */
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#define STM32L4_SAI_ACLRFR_OFFSET 0x001c /* SAI Clear Flag Register A */
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#define STM32L4_SAI_ADR_OFFSET 0x0020 /* SAI Data Register A */
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#define STM32L4_SAI_A_OFFSET 0x0004
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#define STM32L4_SAI_B_OFFSET 0x0024
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#define STM32L4_SAI_BCR1_OFFSET 0x0024 /* SAI Configuration Register 1 B */
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#define STM32L4_SAI_BCR2_OFFSET 0x0028 /* SAI Configuration Register 2 B */
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#define STM32L4_SAI_BFRCR_OFFSET 0x002c /* SAI Frame Configuration Register B */
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#define STM32L4_SAI_BSLOTR_OFFSET 0x0030 /* SAI Slot Register B */
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#define STM32L4_SAI_BIM_OFFSET 0x0034 /* SAI Interrupt Mask Register 2 B */
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#define STM32L4_SAI_BSR_OFFSET 0x0038 /* SAI Status Register B */
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#define STM32L4_SAI_BCLRFR_OFFSET 0x003c /* SAI Clear Flag Register A */
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#define STM32L4_SAI_BDR_OFFSET 0x0040 /* SAI Data Register B */
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#define STM32L4_SAI_CR1_OFFSET 0x0000 /* SAI Configuration Register 1 A */
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#define STM32L4_SAI_CR2_OFFSET 0x0004 /* SAI Configuration Register 2 A */
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#define STM32L4_SAI_FRCR_OFFSET 0x0008 /* SAI Frame Configuration Register A */
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#define STM32L4_SAI_SLOTR_OFFSET 0x000c /* SAI Slot Register A */
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#define STM32L4_SAI_IM_OFFSET 0x0010 /* SAI Interrupt Mask Register 2 A */
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#define STM32L4_SAI_SR_OFFSET 0x0014 /* SAI Status Register A */
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#define STM32L4_SAI_CLRFR_OFFSET 0x0018 /* SAI Clear Flag Register A */
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#define STM32L4_SAI_DR_OFFSET 0x001c /* SAI Data Register A */
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/* Register Addresses ***************************************************************/
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#define STM32L4_SAI1_GCR (STM32L4_SAI1_BASE+STM32L4_SAI_GCR_OFFSET)
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#define STM32L4_SAI1_GCR (STM32L4_SAI_GCR_OFFSET)
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#define STM32L4_SAI1_ACR1 (STM32L4_SAI1_BASE+STM32L4_SAI_ACR1_OFFSET)
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#define STM32L4_SAI1_ACR2 (STM32L4_SAI1_BASE+STM32L4_SAI_ACR2_OFFSET)
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#define STM32L4_SAI1_AFRCR (STM32L4_SAI1_BASE+STM32L4_SAI_AFRCR_OFFSET)
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#define STM32L4_SAI1_ASLOTR (STM32L4_SAI1_BASE+STM32L4_SAI_ASLOTR_OFFSET)
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#define STM32L4_SAI1_AIM (STM32L4_SAI1_BASE+STM32L4_SAI_AIM_OFFSET)
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#define STM32L4_SAI1_ASR (STM32L4_SAI1_BASE+STM32L4_SAI_ASR_OFFSET)
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#define STM32L4_SAI1_ACLRFR (STM32L4_SAI1_BASE+STM32L4_SAI_ACLRFR_OFFSET)
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#define STM32L4_SAI1_ADR (STM32L4_SAI1_BASE+STM32L4_SAI_ADR_OFFSET)
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#define STM32L4_SAI1_A_BASE (STM32L4_SAI1_BASE+STM32L4_SAI_A_OFFSET)
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#define STM32L4_SAI1_B_BASE (STM32L4_SAI1_BASE+STM32L4_SAI_B_OFFSET)
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#define STM32L4_SAI1_BCR1 (STM32L4_SAI1_BASE+STM32L4_SAI_BCR1_OFFSET)
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#define STM32L4_SAI1_BCR2 (STM32L4_SAI1_BASE+STM32L4_SAI_BCR2_OFFSET)
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#define STM32L4_SAI1_BFRCR (STM32L4_SAI1_BASE+STM32L4_SAI_BFRCR_OFFSET)
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#define STM32L4_SAI1_BSLOTR (STM32L4_SAI1_BASE+STM32L4_SAI_BSLOTR_OFFSET)
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#define STM32L4_SAI1_BIM (STM32L4_SAI1_BASE+STM32L4_SAI_BIM_OFFSET)
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#define STM32L4_SAI1_BSR (STM32L4_SAI1_BASE+STM32L4_SAI_BSR_OFFSET)
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#define STM32L4_SAI1_BCLRFR (STM32L4_SAI1_BASE+STM32L4_SAI_BCLRFR_OFFSET)
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#define STM32L4_SAI1_BDR (STM32L4_SAI1_BASE+STM32L4_SAI_BDR_OFFSET)
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#define STM32L4_SAI1_ACR1 (STM32L4_SAI1_A_BASE+STM32L4_SAI_ACR1_OFFSET)
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#define STM32L4_SAI1_ACR2 (STM32L4_SAI1_A_BASE+STM32L4_SAI_ACR2_OFFSET)
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#define STM32L4_SAI1_AFRCR (STM32L4_SAI1_A_BASE+STM32L4_SAI_AFRCR_OFFSET)
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#define STM32L4_SAI1_ASLOTR (STM32L4_SAI1_A_BASE+STM32L4_SAI_ASLOTR_OFFSET)
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#define STM32L4_SAI1_AIM (STM32L4_SAI1_A_BASE+STM32L4_SAI_AIM_OFFSET)
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#define STM32L4_SAI1_ASR (STM32L4_SAI1_A_BASE+STM32L4_SAI_ASR_OFFSET)
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#define STM32L4_SAI1_ACLRFR (STM32L4_SAI1_A_BASE+STM32L4_SAI_ACLRFR_OFFSET)
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#define STM32L4_SAI1_ADR (STM32L4_SAI1_A_BASE+STM32L4_SAI_ADR_OFFSET)
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#define STM32L4_SAI1_BCR1 (STM32L4_SAI1_B_BASE+STM32L4_SAI_BCR1_OFFSET)
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#define STM32L4_SAI1_BCR2 (STM32L4_SAI1_B_BASE+STM32L4_SAI_BCR2_OFFSET)
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#define STM32L4_SAI1_BFRCR (STM32L4_SAI1_B_BASE+STM32L4_SAI_BFRCR_OFFSET)
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#define STM32L4_SAI1_BSLOTR (STM32L4_SAI1_B_BASE+STM32L4_SAI_BSLOTR_OFFSET)
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#define STM32L4_SAI1_BIM (STM32L4_SAI1_B_BASE+STM32L4_SAI_BIM_OFFSET)
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#define STM32L4_SAI1_BSR (STM32L4_SAI1_B_BASE+STM32L4_SAI_BSR_OFFSET)
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#define STM32L4_SAI1_BCLRFR (STM32L4_SAI1_B_BASE+STM32L4_SAI_BCLRFR_OFFSET)
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#define STM32L4_SAI1_BDR (STM32L4_SAI1_B_BASE+STM32L4_SAI_BDR_OFFSET)
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#define STM32L4_SAI2_GCR (STM32L4_SAI2_BASE+STM32L4_SAI_GCR_OFFSET)
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#define STM32L4_SAI2_ACR1 (STM32L4_SAI2_BASE+STM32L4_SAI_ACR1_OFFSET)
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#define STM32L4_SAI2_ACR2 (STM32L4_SAI2_BASE+STM32L4_SAI_ACR2_OFFSET)
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#define STM32L4_SAI2_AFRCR (STM32L4_SAI2_BASE+STM32L4_SAI_AFRCR_OFFSET)
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#define STM32L4_SAI2_ASLOTR (STM32L4_SAI2_BASE+STM32L4_SAI_ASLOTR_OFFSET)
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#define STM32L4_SAI2_AIM (STM32L4_SAI2_BASE+STM32L4_SAI_AIM_OFFSET)
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#define STM32L4_SAI2_ASR (STM32L4_SAI2_BASE+STM32L4_SAI_ASR_OFFSET)
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#define STM32L4_SAI2_ACLRFR (STM32L4_SAI2_BASE+STM32L4_SAI_ACLRFR_OFFSET)
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#define STM32L4_SAI2_ADR (STM32L4_SAI2_BASE+STM32L4_SAI_ADR_OFFSET)
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#define STM32L4_SAI2_A_BASE (STM32L4_SAI2_BASE+STM32L4_SAI_A_OFFSET)
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#define STM32L4_SAI2_B_BASE (STM32L4_SAI2_BASE+STM32L4_SAI_B_OFFSET)
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#define STM32L4_SAI2_BCR1 (STM32L4_SAI2_BASE+STM32L4_SAI_BCR1_OFFSET)
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#define STM32L4_SAI2_BCR2 (STM32L4_SAI2_BASE+STM32L4_SAI_BCR2_OFFSET)
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#define STM32L4_SAI2_BFRCR (STM32L4_SAI2_BASE+STM32L4_SAI_BFRCR_OFFSET)
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#define STM32L4_SAI2_BSLOTR (STM32L4_SAI2_BASE+STM32L4_SAI_BSLOTR_OFFSET)
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#define STM32L4_SAI2_BIM (STM32L4_SAI2_BASE+STM32L4_SAI_BIM_OFFSET)
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#define STM32L4_SAI2_BSR (STM32L4_SAI2_BASE+STM32L4_SAI_BSR_OFFSET)
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#define STM32L4_SAI2_BCLRFR (STM32L4_SAI2_BASE+STM32L4_SAI_BCLRFR_OFFSET)
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#define STM32L4_SAI2_BDR (STM32L4_SAI2_BASE+STM32L4_SAI_BDR_OFFSET)
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#define STM32L4_SAI2_ACR1 (STM32L4_SAI2_A_BASE+STM32L4_SAI_ACR1_OFFSET)
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#define STM32L4_SAI2_ACR2 (STM32L4_SAI2_A_BASE+STM32L4_SAI_ACR2_OFFSET)
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#define STM32L4_SAI2_AFRCR (STM32L4_SAI2_A_BASE+STM32L4_SAI_AFRCR_OFFSET)
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#define STM32L4_SAI2_ASLOTR (STM32L4_SAI2_A_BASE+STM32L4_SAI_ASLOTR_OFFSET)
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#define STM32L4_SAI2_AIM (STM32L4_SAI2_A_BASE+STM32L4_SAI_AIM_OFFSET)
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#define STM32L4_SAI2_ASR (STM32L4_SAI2_A_BASE+STM32L4_SAI_ASR_OFFSET)
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#define STM32L4_SAI2_ACLRFR (STM32L4_SAI2_A_BASE+STM32L4_SAI_ACLRFR_OFFSET)
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#define STM32L4_SAI2_ADR (STM32L4_SAI2_A_BASE+STM32L4_SAI_ADR_OFFSET)
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#define STM32L4_SAI2_BCR1 (STM32L4_SAI2_B_BASE+STM32L4_SAI_BCR1_OFFSET)
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#define STM32L4_SAI2_BCR2 (STM32L4_SAI2_B_BASE+STM32L4_SAI_BCR2_OFFSET)
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#define STM32L4_SAI2_BFRCR (STM32L4_SAI2_B_BASE+STM32L4_SAI_BFRCR_OFFSET)
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#define STM32L4_SAI2_BSLOTR (STM32L4_SAI2_B_BASE+STM32L4_SAI_BSLOTR_OFFSET)
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#define STM32L4_SAI2_BIM (STM32L4_SAI2_B_BASE+STM32L4_SAI_BIM_OFFSET)
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#define STM32L4_SAI2_BSR (STM32L4_SAI2_B_BASE+STM32L4_SAI_BSR_OFFSET)
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#define STM32L4_SAI2_BCLRFR (STM32L4_SAI2_B_BASE+STM32L4_SAI_BCLRFR_OFFSET)
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#define STM32L4_SAI2_BDR (STM32L4_SAI2_B_BASE+STM32L4_SAI_BDR_OFFSET)
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/* Register Bitfield Definitions ****************************************************/
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@ -128,10 +128,10 @@
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#define SAI_CR1_MODE_SHIFT (0) /* Bits 0-1: SAI audio block mode */
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#define SAI_CR1_MODE_MASK (3 << SAI_CR1_MODE_SHIFT)
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# define SAI_CR1_MODE_MXMIT (0 << SAI_CR1_MODE_SHIFT) /* Master transmitter */
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# define SAI_CR1_MODE_MRECV (1 << SAI_CR1_MODE_SHIFT) /* Master receiver */
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# define SAI_CR1_MODE_SXMIT (2 << SAI_CR1_MODE_SHIFT) /* Slave transmitter */
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# define SAI_CR1_MODE_SRECV (3 << SAI_CR1_MODE_SHIFT) /* Slave receiver */
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# define SAI_CR1_MODE_MASTER_TX (0 << SAI_CR1_MODE_SHIFT) /* Master transmitter */
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# define SAI_CR1_MODE_MASTER_RX (1 << SAI_CR1_MODE_SHIFT) /* Master receiver */
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# define SAI_CR1_MODE_SLAVE_TX (2 << SAI_CR1_MODE_SHIFT) /* Slave transmitter */
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# define SAI_CR1_MODE_SLAVE_RX (3 << SAI_CR1_MODE_SHIFT) /* Slave receiver */
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#define SAI_CR1_PRTCFG_SHIFT (2) /* Bits 2-3: Protocol configuration */
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#define SAI_CR1_PRTCFG_MASK (3 << SAI_CR1_PRTCFG_SHIFT)
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# define SAI_CR1_PRTCFG_FREE (0 << SAI_CR1_PRTCFG_SHIFT) /* Free protocol */
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@ -167,12 +167,12 @@
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/* SAI Configuration Register 2 */
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#define SAI_CR2_FTH_SHIFT (x0x) /* Bits 0-2: FIFO threshold */
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#define SAI_CR2_FTH_SHIFT (0) /* Bits 0-2: FIFO threshold */
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#define SAI_CR2_FTH_MASK (7 << SAI_CR2_FTH_SHIFT)
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# define SAI_CR2_FTH_EMPTY (0 << SAI_CR2_FTH_SHIFT) /* FIFO empty */
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# define SAI_CR2_FTH_25PCT (1 << SAI_CR2_FTH_SHIFT) /* 25% FIFO */
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# define SAI_CR2_FTH_50PCT (2 << SAI_CR2_FTH_SHIFT) /* 50% FIFO */
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# define SAI_CR2_FTH_75PCT (3 << SAI_CR2_FTH_SHIFT) /* 75% FIFO */
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# define SAI_CR2_FTH_1QF (1 << SAI_CR2_FTH_SHIFT) /* 1/4 FIFO */
|
||||
# define SAI_CR2_FTH_HF (2 << SAI_CR2_FTH_SHIFT) /* 1/2 FIFO */
|
||||
# define SAI_CR2_FTH_3QF (3 << SAI_CR2_FTH_SHIFT) /* 3/4 FIFO */
|
||||
# define SAI_CR2_FTH_FULL (4 << SAI_CR2_FTH_SHIFT) /* FIFO full */
|
||||
#define SAI_CR2_FFLUSH (1 << 3) /* Bit 3: FIFO flush */
|
||||
#define SAI_CR2_TRIS (1 << 4) /* Bit 4: Tristate management on data line */
|
||||
@ -193,13 +193,19 @@
|
||||
|
||||
#define SAI_FRCR_FRL_SHIFT (0) /* Bits 0-7: Frame length */
|
||||
#define SAI_FRCR_FRL_MASK (0xff << SAI_FRCR_FRL_SHIFT)
|
||||
# define SAI_FRCR_FRL(n) ((uint32_t)(n) << SAI_FRCR_FRL_SHIFT)
|
||||
# define SAI_FRCR_FRL(n) ((uint32_t)((n) - 1) << SAI_FRCR_FRL_SHIFT)
|
||||
#define SAI_FRCR_FSALL_SHIFT (8) /* Bits 8-14: Frame synchronization active level length */
|
||||
#define SAI_FRCR_FSALL_MASK (0x7f << SAI_FRCR_FSALL_SHIFT)
|
||||
# define SAI_FRCR_FSALL(n) ((uint32_t)(n) << SAI_FRCR_FSALL_SHIFT)
|
||||
# define SAI_FRCR_FSALL(n) ((uint32_t)((n) - 1) << SAI_FRCR_FSALL_SHIFT)
|
||||
#define SAI_FRCR_FSDEF (1 << 16) /* Bit 16: Frame synchronization definition */
|
||||
# define SAI_FRCR_FSDEF_SF (0) /* FS signal is a start frame signal */
|
||||
# define SAI_FRCR_FSDEF_CHID SAI_FRCR_FSDEF /* FS signal is a start of frame + channel side ID */
|
||||
#define SAI_FRCR_FSPOL (1 << 17) /* Bit 17: Frame synchronization polarity */
|
||||
# define SAI_FRCR_FSPOL_LOW (0) /* FS is active low */
|
||||
# define SAI_FRCR_FSPOL_HIGH SAI_FRCR_FSPOL /* FS is active high */
|
||||
#define SAI_FRCR_FSOFF (1 << 18) /* Bit 18: Frame synchronization offset */
|
||||
# define SAI_FRCR_FSOFF_FB (0) /* FS on first bit of slot 0 */
|
||||
# define SAI_FRCR_FSOFF_BFB SAI_FRCR_FSOFF /* FS one bit before first bit of slot 0 */
|
||||
/* Bits 19-31: Reserved */
|
||||
|
||||
/* SAI Slot Register */
|
||||
@ -215,11 +221,27 @@
|
||||
# define SAI_SLOTR_SLOTSZ_32BIT (2 << SAI_SLOTR_SLOTSZ_SHIFT) /* 32-bit */
|
||||
#define SAI_SLOTR_NBSLOT_SHIFT (0) /* Bits 0-3: Number of slots in an audio frame */
|
||||
#define SAI_SLOTR_NBSLOT_MASK (15 << SAI_SLOTR_NBSLOT_SHIFT)
|
||||
# define SAI_SLOTR_NBSLOT(n) ((uint32_t)(n) << SAI_SLOTR_NBSLOT_SHIFT)
|
||||
# define SAI_SLOTR_NBSLOT(n) ((uint32_t)((n) - 1) << SAI_SLOTR_NBSLOT_SHIFT)
|
||||
/* Bits 12-15: Reserved */
|
||||
#define SAI_SLOTR_SLOTEN_SHIFT (16) /* Bits 16-31: Slot enable */
|
||||
#define SAI_SLOTR_SLOTEN_MASK (0xffff << SAI_SLOTR_SLOTEN_SHIFT)
|
||||
# define SAI_SLOTR_SLOTEN(n) ((uint32_t)(n) << SAI_SLOTR_SLOTEN_SHIFT)
|
||||
# define SAI_SLOTR_SLOTEN_0 (1 << 16) /* Bit 16: Slot 0 Enabled */
|
||||
# define SAI_SLOTR_SLOTEN_1 (1 << 17) /* Bit 17: Slot 1 Enabled */
|
||||
# define SAI_SLOTR_SLOTEN_2 (1 << 18) /* Bit 18: Slot 2 Enabled */
|
||||
# define SAI_SLOTR_SLOTEN_3 (1 << 19) /* Bit 19: Slot 3 Enabled */
|
||||
# define SAI_SLOTR_SLOTEN_4 (1 << 20) /* Bit 20: Slot 4 Enabled */
|
||||
# define SAI_SLOTR_SLOTEN_5 (1 << 21) /* Bit 21: Slot 5 Enabled */
|
||||
# define SAI_SLOTR_SLOTEN_6 (1 << 22) /* Bit 22: Slot 6 Enabled */
|
||||
# define SAI_SLOTR_SLOTEN_7 (1 << 23) /* Bit 23: Slot 7 Enabled */
|
||||
# define SAI_SLOTR_SLOTEN_8 (1 << 24) /* Bit 24: Slot 8 Enabled */
|
||||
# define SAI_SLOTR_SLOTEN_9 (1 << 25) /* Bit 25: Slot 9 Enabled */
|
||||
# define SAI_SLOTR_SLOTEN_10 (1 << 26) /* Bit 26: Slot 10 Enabled */
|
||||
# define SAI_SLOTR_SLOTEN_11 (1 << 27) /* Bit 27: Slot 11 Enabled */
|
||||
# define SAI_SLOTR_SLOTEN_12 (1 << 28) /* Bit 28: Slot 12 Enabled */
|
||||
# define SAI_SLOTR_SLOTEN_13 (1 << 29) /* Bit 29: Slot 13 Enabled */
|
||||
# define SAI_SLOTR_SLOTEN_14 (1 << 30) /* Bit 30: Slot 14 Enabled */
|
||||
# define SAI_SLOTR_SLOTEN_15 (1 << 31) /* Bit 31: Slot 15 Enabled */
|
||||
|
||||
/* SAI Interrupt Mask Register 2, SAI Status Register, and SAI Clear Flag Register */
|
||||
|
||||
|
||||
1450
arch/arm/src/stm32l4/stm32l4_sai.c
Normal file
1450
arch/arm/src/stm32l4/stm32l4_sai.c
Normal file
File diff suppressed because it is too large
Load Diff
95
arch/arm/src/stm32l4/stm32l4_sai.h
Normal file
95
arch/arm/src/stm32l4/stm32l4_sai.h
Normal file
@ -0,0 +1,95 @@
|
||||
/******************************************************************************
|
||||
* arch/arm/src/stm32l4/stm32l4_sai.h
|
||||
*
|
||||
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
|
||||
* Copyright (c) 2016 Motorola Mobility, LLC.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_SAI_H
|
||||
#define __ARCH_ARM_SRC_STM32L4_STM32L4_SAI_H
|
||||
|
||||
/******************************************************************************
|
||||
* Included Files
|
||||
******************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "chip/stm32l4_sai.h"
|
||||
|
||||
#include <nuttx/audio/i2s.h>
|
||||
|
||||
/******************************************************************************
|
||||
* Pre-processor definitions
|
||||
******************************************************************************/
|
||||
|
||||
#define SAI1_BLOCK_A 0
|
||||
#define SAI1_BLOCK_B 1
|
||||
#define SAI2_BLOCK_A 2
|
||||
#define SAI2_BLOCK_B 3
|
||||
|
||||
/******************************************************************************
|
||||
* Public Function Prototypes
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32l4_sai_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the selected SAI block
|
||||
*
|
||||
* Input Parameters:
|
||||
* intf - I2S interface number (identifying the "logical" SAI interface)
|
||||
*
|
||||
* Returned Value:
|
||||
* Valid I2S device structure reference on success; a NULL on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
struct i2s_dev_s *stm32l4_sai_initialize(int intf);
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_SAI_H */
|
||||
Loading…
Reference in New Issue
Block a user