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Cosmetic update to comments and README files

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This commit is contained in:
Gregory Nutt 2014-04-24 12:44:30 -06:00
parent 0d2e525bd4
commit e4fd434a60
2 changed files with 31 additions and 34 deletions
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24
arch/arm/src/armv7-a/mmu.h
View File

@ -333,12 +333,12 @@
*
* Key:
*
* WR - Read/write addess allowed
* WR - Read/write address allowed
* R - Read-only access allowed
* 0,1,2 - At PL0, PL1, and/or PL2
*
* PL0 - User privilege level
* PL1 - Privilieged mode
* PL1 - Privileged mode
* PL2 - Software executing in Hyp mode
*/
@ -501,7 +501,7 @@
*
* Interpretation of Cacheable (C) and Bufferable (B) Bits:
*
* Write-Through Write-Back Write-Through/Write-Back
* Write-Through Write-Back Write-Through/Write-Back
* C B Cache Only Cache Cache
* --- --- -------------- ------------- -------------------------
* 0 0 Uncached/ Uncached/ Uncached/
@ -668,7 +668,7 @@
/* Page Table Info ******************************************************************/
/* The number of pages in the in the page table (PG_PGTABLE_NPAGES). We
* position the pagetable PTEs just after the data section PTEs.
* position the page table PTEs just after the data section PTEs.
*/
#define PG_PGTABLE_NPAGES (PGTABLE_SIZE >> PAGESHIFT)
@ -750,7 +750,7 @@
/* Page Management ******************************************************************/
/* For page managment purposes, the following summarize the "heap" of
/* For page management purposes, the following summarize the "heap" of
* free pages, operations on free pages and the L2 page table.
*
* PG_POOL_VA2L1OFFSET(va) - Given a virtual address, return the L1 table
@ -778,7 +778,7 @@
* Index 0 corresponds to the first L2 page table
* entry for the first page in the virtual paged
* text address space.
* PG_POOL_NDX2VA(ndx) - Performs the opposite conversion.. convests
* PG_POOL_NDX2VA(ndx) - Performs the opposite conversion.. converts
* an index into a virtual address in the paged
* text region (the address at the beginning of
* the page).
@ -952,7 +952,7 @@ struct section_mapping_s
* Description:
* Write several, contiguous L2 page table entries. npages entries will be
* written. This macro is used when CONFIG_PAGING is enable. This case,
* it is used asfollows:
* it is used as follows:
*
* ldr r0, =PGTABLE_L2_BASE_PADDR <-- Address in L2 table
* ldr r1, =PG_LOCKED_PBASE <-- Physical page memory address
@ -1247,9 +1247,9 @@ static inline void cp14_wrttb(unsigned int ttb)
* Name: mmu_l1_getentry
*
* Description:
* Given a virtual address, return the valule of the corresponding L1 table entry.
* Given a virtual address, return the value of the corresponding L1 table entry.
*
* Input Paramters:
* Input Parameters:
* vaddr - The virtual address to be mapped.
*
************************************************************************************/
@ -1271,9 +1271,9 @@ static inline uint32_t mmu_l1_getentry(uint32_t vaddr)
*
* Description:
* Given a address of the beginning of an L2 page table and a virtual address,
* return the varlue of the corresponding L2 page table entry.
* return the value of the corresponding L2 page table entry.
*
* Input Paramters:
* Input Parameters:
* l2vaddr - The virtual address of the beginning of the L2 page table
* vaddr - The virtual address to be mapped.
*
@ -1323,7 +1323,7 @@ extern "C" {
* Set a one level 1 translation table entry. Only a single L1 page table is
* supported.
*
* Input Paramters:
* Input Parameters:
* paddr - The physical address to be mapped. Must be aligned to a 1MB address
* boundary
* vaddr - The virtual address to be mapped. Must be aligned to a 1MB address

41
arch/arm/src/sam34/sam_spi.c
View File

@ -204,7 +204,7 @@ struct sam_spics_s
#endif
};
/* Type of board-specific SPI status fuction */
/* Type of board-specific SPI status function */
typedef void (*select_t)(enum spi_dev_e devid, bool selected);
@ -216,7 +216,7 @@ struct sam_spidev_s
{
uint32_t base; /* SPI controller register base address */
sem_t spisem; /* Assures mutually exclusive access to SPI */
select_t select; /* SPI select callout */
select_t select; /* SPI select call-out */
bool initialized; /* TRUE: Controller has been initialized */
#ifdef CONFIG_SAM34_SPI_DMA
uint8_t rxintf; /* RX hardware interface number */
@ -599,7 +599,7 @@ static inline void spi_flush(struct sam_spidev_s *spi)
* Map the chip select number to the bit-set PCS field used in the SPI
* registers. A chip select number is used for indexing and identifying
* chip selects. However, the chip select information is represented by
* a bit set in the SPI regsisters. This function maps those chip select
* a bit set in the SPI registers. This function maps those chip select
* numbers to the correct bit set:
*
* CS Returned Spec Effective
@ -699,7 +699,7 @@ static void spi_dma_sampledone(struct sam_spics_s *spics)
/* Register values at the time of the TX and RX DMA callbacks
* -OR- DMA timeout.
*
* If the DMA timedout, then there will not be any RX DMA
* If the DMA timed out, then there will not be any RX DMA
* callback samples. There is probably no TX DMA callback
* samples either, but we don't know for sure.
*/
@ -776,7 +776,7 @@ static void spi_dmatimeout(int argc, uint32_t arg)
*
* Input Parameters:
* handle - The DMA handler
* arg - A pointer to the chip select struction
* arg - A pointer to the chip select structure
* result - The result of the DMA transfer
*
* Returned Value:
@ -804,7 +804,7 @@ static void spi_rxcallback(DMA_HANDLE handle, void *arg, int result)
if (spics->result == -EBUSY)
{
/* Save the result of the transfer if no error was previuosly reported */
/* Save the result of the transfer if no error was previously reported */
spics->result = result;
}
@ -874,12 +874,12 @@ static inline uintptr_t spi_regaddr(struct sam_spics_s *spics,
* Name: spi_lock
*
* Description:
* On SPI busses where there are multiple devices, it will be necessary to
* lock SPI to have exclusive access to the busses for a sequence of
* On SPI buses where there are multiple devices, it will be necessary to
* lock SPI to have exclusive access to the buses for a sequence of
* transfers. The bus should be locked before the chip is selected. After
* locking the SPI bus, the caller should then also call the setfrequency,
* setbits, and setmode methods to make sure that the SPI is properly
* configured for the device. If the SPI buss is being shared, then it
* configured for the device. If the SPI bus is being shared, then it
* may have been left in an incompatible state.
*
* Input Parameters:
@ -1262,7 +1262,7 @@ static uint16_t spi_send(struct spi_dev_s *dev, uint16_t wd)
* Input Parameters:
* dev - Device-specific state data
* txbuffer - A pointer to the buffer of data to be sent
* rxbuffer - A pointer to the buffer in which to recieve data
* rxbuffer - A pointer to the buffer in which to receive data
* nwords - the length of data that to be exchanged in units of words.
* The wordsize is determined by the number of bits-per-word
* selected for the SPI interface. If nbits <= 8, the data is
@ -1318,14 +1318,11 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
spi_flush(spi);
/* Loop, sending each word in the user-provied data buffer.
/* Loop, sending each word in the user-provided data buffer.
*
* Note 1: Right now, this only deals with 8-bit words. If the SPI
* interface were configured for words of other sizes, this
* would fail.
* Note 2: Good SPI performance would require that we implement DMA
* Note 1: Good SPI performance would require that we implement DMA
* transfers!
* Note 3: This loop might be made more efficient. Would logic
* Note 2: This loop might be made more efficient. Would logic
* like the following improve the throughput? Or would it
* just add the risk of overruns?
*
@ -1603,7 +1600,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
spi_txdma_sample(spics, DMA_AFTER_START);
/* Wait for DMA completion. This is done in a loop becaue there my be
/* Wait for DMA completion. This is done in a loop because there may be
* false alarm semaphore counts that cause sam_wait() not fail to wait
* or to wake-up prematurely (for example due to the receipt of a signal).
* We know that the DMA has completed when the result is anything other
@ -1634,7 +1631,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
if (ret < 0)
{
/* EINTR is not a failure. That simply means that the wait
* was awakened by a signel.
* was awakened by a signal.
*/
int errorcode = errno;
@ -1645,9 +1642,9 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
}
}
/* Not that we might be awkened before the wait is over due to
/* Not that we might be awakened before the wait is over due to
* residual counts on the semaphore. So, to handle, that case,
* we loop until somthing changes the DMA result to any value other
* we loop until something changes the DMA result to any value other
* than -EBUSY.
*/
}
@ -1712,7 +1709,7 @@ static void spi_sndblock(struct spi_dev_s *dev, const void *buffer,
*
* Input Parameters:
* dev - Device-specific state data
* buffer - A pointer to the buffer in which to recieve data
* buffer - A pointer to the buffer in which to receive data
* nwords - the length of data that can be received in the buffer in number
* of words. The wordsize is determined by the number of bits-per-word
* selected for the SPI interface. If nbits <= 8, the data is
@ -1747,7 +1744,7 @@ static void spi_recvblock(struct spi_dev_s *dev, void *buffer, size_t nwords)
* cs - Chip select number (identifying the "logical" SPI port)
*
* Returned Value:
* Valid SPI device structure reference on succcess; a NULL on failure
* Valid SPI device structure reference on success; a NULL on failure
*
****************************************************************************/