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photon: wlan support

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This commit is contained in:
Simon Piriou 2017-03-26 17:42:53 +02:00
parent 1f71c8ced8
commit e5c4a28c3a
22 changed files with 19028 additions and 684 deletions

26
arch/arm/src/stm32/stm32_sdio.c

@ -186,7 +186,8 @@
/* Big DTIMER setting */
#define SDIO_DTIMER_DATATIMEOUT (0x000fffff)
// #define SDIO_DTIMER_DATATIMEOUT (0x000fffff)
#define SDIO_DTIMER_DATATIMEOUT (0xffffffff)
/* DMA channel/stream configuration register settings. The following
* must be selected. The DMA driver will select the remaining fields.
@ -300,7 +301,7 @@
# endif
#endif
#define STM32_SDIO_USE_DEFAULT_BLOCK_SIZE ((uint8_t)-1)
#define STM32_SDIO_USE_DEFAULT_BLOCKSIZE ((uint8_t)-1)
/****************************************************************************
* Private Types
@ -468,8 +469,6 @@ static int stm32_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd,
uint32_t rlong[4]);
static int stm32_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd,
uint32_t *rshort);
static int stm32_recvnotimpl(FAR struct sdio_dev_s *dev, uint32_t cmd,
uint32_t *rnotimpl);
/* EVENT handler */
@ -1027,8 +1026,11 @@ static void stm32_dataconfig(uint32_t timeout, uint32_t dlen, uint32_t dctrl)
regval = getreg32(STM32_SDIO_DCTRL);
regval &= ~(SDIO_DCTRL_DTDIR | SDIO_DCTRL_DTMODE | SDIO_DCTRL_DBLOCKSIZE_MASK);
dctrl &= (SDIO_DCTRL_DTDIR | SDIO_DCTRL_DTMODE | SDIO_DCTRL_DBLOCKSIZE_MASK);
regval |= (dctrl | SDIO_DCTRL_DTEN);
regval |= (dctrl | SDIO_DCTRL_DTEN | SDIO_DCTRL_SDIOEN);
putreg32(regval, STM32_SDIO_DCTRL);
struct stm32_dev_s *priv = &g_sdiodev;
// mcinfo("data cfg: %08x %08x %08x (bs=%d)\n", timeout, dlen, regval, 1<<priv->block_size);
}
/****************************************************************************
@ -1868,7 +1870,7 @@ static int stm32_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t arg)
cmdidx = (cmd & MMCSD_CMDIDX_MASK) >> MMCSD_CMDIDX_SHIFT;
regval |= cmdidx | SDIO_CMD_CPSMEN;
mcinfo("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval);
// mcinfo("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval);
/* Write the SDIO CMD */
@ -2260,7 +2262,7 @@ static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t
putreg32(SDIO_RESPDONE_ICR | SDIO_CMDDONE_ICR, STM32_SDIO_ICR);
*rshort = getreg32(STM32_SDIO_RESP1);
mcinfo("data: %08x %08x\n", *rshort, respcmd);
// mcinfo("data: %08x %08x\n", *rshort, respcmd);
return ret;
}
@ -2361,20 +2363,12 @@ static int stm32_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *r
if (rshort)
{
*rshort = getreg32(STM32_SDIO_RESP1);
mcinfo("data: %08x\n", *rshort);
// mcinfo("data: %08x\n", *rshort);
}
return ret;
}
/* MMC responses not supported */
static int stm32_recvnotimpl(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *rnotimpl)
{
putreg32(SDIO_RESPDONE_ICR | SDIO_CMDDONE_ICR, STM32_SDIO_ICR);
return -ENOSYS;
}
/****************************************************************************
* Name: stm32_waitenable
*

7
config_wlan

@ -822,8 +822,12 @@ CONFIG_MMCSD_NSLOTS=1
CONFIG_ARCH_HAVE_SDIO=y
# CONFIG_SDIO_DMA is not set
CONFIG_ARCH_HAVE_SDIOWAIT_WRCOMPLETE=y
# CONFIG_MMCSD_SDIO is not set
CONFIG_MMCSD_SDIO=y
CONFIG_SDIO_PREFLIGHT=y
# CONFIG_SDIO_MUXBUS is not set
# CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE is not set
# CONFIG_SDIO_WIDTH_D1_ONLY is not set
CONFIG_SDIO_BLOCKSETUP=y
# CONFIG_MODEM is not set
# CONFIG_MTD is not set
# CONFIG_EEPROM is not set
@ -891,6 +895,7 @@ CONFIG_DRIVERS_WIRELESS=y
# CONFIG_DRIVERS_IEEE802154 is not set
CONFIG_DRIVERS_IEEE80211=y
CONFIG_IEEE80211_BROADCOM_FULLMAC=y
CONFIG_IEEE80211_BROADCOM_BCM43362=y
CONFIG_IEEE80211_BROADCOM_FULLMAC_SDIO=y
# CONFIG_WL_NRF24L01 is not set
# CONFIG_DRIVERS_CONTACTLESS is not set

10
configs/photon/scripts/photon_dfu.ld

@ -61,6 +61,16 @@ SECTIONS
*(.text .text.*)
*(.fixup)
*(.gnu.warning)
. = ALIGN(0x4);
wlan_firmware_image_location = .;
*(.wlan_firmware_image .wlan_firmware_image.*)
wlan_firmware_image_end = .;
. = ALIGN(0x4);
wlan_nvram_image_location = .;
*(.wlan_nvram_image .wlan_nvram_image.*)
wlan_nvram_image_end = .;
*(.rodata .rodata.*)
*(.gnu.linkonce.t.*)
*(.glue_7)

1
configs/photon/src/Makefile

@ -55,6 +55,7 @@ endif
ifeq ($(CONFIG_PHOTON_WLAN),y)
CSRCS += stm32_wlan.c
CSRCS += stm32_wlan_firmware.c
endif
ifeq ($(CONFIG_STM32_OTGHS),y)

10
configs/photon/src/stm32_wlan.c

@ -99,20 +99,18 @@ void bcmf_board_initialize(int minor)
* Name: bcmf_board_setup_oob_irq
****************************************************************************/
void bcmf_board_setup_oob_irq(int minor)
void bcmf_board_setup_oob_irq(int minor, xcpt_t func, void *arg)
{
if (minor != SDIO_WLAN0_MINOR)
{
return;
}
/* Configure reset pin */
/* Configure interrupt pin */
stm32_configgpio(GPIO_WLAN0_RESET);
stm32_configgpio(GPIO_WLAN0_OOB_INT);
/* Put wlan chip in reset state */
bcmf_board_reset(minor, true);
stm32_gpiosetevent(GPIO_WLAN0_OOB_INT, true, false, false, func, arg);
}
/****************************************************************************

17650
configs/photon/src/stm32_wlan_firmware.c Normal file

File diff suppressed because it is too large Load Diff

5
drivers/wireless/ieee80211/Kconfig

@ -8,6 +8,11 @@ if DRIVERS_IEEE80211
config IEEE80211_BROADCOM_FULLMAC
bool
config IEEE80211_BROADCOM_BCM43362
bool "Broadcom 43362 chip support"
depends on IEEE80211_BROADCOM_FULLMAC
default n
config IEEE80211_BROADCOM_FULLMAC_SDIO
bool "Broadcom FullMAC driver on SDIO bus"
depends on ARCH_HAVE_SDIO

5
drivers/wireless/ieee80211/Make.defs

@ -42,9 +42,14 @@ ifeq ($(CONFIG_DRIVERS_IEEE80211),y)
ifeq ($(CONFIG_IEEE80211_BROADCOM_FULLMAC_SDIO),y)
CSRCS += bcmf_sdio.c
CSRCS += bcmf_core.c
CSRCS += mmc_sdio.c
endif
ifeq ($(CONFIG_IEEE80211_BROADCOM_BCM43362),y)
CSRCS += bcmf_chip_43362.c
endif
# Include IEEE 802.11 build support
DEPPATH += --dep-path wireless$(DELIM)ieee80211

164
drivers/wireless/ieee80211/bcm43362_constants.h Normal file

@ -0,0 +1,164 @@
/*
* Copyright (c) 2015 Broadcom
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* 3. Neither the name of Broadcom nor the names of other contributors to this
* software may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* 4. This software may not be used as a standalone product, and may only be used as
* incorporated in your product or device that incorporates Broadcom wireless connectivity
* products and solely for the purpose of enabling the functionalities of such Broadcom products.
*
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY WARRANTIES OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT, ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef BCM43362_CONSTANTS_H_
#define BCM43362_CONSTANTS_H_
/******************************************************
* Architecture Constants
******************************************************/
/* General chip stats */
#define CHIP_RAM_SIZE 0x3C000
/* Backplane architecture */
#define CHIPCOMMON_BASE_ADDRESS 0x18000000 /* Chipcommon core register region */
#define DOT11MAC_BASE_ADDRESS 0x18001000 /* dot11mac core register region */
#define SDIO_BASE_ADDRESS 0x18002000 /* SDIOD Device core register region */
#define WLAN_ARMCM3_BASE_ADDRESS 0x18003000 /* ARMCM3 core register region */
#define SOCSRAM_BASE_ADDRESS 0x18004000 /* SOCSRAM core register region */
#define BACKPLANE_ADDRESS_MASK 0x7FFF
#define CHIP_STA_INTERFACE 0
#define CHIP_AP_INTERFACE 1
#define CHIP_P2P_INTERFACE 2
/* Maximum value of bus data credit difference */
#define CHIP_MAX_BUS_DATA_CREDIT_DIFF 7
/* Chipcommon registers */
#define CHIPCOMMON_GPIO_CONTROL ((uint32_t) (CHIPCOMMON_BASE_ADDRESS + 0x6C) )
/******************************************************
* SDIO Constants
******************************************************/
/* CurrentSdiodProgGuide r23 */
/* Base registers */
#define SDIO_CORE ((uint32_t) (SDIO_BASE_ADDRESS + 0x00) )
#define SDIO_INT_STATUS ((uint32_t) (SDIO_BASE_ADDRESS + 0x20) )
#define SDIO_TO_SB_MAILBOX ((uint32_t) (SDIO_BASE_ADDRESS + 0x40) )
#define SDIO_TO_SB_MAILBOX_DATA ((uint32_t) (SDIO_BASE_ADDRESS + 0x48) )
#define SDIO_TO_HOST_MAILBOX_DATA ((uint32_t) (SDIO_BASE_ADDRESS + 0x4C) )
#define SDIO_TO_SB_MAIL_BOX ((uint32_t) (SDIO_BASE_ADDRESS + 0x40) )
#define SDIO_INT_HOST_MASK ((uint32_t) (SDIO_BASE_ADDRESS + 0x24) )
#define SDIO_FUNCTION_INT_MASK ((uint32_t) (SDIO_BASE_ADDRESS + 0x34) )
/* SDIO Function 0 (SDIO Bus) register addresses */
/* SDIO Device CCCR offsets */
/* TODO: What does CIS/CCCR stand for? */
/* CCCR accesses do not require backpane clock */
#define SDIOD_CCCR_UHS_I ( (uint32_t) 0x14 ) /* UHS-I Support */
#define SDIOD_CCCR_DRIVE ( (uint32_t) 0x15 ) /* Drive Strength */
#define SDIOD_CCCR_INTEXT ( (uint32_t) 0x16 ) /* Interrupt Extension */
#define SDIOD_SEP_INT_CTL ( (uint32_t) 0xF2 ) /* Separate Interrupt Control*/
#define SDIOD_CCCR_F1INFO ( (uint32_t) 0x100 ) /* Function 1 (Backplane) Info */
#define SDIOD_CCCR_F1HP ( (uint32_t) 0x102 ) /* Function 1 (Backplane) High Power */
#define SDIOD_CCCR_F1CISPTR_0 ( (uint32_t) 0x109 ) /* Function 1 (Backplane) CIS Base Address Pointer Register 0 (LSB) */
#define SDIOD_CCCR_F1CISPTR_1 ( (uint32_t) 0x10A ) /* Function 1 (Backplane) CIS Base Address Pointer Register 1 */
#define SDIOD_CCCR_F1CISPTR_2 ( (uint32_t) 0x10B ) /* Function 1 (Backplane) CIS Base Address Pointer Register 2 (MSB - only bit 1 valid) */
#define SDIOD_CCCR_F1BLKSIZE_0 ( (uint32_t) 0x110 ) /* Function 1 (Backplane) SDIO Block Size Register 0 (LSB) */
#define SDIOD_CCCR_F1BLKSIZE_1 ( (uint32_t) 0x111 ) /* Function 1 (Backplane) SDIO Block Size Register 1 (MSB) */
#define SDIOD_CCCR_F2INFO ( (uint32_t) 0x200 ) /* Function 2 (WLAN Data FIFO) Info */
#define SDIOD_CCCR_F2HP ( (uint32_t) 0x202 ) /* Function 2 (WLAN Data FIFO) High Power */
#define SDIOD_CCCR_F2CISPTR_0 ( (uint32_t) 0x209 ) /* Function 2 (WLAN Data FIFO) CIS Base Address Pointer Register 0 (LSB) */
#define SDIOD_CCCR_F2CISPTR_1 ( (uint32_t) 0x20A ) /* Function 2 (WLAN Data FIFO) CIS Base Address Pointer Register 1 */
#define SDIOD_CCCR_F2CISPTR_2 ( (uint32_t) 0x20B ) /* Function 2 (WLAN Data FIFO) CIS Base Address Pointer Register 2 (MSB - only bit 1 valid) */
#define SDIOD_CCCR_F2BLKSIZE_0 ( (uint32_t) 0x210 ) /* Function 2 (WLAN Data FIFO) SDIO Block Size Register 0 (LSB) */
#define SDIOD_CCCR_F2BLKSIZE_1 ( (uint32_t) 0x211 ) /* Function 2 (WLAN Data FIFO) SDIO Block Size Register 1 (MSB) */
#define SDIOD_CCCR_F3INFO ( (uint32_t) 0x300 ) /* Function 3 (Bluetooth Data FIFO) Info */
#define SDIOD_CCCR_F3HP ( (uint32_t) 0x302 ) /* Function 3 (Bluetooth Data FIFO) High Power */
#define SDIOD_CCCR_F3CISPTR_0 ( (uint32_t) 0x309 ) /* Function 3 (Bluetooth Data FIFO) CIS Base Address Pointer Register 0 (LSB) */
#define SDIOD_CCCR_F3CISPTR_1 ( (uint32_t) 0x30A ) /* Function 3 (Bluetooth Data FIFO) CIS Base Address Pointer Register 1 */
#define SDIOD_CCCR_F3CISPTR_2 ( (uint32_t) 0x30B ) /* Function 3 (Bluetooth Data FIFO) CIS Base Address Pointer Register 2 (MSB - only bit 1 valid) */
#define SDIOD_CCCR_F3BLKSIZE_0 ( (uint32_t) 0x310 ) /* Function 3 (Bluetooth Data FIFO) SDIO Block Size Register 0 (LSB) */
#define SDIOD_CCCR_F3BLKSIZE_1 ( (uint32_t) 0x311 ) /* Function 3 (Bluetooth Data FIFO) SDIO Block Size Register 1 (MSB) */
/* SDIO Function 1 (Backplane) register addresses */
/* Addresses 0x00000000 - 0x0000FFFF are directly access the backplane
* throught the backplane window. Addresses above 0x0000FFFF are
* registers relating to backplane access, and do not require a backpane
* clock to access them
*/
#define SDIO_GPIO_SELECT ( (uint32_t) 0x10005 )
#define SDIO_GPIO_OUTPUT ( (uint32_t) 0x10006 )
#define SDIO_GPIO_ENABLE ( (uint32_t) 0x10007 )
#define SDIO_FUNCTION2_WATERMARK ( (uint32_t) 0x10008 )
#define SDIO_DEVICE_CONTROL ( (uint32_t) 0x10009 )
#define SDIO_BACKPLANE_ADDRESS_LOW ( (uint32_t) 0x1000A )
#define SDIO_BACKPLANE_ADDRESS_MID ( (uint32_t) 0x1000B )
#define SDIO_BACKPLANE_ADDRESS_HIGH ( (uint32_t) 0x1000C )
#define SDIO_FRAME_CONTROL ( (uint32_t) 0x1000D )
#define SDIO_CHIP_CLOCK_CSR ( (uint32_t) 0x1000E )
#define SDIO_PULL_UP ( (uint32_t) 0x1000F )
#define SDIO_READ_FRAME_BC_LOW ( (uint32_t) 0x1001B )
#define SDIO_READ_FRAME_BC_HIGH ( (uint32_t) 0x1001C )
#define I_HMB_SW_MASK ( (uint32_t) 0x000000F0 )
#define I_HMB_FRAME_IND ( 1<<6 )
#define FRAME_AVAILABLE_MASK I_HMB_SW_MASK
/******************************************************
* Bit Masks
******************************************************/
/* SDIO_FRAME_CONTROL Bits */
#define SFC_RF_TERM ( (uint32_t) (1 << 0) ) /* Read Frame Terminate */
#define SFC_WF_TERM ( (uint32_t) (1 << 1) ) /* Write Frame Terminate */
#define SFC_CRC4WOOS ( (uint32_t) (1 << 2) ) /* HW reports CRC error for write out of sync */
#define SFC_ABORTALL ( (uint32_t) (1 << 3) ) /* Abort cancels all in-progress frames */
/* SDIO_TO_SB_MAIL_BOX bits corresponding to intstatus bits */
#define SMB_NAK ( (uint32_t) (1 << 0) ) /* To SB Mailbox Frame NAK */
#define SMB_INT_ACK ( (uint32_t) (1 << 1) ) /* To SB Mailbox Host Interrupt ACK */
#define SMB_USE_OOB ( (uint32_t) (1 << 2) ) /* To SB Mailbox Use OOB Wakeup */
#define SMB_DEV_INT ( (uint32_t) (1 << 3) ) /* To SB Mailbox Miscellaneous Interrupt */
#define WL_CHANSPEC_BAND_MASK (0xf000)
#define WL_CHANSPEC_BAND_5G (0x1000)
#define WL_CHANSPEC_BAND_2G (0x2000)
#define WL_CHANSPEC_CTL_SB_MASK (0x0300)
#define WL_CHANSPEC_CTL_SB_LOWER (0x0100)
#define WL_CHANSPEC_CTL_SB_UPPER (0x0200)
#define WL_CHANSPEC_CTL_SB_NONE (0x0300)
#define WL_CHANSPEC_BW_MASK (0x0C00)
#define WL_CHANSPEC_BW_10 (0x0400)
#define WL_CHANSPEC_BW_20 (0x0800)
#define WL_CHANSPEC_BW_40 (0x0C00)
#endif /* ifndef BCM43362_CONSTANTS_H_ */

28
drivers/wireless/ieee80211/bcmf_chip_43362.c Normal file

@ -0,0 +1,28 @@
#include "bcmf_chip_43362.h"
#include "bcm43362_constants.h"
#include <stdint.h>
#include <debug.h>
#include "bcmf_sdio_core.h"
#define WRAPPER_REGISTER_OFFSET (0x100000)
uint32_t bcmf_43362_get_core_base_address(unsigned int core)
{
switch (core)
{
case CHIPCOMMON_CORE_ID:
return CHIPCOMMON_BASE_ADDRESS;
case DOT11MAC_CORE_ID:
return DOT11MAC_BASE_ADDRESS;
case SDIOD_CORE_ID:
return SDIO_BASE_ADDRESS;
case WLAN_ARMCM3_CORE_ID:
return WLAN_ARMCM3_BASE_ADDRESS + WRAPPER_REGISTER_OFFSET;
case SOCSRAM_CORE_ID:
return SOCSRAM_BASE_ADDRESS + WRAPPER_REGISTER_OFFSET;
default:
_err("Invalid core id %d\n", core);
}
return 0;
}

8
drivers/wireless/ieee80211/bcmf_chip_43362.h Normal file

@ -0,0 +1,8 @@
#ifndef __DRIVERS_WIRELESS_IEEE80211_BCM_CHIP_43362_H
#define __DRIVERS_WIRELESS_IEEE80211_BCM_CHIP_43362_H
#include <stdint.h>
uint32_t bcmf_43362_get_core_base_address(unsigned int core);
#endif /* __DRIVERS_WIRELESS_IEEE80211_BCM_CHIP_43362_H */

390
drivers/wireless/ieee80211/bcmf_core.c Normal file

@ -0,0 +1,390 @@
/****************************************************************************
* drivers/wireless/ieee80211/bcmf_core.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Simon Piriou <spiriou31@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/compiler.h>
#include <debug.h>
#include <errno.h>
#include <nuttx/arch.h>
#include "bcmf_core.h"
#include "bcmf_sdio.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Agent registers (common for every core) */
#define BCMA_IOCTL 0x0408 /* IO control */
#define BCMA_IOST 0x0500 /* IO status */
#define BCMA_RESET_CTL 0x0800 /* Reset control */
#define BCMA_RESET_ST 0x0804
#define BCMA_IOCTL_CLK 0x0001
#define BCMA_IOCTL_FGC 0x0002
#define BCMA_IOCTL_CORE_BITS 0x3FFC
#define BCMA_IOCTL_PME_EN 0x4000
#define BCMA_IOCTL_BIST_EN 0x8000
#define BCMA_IOST_CORE_BITS 0x0FFF
#define BCMA_IOST_DMA64 0x1000
#define BCMA_IOST_GATED_CLK 0x2000
#define BCMA_IOST_BIST_ERROR 0x4000
#define BCMA_IOST_BIST_DONE 0x8000
#define BCMA_RESET_CTL_RESET 0x0001
/* Transfer size properties */
#define BCMF_UPLOAD_TRANSFER_SIZE (64 * 256)
// TODO move in chip configuration data
#define CHIP_RAM_SIZE 0x3C000
extern const char bcmf_nvram_image[];
extern const unsigned int bcmf_nvram_image_len;
extern const uint8_t bcmf_firmware_image[];
extern const unsigned int bcmf_firmware_image_len;
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
static int bcmf_core_set_backplane_window(FAR struct bcmf_dev_s *priv,
uint32_t address);
static int bcmf_upload_binary(FAR struct bcmf_dev_s *priv,
uint32_t address, uint8_t *buf,
unsigned int len);
static int bcmf_upload_nvram(FAR struct bcmf_dev_s *priv);
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
int bcmf_core_set_backplane_window(FAR struct bcmf_dev_s *priv, uint32_t address)
{
int ret;
int i;
address &= ~SBSDIO_SB_OFT_ADDR_MASK;
for (i = 1; i < 4; i++)
{
uint8_t addr_part = (address >> (8*i)) & 0xff;
uint8_t cur_addr_part = (priv->backplane_current_addr >> (8*i)) & 0xff;
if (addr_part != cur_addr_part)
{
/* Update current backplane base address */
ret = bcmf_write_reg(priv, 1, SBSDIO_FUNC1_SBADDRLOW+i-1,
addr_part);
if (ret != OK)
{
return ret;
}
priv->backplane_current_addr &= ~(0xff << (8*i));
priv->backplane_current_addr |= addr_part << (8*i);
}
}
return OK;
}
int bcmf_upload_binary(FAR struct bcmf_dev_s *priv, uint32_t address,
uint8_t *buf, unsigned int len)
{
unsigned int size;
while (len > 0)
{
/* Set the backplane window to include the start address */
int ret = bcmf_core_set_backplane_window(priv, address);
if (ret != OK)
{
return ret;
}
if (len > BCMF_UPLOAD_TRANSFER_SIZE)
{
size = BCMF_UPLOAD_TRANSFER_SIZE;
}
else
{
size = len;
}
/* Transfer firmware data */
ret = bcmf_transfer_bytes(priv, true, 1,
address & SBSDIO_SB_OFT_ADDR_MASK, buf, size);
if (ret != OK)
{
_err("transfer failed %d %x %d\n", ret, address, size);
return ret;
}
len -= size;
address += size;
buf += size;
}
return OK;
}
int bcmf_upload_nvram(FAR struct bcmf_dev_s *priv)
{
int ret;
uint32_t nvram_sz;
uint32_t token;
/* Round up the size of the image */
nvram_sz = (bcmf_nvram_image_len + 63) & (-64);
_info("nvram size is %d %d bytes\n", nvram_sz, bcmf_nvram_image_len);
/* Write image */
ret = bcmf_upload_binary(priv, CHIP_RAM_SIZE - 4 - nvram_sz,
(uint8_t*)bcmf_nvram_image, bcmf_nvram_image_len);
if ( ret != OK)
{
return ret;
}
/* generate length token */
token = nvram_sz / 4;
token = (~token << 16) | (token & 0x0000FFFF);
/* Write the length token to the last word */
ret = bcmf_write_sbreg(priv, CHIP_RAM_SIZE - 4, (uint8_t*)&token, 4);
if ( ret != OK)
{
return ret;
}
return OK;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: bcmf_read_sbreg
****************************************************************************/
int bcmf_read_sbreg(FAR struct bcmf_dev_s *priv, uint32_t address,
uint8_t *reg, unsigned int len)
{
int ret = bcmf_core_set_backplane_window(priv, address);
if (ret != OK)
{
return ret;
}
return bcmf_transfer_bytes(priv, false, 1,
address & SBSDIO_SB_OFT_ADDR_MASK, reg, len);
}
/****************************************************************************
* Name: bcmf_write_sbreg
****************************************************************************/
int bcmf_write_sbreg(FAR struct bcmf_dev_s *priv, uint32_t address,
uint8_t *reg, unsigned int len)
{
int ret = bcmf_core_set_backplane_window(priv, address);
if (ret != OK)
{
return ret;
}
return bcmf_transfer_bytes(priv, true, 1, address & SBSDIO_SB_OFT_ADDR_MASK,
reg, len);
}
/****************************************************************************
* Name: bcmf_core_upload_firmware
****************************************************************************/
int bcmf_core_upload_firmware(FAR struct bcmf_dev_s *priv)
{
int ret;
_info("upload firmware\n");
/* Disable ARMCM3 core and reset SOCRAM core
* to set device in firmware upload mode */
bcmf_core_disable(priv, WLAN_ARMCM3_CORE_ID);
bcmf_core_reset(priv, SOCSRAM_CORE_ID);
up_mdelay(50);
/* Flash chip firmware */
_info("firmware size is %d bytes\n", bcmf_firmware_image_len);
ret = bcmf_upload_binary(priv, 0, (uint8_t*)bcmf_firmware_image,
bcmf_firmware_image_len);
if (ret != OK)
{
_err("Failed to upload firmware\n");
return ret;
}
/* Flash NVRAM configuration file */
_info("upload nvram configuration\n");
ret = bcmf_upload_nvram(priv);
if (ret != OK)
{
_err("Failed to upload nvram\n");
return ret;
}
/* Firmware upload done, restart ARMCM3 core */
up_mdelay(10);
bcmf_core_reset(priv, WLAN_ARMCM3_CORE_ID);
/* Check ARMCM3 core is running */
up_mdelay(10);
if (!bcmf_core_isup(priv, WLAN_ARMCM3_CORE_ID))
{
_err("Cannot start ARMCM3 core\n");
return -ETIMEDOUT;
}
return OK;
}
bool bcmf_core_isup(FAR struct bcmf_dev_s *priv, unsigned int core)
{
uint32_t value = 0;
uint32_t base = priv->get_core_base_address(core);
bcmf_read_sbregw(priv, base + BCMA_IOCTL, &value);
if ((value & (BCMA_IOCTL_FGC | BCMA_IOCTL_CLK)) != BCMA_IOCTL_CLK)
{
return false;
}
bcmf_read_sbregw(priv, base + BCMA_RESET_CTL, &value);
return (value & BCMA_RESET_CTL_RESET) == 0;
}
void bcmf_core_disable(FAR struct bcmf_dev_s *priv, unsigned int core)
{
uint8_t value;
uint32_t base = priv->get_core_base_address(core);
/* Check if core is already in reset state */
bcmf_read_sbregb(priv, base + BCMA_RESET_CTL, &value);
if ((value & BCMA_RESET_CTL_RESET) != 0)
{
/* Core already disabled */
return;
}
/* Ensure no backplane operation is pending */
up_mdelay(10);
/* Set core in reset state */
bcmf_write_sbregb(priv, base + BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
up_udelay(1);
/* Write 0 to the IO control and read it back */
bcmf_write_sbregb(priv, base + BCMA_IOCTL, 0);
bcmf_read_sbregb(priv, base + BCMA_IOCTL, &value);
up_udelay(10);
}
void bcmf_core_reset(FAR struct bcmf_dev_s *priv, unsigned int core)
{
uint32_t value;
uint32_t base = priv->get_core_base_address(core);
/* Put core in reset state */
bcmf_core_disable(priv, core);
/* Run initialization sequence */
bcmf_write_sbregb(priv, base + BCMA_IOCTL, BCMA_IOCTL_FGC | BCMA_IOCTL_CLK);
bcmf_read_sbregw(priv, base + BCMA_IOCTL, &value);
bcmf_write_sbregb(priv, base + BCMA_RESET_CTL, 0);
bcmf_read_sbregw(priv, base + BCMA_RESET_CTL, &value);
up_udelay(1);
bcmf_write_sbregb(priv, base + BCMA_IOCTL, BCMA_IOCTL_CLK);
bcmf_read_sbregw(priv, base + BCMA_IOCTL, &value);
up_udelay(1);
}

83
drivers/wireless/ieee80211/bcmf_core.h Normal file

@ -0,0 +1,83 @@
/****************************************************************************
* drivers/wireless/ieee80211/bcmf_core.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Simon Piriou <spiriou31@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __DRIVERS_WIRELESS_IEEE80211_BCMF_CORE_H
#define __DRIVERS_WIRELESS_IEEE80211_BCMF_CORE_H
#include <stdint.h>
#include <stdbool.h>
#include "bcmf_driver.h"
int bcmf_read_sbreg(FAR struct bcmf_dev_s *priv, uint32_t address,
uint8_t *reg, unsigned int len);
int bcmf_write_sbreg(FAR struct bcmf_dev_s *priv, uint32_t address,
uint8_t *reg, unsigned int len);
bool bcmf_core_isup(FAR struct bcmf_dev_s *priv, unsigned int core);
void bcmf_core_disable(FAR struct bcmf_dev_s *priv, unsigned int core);
void bcmf_core_reset(FAR struct bcmf_dev_s *priv, unsigned int core);
int bcmf_core_upload_firmware(FAR struct bcmf_dev_s *priv);
static inline int bcmf_read_sbregb(FAR struct bcmf_dev_s *priv,
uint32_t address, uint8_t *reg)
{
return bcmf_read_sbreg(priv, address, reg, 1);
}
static inline int bcmf_read_sbregw(FAR struct bcmf_dev_s *priv,
uint32_t address, uint32_t *reg)
{
return bcmf_read_sbreg(priv, address, (uint8_t*)reg, 4);
}
static inline int bcmf_write_sbregb(FAR struct bcmf_dev_s *priv,
uint32_t address, uint8_t reg)
{
return bcmf_write_sbreg(priv, address, &reg, 1);
}
static inline int bcmf_write_sbregw(FAR struct bcmf_dev_s *priv,
uint32_t address, uint32_t reg)
{
return bcmf_write_sbreg(priv, address, (uint8_t*)&reg, 4);
}
#endif /* __DRIVERS_WIRELESS_IEEE80211_BCMF_CORE_H */

54
drivers/wireless/ieee80211/bcmf_driver.h Normal file

@ -0,0 +1,54 @@
/****************************************************************************
* drivers/wireless/ieee80211/bcmf_driver.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Simon Piriou <spiriou31@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __DRIVERS_WIRELESS_IEEE80211_BCMF_DRIVER_H
#define __DRIVERS_WIRELESS_IEEE80211_BCMF_DRIVER_H
#include <nuttx/sdio.h>
/* This structure contains the unique state of the Broadcom FullMAC driver */
struct bcmf_dev_s
{
FAR struct sdio_dev_s *sdio_dev; /* The SDIO device bound to this instance */
int minor; /* Device minor number */
uint32_t backplane_current_addr; /* Current function 1 backplane base addr */
uint32_t (*get_core_base_address)(unsigned int core); /* Get chip specific
base address for evey cores */
};
#endif /* __DRIVERS_WIRELESS_IEEE80211_BCMF_DRIVER_H */

411
drivers/wireless/ieee80211/bcmf_sdio.c

@ -54,7 +54,8 @@
#include <nuttx/wireless/ieee80211/bcmf_sdio.h>
#include <nuttx/wireless/ieee80211/bcmf_board.h>
#include "chip_constants.h"
#include "bcmf_sdio.h"
#include "bcmf_core.h"
/****************************************************************************
* Pre-processor Definitions
@ -64,66 +65,20 @@
#define BCMF_DEVICE_START_DELAY_MS 10
#define BCMF_CLOCK_SETUP_DELAY_MS 500
/* Agent registers (common for every core) */
#define BCMA_IOCTL 0x0408 /* IO control */
#define BCMA_IOST 0x0500 /* IO status */
#define BCMA_RESET_CTL 0x0800 /* Reset control */
#define BCMA_RESET_ST 0x0804
#define BCMA_IOCTL_CLK 0x0001
#define BCMA_IOCTL_FGC 0x0002
#define BCMA_IOCTL_CORE_BITS 0x3FFC
#define BCMA_IOCTL_PME_EN 0x4000
#define BCMA_IOCTL_BIST_EN 0x8000
#define BCMA_IOST_CORE_BITS 0x0FFF
#define BCMA_IOST_DMA64 0x1000
#define BCMA_IOST_GATED_CLK 0x2000
#define BCMA_IOST_BIST_ERROR 0x4000
#define BCMA_IOST_BIST_DONE 0x8000
#define BCMA_RESET_CTL_RESET 0x0001
/****************************************************************************
* Private Types
****************************************************************************/
/* This structure contains the unique state of the Broadcom FullMAC driver */
struct bcmf_dev_s
{
FAR struct sdio_dev_s *sdio_dev; /* The SDIO device bound to this instance */
int minor; /* Device minor number */
uint32_t backplane_current_addr; /* Current function 1 backplane base addr */
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
static int bcmf_transfer_bytes(FAR struct bcmf_dev_s *priv, bool write,
uint8_t function, uint32_t address,
uint8_t *buf, unsigned int len);
static int bcmf_read_reg(FAR struct bcmf_dev_s *priv, uint8_t function,
uint32_t address, uint8_t *reg);
static int bcmf_write_reg(FAR struct bcmf_dev_s *priv, uint8_t function,
uint32_t address, uint8_t reg);
static int bcmf_read_sbreg(FAR struct bcmf_dev_s *priv, uint32_t address,
uint32_t *reg);
static int bcmf_write_sbreg(FAR struct bcmf_dev_s *priv, uint32_t address,
uint32_t reg);
static int bcmf_probe(FAR struct bcmf_dev_s *priv);
static int bcmf_hwinitialize(FAR struct bcmf_dev_s *priv);
static void bcmf_hwuninitialize(FAR struct bcmf_dev_s *priv);
static int bcmf_chipinitialize(FAR struct bcmf_dev_s *priv);
static int bcmf_set_backplane_window(FAR struct bcmf_dev_s *priv, uint32_t addr);
static int bcmf_oob_irq(int irq, FAR void *context, FAR void *arg);
/****************************************************************************
* Private Data
@ -133,80 +88,10 @@ static int bcmf_set_backplane_window(FAR struct bcmf_dev_s *priv, uint32_t addr
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: bcmf_transfer_bytes
****************************************************************************/
int bcmf_transfer_bytes(FAR struct bcmf_dev_s *priv, bool write,
uint8_t function, uint32_t address,
uint8_t *buf, unsigned int len)
int bcmf_oob_irq(int irq, FAR void *context, FAR void *arg)
{
/* Use rw_io_direct method if len is 1 */
if (len == 1)
{
return sdio_io_rw_direct(priv->sdio_dev, write,
function, address, *buf, buf);
}
return sdio_io_rw_extended(priv->sdio_dev, write,
function, address, true, buf, len, 1);
// return -EINVAL;
}
/****************************************************************************
* Name: bcmf_read_reg
****************************************************************************/
int bcmf_read_reg(FAR struct bcmf_dev_s *priv, uint8_t function,
uint32_t address, uint8_t *reg)
{
return bcmf_transfer_bytes(priv, false, function, address, reg, 1);
}
/****************************************************************************
* Name: bcmf_write_reg
****************************************************************************/
int bcmf_write_reg(FAR struct bcmf_dev_s *priv, uint8_t function,
uint32_t address, uint8_t reg)
{
return bcmf_transfer_bytes(priv, true, function, address, &reg, 1);
}
/****************************************************************************
* Name: bcmf_read_sbreg
****************************************************************************/
int bcmf_read_sbreg(FAR struct bcmf_dev_s *priv, uint32_t address,
uint32_t *reg)
{
int ret = bcmf_set_backplane_window(priv, address);
if (ret != OK)
{
return ret;
}
return bcmf_transfer_bytes(priv, false, 1, address, (uint8_t*)reg, 4);
}
/****************************************************************************
* Name: bcmf_write_sbreg
****************************************************************************/
int bcmf_write_sbreg(FAR struct bcmf_dev_s *priv, uint32_t address,
uint32_t reg)
{
int ret = bcmf_set_backplane_window(priv, address);
if (ret != OK)
{
return ret;
}
return bcmf_transfer_bytes(priv, true, 1, address,
(uint8_t*)&reg, 4);
/* TODO */
return OK;
}
/****************************************************************************
@ -217,7 +102,6 @@ int bcmf_probe(FAR struct bcmf_dev_s *priv)
{
int ret;
uint8_t value;
int loops;
/* Probe sdio card compatible device */
@ -227,14 +111,6 @@ int bcmf_probe(FAR struct bcmf_dev_s *priv)
goto exit_error;
}
/* Enable bus FN1 */
ret = sdio_enable_function(priv->sdio_dev, 1);
if (ret != OK)
{
goto exit_error;
}
/* Set FN0 / FN1 / FN2 default block size */
ret = sdio_set_blocksize(priv->sdio_dev, 0, 64);
@ -257,8 +133,6 @@ int bcmf_probe(FAR struct bcmf_dev_s *priv)
/* Enable device interrupts for FN0, FN1 and FN2 */
// ret = sdio_io_rw_direct(priv->sdio_dev, true, 0, SDIO_CCCR_INTEN,
// (1 << 0) | (1 << 1) | (1 << 2), NULL);
ret = bcmf_write_reg(priv, 0, SDIO_CCCR_INTEN,
(1 << 0) | (1 << 1) | (1 << 2));
if (ret != OK)
@ -266,41 +140,20 @@ int bcmf_probe(FAR struct bcmf_dev_s *priv)
goto exit_error;
}
/* Default device clock speed is up to 25 Mhz
* We could set EHS bit to operate at a clock rate up to 50 Mhz */
SDIO_CLOCK(priv->sdio_dev, CLOCK_SD_TRANSFER_4BIT);
up_mdelay(BCMF_CLOCK_SETUP_DELAY_MS);
/* Wait for function 1 to be ready */
/* Enable bus FN1 */
loops = 10;
while (--loops > 0)
ret = sdio_enable_function(priv->sdio_dev, 1);
if (ret != OK)
{
up_mdelay(1);
// ret = sdio_io_rw_direct(priv->sdio_dev, false, 0, SDIO_CCCR_IORDY, 0, &value);
ret = bcmf_read_reg(priv, 0, SDIO_CCCR_IORDY, &value);
if (ret != OK)
{
return ret;
}
if (value & (1 << 1))
{
/* Function 1 is ready */
break;
}
goto exit_error;
}
if (loops <= 0)
{
return -ETIMEDOUT;
}
_info("sdio fn1 ready\n");
return OK;
exit_error:
@ -313,14 +166,15 @@ exit_error:
* Name: bcmf_businitialize
****************************************************************************/
int bcmf_businitialize(FAR struct bcmf_dev_s *priv)
int bcmf_businitialize(FAR struct bcmf_dev_s *priv)
{
int ret;
int loops;
uint8_t value;
/* Send Active Low-Power clock request */
ret = bcmf_write_reg(priv, 1, SDIO_CHIP_CLOCK_CSR,
ret = bcmf_write_reg(priv, 1, SBSDIO_FUNC1_CHIPCLKCSR,
SBSDIO_FORCE_HW_CLKREQ_OFF |
SBSDIO_ALP_AVAIL_REQ |
SBSDIO_FORCE_ALP);
@ -333,10 +187,8 @@ exit_error:
loops = 10;
while (--loops > 0)
{
uint8_t value;
up_mdelay(10);
ret = bcmf_read_reg(priv, 1, SDIO_CHIP_CLOCK_CSR, &value);
ret = bcmf_read_reg(priv, 1, SBSDIO_FUNC1_CHIPCLKCSR, &value);
if (ret != OK)
{
@ -358,7 +210,7 @@ exit_error:
/* Clear Active Low-Power clock request */
ret = bcmf_write_reg(priv, 1, SDIO_CHIP_CLOCK_CSR, 0);
ret = bcmf_write_reg(priv, 1, SBSDIO_FUNC1_CHIPCLKCSR, 0);
if (ret != OK)
{
return ret;
@ -366,7 +218,7 @@ exit_error:
/* Disable pull-ups on SDIO cmd, d0-2 lines */
ret = bcmf_write_reg(priv, 1, SDIO_PULL_UP, 0);
ret = bcmf_write_reg(priv, 1, SBSDIO_FUNC1_SDIOPULLUP, 0);
if (ret != OK)
{
return ret;
@ -380,41 +232,87 @@ exit_error:
return ret;
}
// /* Enable function 2 */
// ret = sdio_enable_function(priv->sdio_dev, 2);
// if (ret != OK)
// {
// goto exit_error;
// }
// /* Enable out-of-band interrupt signal */
// ret = sdio_io_rw_direct(priv->sdio_dev, true, 0, SDIOD_SEP_INT_CTL,
// SEP_INTR_CTL_MASK | SEP_INTR_CTL_EN | SEP_INTR_CTL_POL, NULL);
// if (ret != OK)
// {
// return ret;
// }
// /* Enable function 2 interrupt */
// ret = sdio_enable_interrupt(priv->sdio_dev, 0);
// if (ret != OK)
// {
// return ret;
// }
// ret = sdio_enable_interrupt(priv->sdio_dev, 2);
// if (ret != OK)
// {
// return ret;
// }
// bcmf_board_setup_oob_irq(priv->minor, bcmf_oob_irq, (void*)priv);
/* Upload firmware */
_info("upload firmware\n");
ret = bcmf_core_upload_firmware(priv);
if (ret != OK)
{
return ret;
}
/* Enable FN2 (frame transfers) */
ret = sdio_enable_function(priv->sdio_dev, 2);
if (ret != OK)
{
return ret;
}
/* Configure gpio interrupt pin */
bcmf_board_setup_oob_irq(priv->minor, bcmf_oob_irq, (void*)priv);
/* Enable function 2 interrupt */
ret = sdio_enable_interrupt(priv->sdio_dev, 0);
if (ret != OK)
{
return ret;
}
ret = sdio_enable_interrupt(priv->sdio_dev, 2);
if (ret != OK)
{
return ret;
}
/* Redirect, configure and enable io for out-of-band interrupt signal */
ret = sdio_io_rw_direct(priv->sdio_dev, true, 0, SDIO_CCCR_BRCM_SEPINT,
SDIO_SEPINT_MASK | SDIO_SEPINT_OE | SDIO_SEPINT_ACT_HI, NULL);
if (ret != OK)
{
return ret;
}
_info("wait high throughput clock\n");
/* Wait for High Troughput clock to be sure function 2 is running */
loops = 10;
while (--loops > 0)
{
up_mdelay(10);
ret = bcmf_read_reg(priv, 1, SBSDIO_FUNC1_CHIPCLKCSR, &value);
if (ret != OK)
{
return ret;
}
if (value & SBSDIO_HT_AVAIL)
{
/* High Throughput clock is ready */
break;
}
}
if (loops <= 0)
{
_err("HT clock not ready\n");
return -ETIMEDOUT;
}
/* FN2 successfully enabled, set core and enable interrupts */
bcmf_write_sbregw(priv,
CORE_BUS_REG(priv->get_core_base_address(SDIOD_CORE_ID),
hostintmask), I_HMB_SW_MASK);
bcmf_write_sbregb(priv,
CORE_BUS_REG(priv->get_core_base_address(SDIOD_CORE_ID),
funcintmask), 2);
bcmf_write_reg(priv, 1, SBSDIO_WATERMARK, 8);
return OK;
}
@ -467,6 +365,76 @@ void bcmf_hwuninitialize(FAR struct bcmf_dev_s *priv)
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: bcmf_transfer_bytes
****************************************************************************/
int bcmf_transfer_bytes(FAR struct bcmf_dev_s *priv, bool write,
uint8_t function, uint32_t address,
uint8_t *buf, unsigned int len)
{
/* Use rw_io_direct method if len is 1 */
if (len == 1)
{
if (write)
{
return sdio_io_rw_direct(priv->sdio_dev, write,
function, address, *buf, NULL);
}
return sdio_io_rw_direct(priv->sdio_dev, write,
function, address, 0, buf);
}
/* Find best block size / count values for transfer */
unsigned int blocklen;
unsigned int nblocks;
if (len == 64 || len > 0 && len % 64 == 0)
{
blocklen = 64;
nblocks = len / 64;
}
else if (len > 20)
{
// FIXME
blocklen = 64;
nblocks = (len+63) / 64;
}
else
{
blocklen = len;
nblocks = 0;
}
// _info("try extended %d %d %d\n", len, blocklen, nblocks);
return sdio_io_rw_extended(priv->sdio_dev, write,
function, address, true, buf, blocklen, nblocks);
// return -EINVAL;
}
/****************************************************************************
* Name: bcmf_read_reg
****************************************************************************/
int bcmf_read_reg(FAR struct bcmf_dev_s *priv, uint8_t function,
uint32_t address, uint8_t *reg)
{
*reg = 0;
return bcmf_transfer_bytes(priv, false, function, address, reg, 1);
}
/****************************************************************************
* Name: bcmf_write_reg
****************************************************************************/
int bcmf_write_reg(FAR struct bcmf_dev_s *priv, uint8_t function,
uint32_t address, uint8_t reg)
{
return bcmf_transfer_bytes(priv, true, function, address, &reg, 1);
}
/****************************************************************************
* Name: bcmf_sdio_initialize
****************************************************************************/
@ -511,7 +479,7 @@ int bcmf_sdio_initialize(int minor, FAR struct sdio_dev_s *dev)
goto exit_uninit_hw;
}
/* Initialize device */
/* Initialize device bus */
ret = bcmf_businitialize(priv);
@ -520,7 +488,12 @@ int bcmf_sdio_initialize(int minor, FAR struct sdio_dev_s *dev)
goto exit_uninit_hw;
}
/* TODO Create a wlan device name and register network driver here */
/* FIXME wait for the chip to be ready to receive commands */
up_mdelay(100);
/* Device is up and running
TODO Create a wlan device name and register network driver here */
return OK;
@ -537,7 +510,7 @@ int bcmf_chipinitialize(FAR struct bcmf_dev_s *priv)
int ret;
uint32_t value = 0;
ret = bcmf_read_sbreg(priv, CHIPCOMMON_BASE_ADDRESS, &value);
ret = bcmf_read_sbregw(priv, SI_ENUM_BASE, &value);
if (ret != OK)
{
return ret;
@ -547,8 +520,9 @@ int bcmf_chipinitialize(FAR struct bcmf_dev_s *priv)
int chipid = value & 0xffff;
switch (chipid)
{
case BCM_43362_CHIP_ID:
_info("bcm43362 chip detected !!\n");
case SDIO_DEVICE_ID_BROADCOM_43362:
_info("bcm43362 chip detected\n");
priv->get_core_base_address = bcmf_43362_get_core_base_address;
break;
default:
_err("chip 0x%x is not supported\n", chipid);
@ -556,36 +530,3 @@ int bcmf_chipinitialize(FAR struct bcmf_dev_s *priv)
}
return OK;
}
int bcmf_set_backplane_window(FAR struct bcmf_dev_s *priv, uint32_t address)
{
int ret;
int i;
address &= ~BACKPLANE_ADDRESS_MASK;
for (i = 1; i < 4; i++)
{
uint8_t addr_part = (address >> (8*i)) & 0xff;
uint8_t cur_addr_part = (priv->backplane_current_addr >> (8*i)) & 0xff;
if (addr_part != cur_addr_part)
{
/* Update current backplane base address */
ret = bcmf_write_reg(priv, 1, SDIO_BACKPLANE_ADDRESS_LOW+i-1,
addr_part);
if (ret != OK)
{
return ret;
}
priv->backplane_current_addr &= ~(0xff << (8*i));
priv->backplane_current_addr |= addr_part << (8*i);
_info("update %d %08x\n", i, priv->backplane_current_addr);
}
}
return OK;
}

21
drivers/wireless/ieee80211/bcmf_sdio.h Normal file

@ -0,0 +1,21 @@
#ifndef __DRIVERS_WIRELESS_IEEE80211_BCMF_SDIO_H
#define __DRIVERS_WIRELESS_IEEE80211_BCMF_SDIO_H
#include "bcmf_sdio_regs.h"
#include "bcmf_sdio_core.h"
#include "bcmf_driver.h"
#include <stdint.h>
#include <stdbool.h>
int bcmf_transfer_bytes(FAR struct bcmf_dev_s *priv, bool write,
uint8_t function, uint32_t address,
uint8_t *buf, unsigned int len);
int bcmf_read_reg(FAR struct bcmf_dev_s *priv, uint8_t function,
uint32_t address, uint8_t *reg);
int bcmf_write_reg(FAR struct bcmf_dev_s *priv, uint8_t function,
uint32_t address, uint8_t reg);
#endif /* __DRIVERS_WIRELESS_IEEE80211_BCMF_SDIO_H */

214
drivers/wireless/ieee80211/bcmf_sdio_core.h Normal file

@ -0,0 +1,214 @@
/*
* Copyright (c) 2011 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef BCMF_SDIO_CHIP_H_
#define BCMF_SDIO_CHIP_H_
#include <stdint.h>
#ifndef PAD
#define _PADLINE(line) pad ## line
#define _XSTR(line) _PADLINE(line)
#define PAD _XSTR(__LINE__)
#endif
/* SDIO device ID */
#define SDIO_DEVICE_ID_BROADCOM_43143 43143
#define SDIO_DEVICE_ID_BROADCOM_43241 0x4324
#define SDIO_DEVICE_ID_BROADCOM_4329 0x4329
#define SDIO_DEVICE_ID_BROADCOM_4330 0x4330
#define SDIO_DEVICE_ID_BROADCOM_4334 0x4334
#define SDIO_DEVICE_ID_BROADCOM_4335_4339 0x4335
#define SDIO_DEVICE_ID_BROADCOM_43362 43362
/*
* Core reg address translation.
* Both macro's returns a 32 bits byte address on the backplane bus.
*/
#define CORE_CC_REG(base, field) \
(base + offsetof(struct chipcregs, field))
#define CORE_BUS_REG(base, field) \
(base + offsetof(struct sdpcmd_regs, field))
#define CORE_SB(base, field) \
(base + offsetof(struct sbconfig, field))
#define BRCMF_MAX_CORENUM 6
#define SI_ENUM_BASE 0x18000000 /* Enumeration space base */
/* Target state register description */
#define SSB_TMSLOW_RESET 0x00000001 /* Reset */
#define SSB_TMSLOW_REJECT 0x00000002 /* Reject (Standard Backplane) */
#define SSB_TMSLOW_REJECT_23 0x00000004 /* Reject (Backplane rev 2.3) */
#define SSB_TMSLOW_CLOCK 0x00010000 /* Clock Enable */
#define SSB_TMSLOW_FGC 0x00020000 /* Force Gated Clocks On */
#define SSB_TMSLOW_PE 0x40000000 /* Power Management Enable */
#define SSB_TMSLOW_BE 0x80000000 /* BIST Enable */
#define I_HMB_SW_MASK ( (uint32_t) 0x000000F0 )
enum {
CHIPCOMMON_CORE_ID,
DOT11MAC_CORE_ID,
SDIOD_CORE_ID,
WLAN_ARMCM3_CORE_ID,
SOCSRAM_CORE_ID
};
struct chip_core_info {
uint16_t id;
uint16_t rev;
uint32_t base;
uint32_t wrapbase;
uint32_t caps;
uint32_t cib;
};
struct sbconfig {
uint8_t PAD[0xf00];
uint32_t PAD[2];
uint32_t sbipsflag; /* initiator port ocp slave flag */
uint32_t PAD[3];
uint32_t sbtpsflag; /* target port ocp slave flag */
uint32_t PAD[11];
uint32_t sbtmerrloga; /* (sonics >= 2.3) */
uint32_t PAD;
uint32_t sbtmerrlog; /* (sonics >= 2.3) */
uint32_t PAD[3];
uint32_t sbadmatch3; /* address match3 */
uint32_t PAD;
uint32_t sbadmatch2; /* address match2 */
uint32_t PAD;
uint32_t sbadmatch1; /* address match1 */
uint32_t PAD[7];
uint32_t sbimstate; /* initiator agent state */
uint32_t sbintvec; /* interrupt mask */
uint32_t sbtmstatelow; /* target state */
uint32_t sbtmstatehigh; /* target state */
uint32_t sbbwa0; /* bandwidth allocation table0 */
uint32_t PAD;
uint32_t sbimconfiglow; /* initiator configuration */
uint32_t sbimconfighigh; /* initiator configuration */
uint32_t sbadmatch0; /* address match0 */
uint32_t PAD;
uint32_t sbtmconfiglow; /* target configuration */
uint32_t sbtmconfighigh; /* target configuration */
uint32_t sbbconfig; /* broadcast configuration */
uint32_t PAD;
uint32_t sbbstate; /* broadcast state */
uint32_t PAD[3];
uint32_t sbactcnfg; /* activate configuration */
uint32_t PAD[3];
uint32_t sbflagst; /* current sbflags */
uint32_t PAD[3];
uint32_t sbidlow; /* identification */
uint32_t sbidhigh; /* identification */
};
/* sdio core registers */
struct sdpcmd_regs {
uint32_t corecontrol; /* 0x00, rev8 */
uint32_t corestatus; /* rev8 */
uint32_t PAD[1];
uint32_t biststatus; /* rev8 */
/* PCMCIA access */
uint16_t pcmciamesportaladdr; /* 0x010, rev8 */
uint16_t PAD[1];
uint16_t pcmciamesportalmask; /* rev8 */
uint16_t PAD[1];
uint16_t pcmciawrframebc; /* rev8 */
uint16_t PAD[1];
uint16_t pcmciaunderflowtimer; /* rev8 */
uint16_t PAD[1];
/* interrupt */
uint32_t intstatus; /* 0x020, rev8 */
uint32_t hostintmask; /* rev8 */
uint32_t intmask; /* rev8 */
uint32_t sbintstatus; /* rev8 */
uint32_t sbintmask; /* rev8 */
uint32_t funcintmask; /* rev4 */
uint32_t PAD[2];
uint32_t tosbmailbox; /* 0x040, rev8 */
uint32_t tohostmailbox; /* rev8 */
uint32_t tosbmailboxdata; /* rev8 */
uint32_t tohostmailboxdata; /* rev8 */
/* synchronized access to registers in SDIO clock domain */
uint32_t sdioaccess; /* 0x050, rev8 */
uint32_t PAD[3];
/* PCMCIA frame control */
uint8_t pcmciaframectrl; /* 0x060, rev8 */
uint8_t PAD[3];
uint8_t pcmciawatermark; /* rev8 */
uint8_t PAD[155];
/* interrupt batching control */
uint32_t intrcvlazy; /* 0x100, rev8 */
uint32_t PAD[3];
/* counters */
uint32_t cmd52rd; /* 0x110, rev8 */
uint32_t cmd52wr; /* rev8 */
uint32_t cmd53rd; /* rev8 */
uint32_t cmd53wr; /* rev8 */
uint32_t abort; /* rev8 */
uint32_t datacrcerror; /* rev8 */
uint32_t rdoutofsync; /* rev8 */
uint32_t wroutofsync; /* rev8 */
uint32_t writebusy; /* rev8 */
uint32_t readwait; /* rev8 */
uint32_t readterm; /* rev8 */
uint32_t writeterm; /* rev8 */
uint32_t PAD[40];
uint32_t clockctlstatus; /* rev8 */
uint32_t PAD[7];
uint32_t PAD[128]; /* DMA engines */
/* SDIO/PCMCIA CIS region */
char cis[512]; /* 0x400-0x5ff, rev6 */
/* PCMCIA function control registers */
char pcmciafcr[256]; /* 0x600-6ff, rev6 */
uint16_t PAD[55];
/* PCMCIA backplane access */
uint16_t backplanecsr; /* 0x76E, rev6 */
uint16_t backplaneaddr0; /* rev6 */
uint16_t backplaneaddr1; /* rev6 */
uint16_t backplaneaddr2; /* rev6 */
uint16_t backplaneaddr3; /* rev6 */
uint16_t backplanedata0; /* rev6 */
uint16_t backplanedata1; /* rev6 */
uint16_t backplanedata2; /* rev6 */
uint16_t backplanedata3; /* rev6 */
uint16_t PAD[31];
/* sprom "size" & "blank" info */
uint16_t spromstatus; /* 0x7BE, rev2 */
uint32_t PAD[464];
uint16_t PAD[0x80];
};
#ifdef CONFIG_IEEE80211_BROADCOM_BCM43362
#include "bcmf_chip_43362.h"
#endif
#endif /* _BCMF_SDIO_CHIP_H_ */

167
drivers/wireless/ieee80211/bcmf_sdio_regs.h Normal file

@ -0,0 +1,167 @@
/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _BRCM_SDH_H_
#define _BRCM_SDH_H_
#define SDIO_FUNC_0 0
#define SDIO_FUNC_1 1
#define SDIO_FUNC_2 2
#define SDIOD_FBR_SIZE 0x100
/* io_en */
#define SDIO_FUNC_ENABLE_1 0x02
#define SDIO_FUNC_ENABLE_2 0x04
/* io_rdys */
#define SDIO_FUNC_READY_1 0x02
#define SDIO_FUNC_READY_2 0x04
/* intr_status */
#define INTR_STATUS_FUNC1 0x2
#define INTR_STATUS_FUNC2 0x4
/* Maximum number of I/O funcs */
#define SDIOD_MAX_IOFUNCS 7
/* mask of register map */
#define REG_F0_REG_MASK 0x7FF
#define REG_F1_MISC_MASK 0x1FFFF
/* as of sdiod rev 0, supports 3 functions */
#define SBSDIO_NUM_FUNCTION 3
/* function 0 vendor specific CCCR registers */
#define SDIO_CCCR_BRCM_CARDCAP 0xf0
#define SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT 0x02
#define SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT 0x04
#define SDIO_CCCR_BRCM_CARDCAP_CMD_NODEC 0x08
#define SDIO_CCCR_BRCM_CARDCTRL 0xf1
#define SDIO_CCCR_BRCM_CARDCTRL_WLANRESET 0x02
#define SDIO_CCCR_BRCM_SEPINT 0xf2
#define SDIO_SEPINT_MASK 0x01
#define SDIO_SEPINT_OE 0x02
#define SDIO_SEPINT_ACT_HI 0x04
/* function 1 miscellaneous registers */
/* sprom command and status */
#define SBSDIO_SPROM_CS 0x10000
/* sprom info register */
#define SBSDIO_SPROM_INFO 0x10001
/* sprom indirect access data byte 0 */
#define SBSDIO_SPROM_DATA_LOW 0x10002
/* sprom indirect access data byte 1 */
#define SBSDIO_SPROM_DATA_HIGH 0x10003
/* sprom indirect access addr byte 0 */
#define SBSDIO_SPROM_ADDR_LOW 0x10004
/* sprom indirect access addr byte 0 */
#define SBSDIO_SPROM_ADDR_HIGH 0x10005
/* xtal_pu (gpio) output */
#define SBSDIO_CHIP_CTRL_DATA 0x10006
/* xtal_pu (gpio) enable */
#define SBSDIO_CHIP_CTRL_EN 0x10007
/* rev < 7, watermark for sdio device */
#define SBSDIO_WATERMARK 0x10008
/* control busy signal generation */
#define SBSDIO_DEVICE_CTL 0x10009
/* SB Address Window Low (b15) */
#define SBSDIO_FUNC1_SBADDRLOW 0x1000A
/* SB Address Window Mid (b23:b16) */
#define SBSDIO_FUNC1_SBADDRMID 0x1000B
/* SB Address Window High (b31:b24) */
#define SBSDIO_FUNC1_SBADDRHIGH 0x1000C
/* Frame Control (frame term/abort) */
#define SBSDIO_FUNC1_FRAMECTRL 0x1000D
/* ChipClockCSR (ALP/HT ctl/status) */
#define SBSDIO_FUNC1_CHIPCLKCSR 0x1000E
/* Force ALP request to backplane */
#define SBSDIO_FORCE_ALP 0x01
/* Force HT request to backplane */
#define SBSDIO_FORCE_HT 0x02
/* Force ILP request to backplane */
#define SBSDIO_FORCE_ILP 0x04
/* Make ALP ready (power up xtal) */
#define SBSDIO_ALP_AVAIL_REQ 0x08
/* Make HT ready (power up PLL) */
#define SBSDIO_HT_AVAIL_REQ 0x10
/* Squelch clock requests from HW */
#define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20
/* Status: ALP is ready */
#define SBSDIO_ALP_AVAIL 0x40
/* Status: HT is ready */
#define SBSDIO_HT_AVAIL 0x80
/* SdioPullUp (on cmd, d0-d2) */
#define SBSDIO_FUNC1_SDIOPULLUP 0x1000F
/* Write Frame Byte Count Low */
#define SBSDIO_FUNC1_WFRAMEBCLO 0x10019
/* Write Frame Byte Count High */
#define SBSDIO_FUNC1_WFRAMEBCHI 0x1001A
/* Read Frame Byte Count Low */
#define SBSDIO_FUNC1_RFRAMEBCLO 0x1001B
/* Read Frame Byte Count High */
#define SBSDIO_FUNC1_RFRAMEBCHI 0x1001C
/* MesBusyCtl (rev 11) */
#define SBSDIO_FUNC1_MESBUSYCTRL 0x1001D
/* Sdio Core Rev 12 */
#define SBSDIO_FUNC1_WAKEUPCTRL 0x1001E
#define SBSDIO_FUNC1_WCTRL_ALPWAIT_MASK 0x1
#define SBSDIO_FUNC1_WCTRL_ALPWAIT_SHIFT 0
#define SBSDIO_FUNC1_WCTRL_HTWAIT_MASK 0x2
#define SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT 1
#define SBSDIO_FUNC1_SLEEPCSR 0x1001F
#define SBSDIO_FUNC1_SLEEPCSR_KSO_MASK 0x1
#define SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT 0
#define SBSDIO_FUNC1_SLEEPCSR_KSO_EN 1
#define SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK 0x2
#define SBSDIO_FUNC1_SLEEPCSR_DEVON_SHIFT 1
#define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
#define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
#define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
#define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
#define SBSDIO_CLKAV(regval, alponly) \
(SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))
#define SBSDIO_FUNC1_MISC_REG_START 0x10000 /* f1 misc register start */
#define SBSDIO_FUNC1_MISC_REG_LIMIT 0x1001F /* f1 misc register end */
/* function 1 OCP space */
/* sb offset addr is <= 15 bits, 32k */
#define SBSDIO_SB_OFT_ADDR_MASK 0x07FFF
#define SBSDIO_SB_OFT_ADDR_LIMIT 0x08000
/* with b15, maps to 32-bit SB access */
#define SBSDIO_SB_ACCESS_2_4B_FLAG 0x08000
/* valid bits in SBSDIO_FUNC1_SBADDRxxx regs */
#define SBSDIO_SBADDRLOW_MASK 0x80 /* Valid bits in SBADDRLOW */
#define SBSDIO_SBADDRMID_MASK 0xff /* Valid bits in SBADDRMID */
#define SBSDIO_SBADDRHIGH_MASK 0xffU /* Valid bits in SBADDRHIGH */
/* Address bits from SBADDR regs */
#define SBSDIO_SBWINDOW_MASK 0xffff8000
/* Packet alignment for most efficient SDIO (can change based on platform) */
#define BRCMF_SDALIGN (1 << 6)
/* watchdog polling interval in ms */
#define BRCMF_WD_POLL_MS 10
#endif /* _BRCM_SDH_H_ */

421
drivers/wireless/ieee80211/chip_constants.h

@ -1,421 +0,0 @@
/*
* Copyright (c) 2015 Broadcom
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* 3. Neither the name of Broadcom nor the names of other contributors to this
* software may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* 4. This software may not be used as a standalone product, and may only be used as
* incorporated in your product or device that incorporates Broadcom wireless connectivity
* products and solely for the purpose of enabling the functionalities of such Broadcom products.
*
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY WARRANTIES OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT, ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef INCLUDED_CHIP_CONSTANTS_H_
#define INCLUDED_CHIP_CONSTANTS_H_
// #include "wwd_wlioctl.h"
#ifdef __cplusplus
extern "C" {
#endif
/******************************************************
* Chip Constants
******************************************************/
#define BCM_43362_CHIP_ID 43362
/******************************************************
* Architecture Constants
******************************************************/
/* General chip stats */
#define CHIP_RAM_SIZE 0x3C000
/* Backplane architecture */
#define CHIPCOMMON_BASE_ADDRESS 0x18000000 /* Chipcommon core register region */
#define DOT11MAC_BASE_ADDRESS 0x18001000 /* dot11mac core register region */
#define SDIO_BASE_ADDRESS 0x18002000 /* SDIOD Device core register region */
#define WLAN_ARMCM3_BASE_ADDRESS 0x18003000 /* ARMCM3 core register region */
#define SOCSRAM_BASE_ADDRESS 0x18004000 /* SOCSRAM core register region */
#define BACKPLANE_ADDRESS_MASK 0x7FFF
#define CHIP_STA_INTERFACE 0
#define CHIP_AP_INTERFACE 1
#define CHIP_P2P_INTERFACE 2
/* Maximum value of bus data credit difference */
#define CHIP_MAX_BUS_DATA_CREDIT_DIFF 7
/* Chipcommon registers */
#define CHIPCOMMON_GPIO_CONTROL ((uint32_t) (CHIPCOMMON_BASE_ADDRESS + 0x6C) )
/******************************************************
* SDIO Constants
******************************************************/
/* CurrentSdiodProgGuide r23 */
/* Base registers */
#define SDIO_CORE ((uint32_t) (SDIO_BASE_ADDRESS + 0x00) )
#define SDIO_INT_STATUS ((uint32_t) (SDIO_BASE_ADDRESS + 0x20) )
#define SDIO_TO_SB_MAILBOX ((uint32_t) (SDIO_BASE_ADDRESS + 0x40) )
#define SDIO_TO_SB_MAILBOX_DATA ((uint32_t) (SDIO_BASE_ADDRESS + 0x48) )
#define SDIO_TO_HOST_MAILBOX_DATA ((uint32_t) (SDIO_BASE_ADDRESS + 0x4C) )
#define SDIO_TO_SB_MAIL_BOX ((uint32_t) (SDIO_BASE_ADDRESS + 0x40) )
#define SDIO_INT_HOST_MASK ((uint32_t) (SDIO_BASE_ADDRESS + 0x24) )
#define SDIO_FUNCTION_INT_MASK ((uint32_t) (SDIO_BASE_ADDRESS + 0x34) )
/* SDIO Function 0 (SDIO Bus) register addresses */
/* SDIO Device CCCR offsets */
/* TODO: What does CIS/CCCR stand for? */
/* CCCR accesses do not require backpane clock */
#define SDIOD_CCCR_REV ( (uint32_t) 0x00 ) /* CCCR/SDIO Revision */
#define SDIOD_CCCR_SDREV ( (uint32_t) 0x01 ) /* SD Revision */
#define SDIOD_CCCR_IOEN ( (uint32_t) 0x02 ) /* I/O Enable */
#define SDIOD_CCCR_IORDY ( (uint32_t) 0x03 ) /* I/O Ready */
#define SDIOD_CCCR_INTEN ( (uint32_t) 0x04 ) /* Interrupt Enable */
#define SDIOD_CCCR_INTPEND ( (uint32_t) 0x05 ) /* Interrupt Pending */
#define SDIOD_CCCR_IOABORT ( (uint32_t) 0x06 ) /* I/O Abort */
#define SDIOD_CCCR_BICTRL ( (uint32_t) 0x07 ) /* Bus Interface control */
#define SDIOD_CCCR_CAPABLITIES ( (uint32_t) 0x08 ) /* Card Capabilities */
#define SDIOD_CCCR_CISPTR_0 ( (uint32_t) 0x09 ) /* Common CIS Base Address Pointer Register 0 (LSB) */
#define SDIOD_CCCR_CISPTR_1 ( (uint32_t) 0x0A ) /* Common CIS Base Address Pointer Register 1 */
#define SDIOD_CCCR_CISPTR_2 ( (uint32_t) 0x0B ) /* Common CIS Base Address Pointer Register 2 (MSB - only bit 1 valid)*/
#define SDIOD_CCCR_BUSSUSP ( (uint32_t) 0x0C ) /* */
#define SDIOD_CCCR_FUNCSEL ( (uint32_t) 0x0D ) /* */
#define SDIOD_CCCR_EXECFLAGS ( (uint32_t) 0x0E ) /* */
#define SDIOD_CCCR_RDYFLAGS ( (uint32_t) 0x0F ) /* */
#define SDIOD_CCCR_BLKSIZE_0 ( (uint32_t) 0x10 ) /* Function 0 (Bus) SDIO Block Size Register 0 (LSB) */
#define SDIOD_CCCR_BLKSIZE_1 ( (uint32_t) 0x11 ) /* Function 0 (Bus) SDIO Block Size Register 1 (MSB) */
#define SDIOD_CCCR_POWER_CONTROL ( (uint32_t) 0x12 ) /* Power Control */
#define SDIOD_CCCR_SPEED_CONTROL ( (uint32_t) 0x13 ) /* Bus Speed Select (control device entry into high-speed clocking mode) */
#define SDIOD_CCCR_UHS_I ( (uint32_t) 0x14 ) /* UHS-I Support */
#define SDIOD_CCCR_DRIVE ( (uint32_t) 0x15 ) /* Drive Strength */
#define SDIOD_CCCR_INTEXT ( (uint32_t) 0x16 ) /* Interrupt Extension */
#define SDIOD_SEP_INT_CTL ( (uint32_t) 0xF2 ) /* Separate Interrupt Control*/
#define SDIOD_CCCR_F1INFO ( (uint32_t) 0x100 ) /* Function 1 (Backplane) Info */
#define SDIOD_CCCR_F1HP ( (uint32_t) 0x102 ) /* Function 1 (Backplane) High Power */
#define SDIOD_CCCR_F1CISPTR_0 ( (uint32_t) 0x109 ) /* Function 1 (Backplane) CIS Base Address Pointer Register 0 (LSB) */
#define SDIOD_CCCR_F1CISPTR_1 ( (uint32_t) 0x10A ) /* Function 1 (Backplane) CIS Base Address Pointer Register 1 */
#define SDIOD_CCCR_F1CISPTR_2 ( (uint32_t) 0x10B ) /* Function 1 (Backplane) CIS Base Address Pointer Register 2 (MSB - only bit 1 valid) */
#define SDIOD_CCCR_F1BLKSIZE_0 ( (uint32_t) 0x110 ) /* Function 1 (Backplane) SDIO Block Size Register 0 (LSB) */
#define SDIOD_CCCR_F1BLKSIZE_1 ( (uint32_t) 0x111 ) /* Function 1 (Backplane) SDIO Block Size Register 1 (MSB) */
#define SDIOD_CCCR_F2INFO ( (uint32_t) 0x200 ) /* Function 2 (WLAN Data FIFO) Info */
#define SDIOD_CCCR_F2HP ( (uint32_t) 0x202 ) /* Function 2 (WLAN Data FIFO) High Power */
#define SDIOD_CCCR_F2CISPTR_0 ( (uint32_t) 0x209 ) /* Function 2 (WLAN Data FIFO) CIS Base Address Pointer Register 0 (LSB) */
#define SDIOD_CCCR_F2CISPTR_1 ( (uint32_t) 0x20A ) /* Function 2 (WLAN Data FIFO) CIS Base Address Pointer Register 1 */
#define SDIOD_CCCR_F2CISPTR_2 ( (uint32_t) 0x20B ) /* Function 2 (WLAN Data FIFO) CIS Base Address Pointer Register 2 (MSB - only bit 1 valid) */
#define SDIOD_CCCR_F2BLKSIZE_0 ( (uint32_t) 0x210 ) /* Function 2 (WLAN Data FIFO) SDIO Block Size Register 0 (LSB) */
#define SDIOD_CCCR_F2BLKSIZE_1 ( (uint32_t) 0x211 ) /* Function 2 (WLAN Data FIFO) SDIO Block Size Register 1 (MSB) */
#define SDIOD_CCCR_F3INFO ( (uint32_t) 0x300 ) /* Function 3 (Bluetooth Data FIFO) Info */
#define SDIOD_CCCR_F3HP ( (uint32_t) 0x302 ) /* Function 3 (Bluetooth Data FIFO) High Power */
#define SDIOD_CCCR_F3CISPTR_0 ( (uint32_t) 0x309 ) /* Function 3 (Bluetooth Data FIFO) CIS Base Address Pointer Register 0 (LSB) */
#define SDIOD_CCCR_F3CISPTR_1 ( (uint32_t) 0x30A ) /* Function 3 (Bluetooth Data FIFO) CIS Base Address Pointer Register 1 */
#define SDIOD_CCCR_F3CISPTR_2 ( (uint32_t) 0x30B ) /* Function 3 (Bluetooth Data FIFO) CIS Base Address Pointer Register 2 (MSB - only bit 1 valid) */
#define SDIOD_CCCR_F3BLKSIZE_0 ( (uint32_t) 0x310 ) /* Function 3 (Bluetooth Data FIFO) SDIO Block Size Register 0 (LSB) */
#define SDIOD_CCCR_F3BLKSIZE_1 ( (uint32_t) 0x311 ) /* Function 3 (Bluetooth Data FIFO) SDIO Block Size Register 1 (MSB) */
/* SDIO Function 1 (Backplane) register addresses */
/* Addresses 0x00000000 - 0x0000FFFF are directly access the backplane
* throught the backplane window. Addresses above 0x0000FFFF are
* registers relating to backplane access, and do not require a backpane
* clock to access them
*/
#define SDIO_GPIO_SELECT ( (uint32_t) 0x10005 )
#define SDIO_GPIO_OUTPUT ( (uint32_t) 0x10006 )
#define SDIO_GPIO_ENABLE ( (uint32_t) 0x10007 )
#define SDIO_FUNCTION2_WATERMARK ( (uint32_t) 0x10008 )
#define SDIO_DEVICE_CONTROL ( (uint32_t) 0x10009 )
#define SDIO_BACKPLANE_ADDRESS_LOW ( (uint32_t) 0x1000A )
#define SDIO_BACKPLANE_ADDRESS_MID ( (uint32_t) 0x1000B )
#define SDIO_BACKPLANE_ADDRESS_HIGH ( (uint32_t) 0x1000C )
#define SDIO_FRAME_CONTROL ( (uint32_t) 0x1000D )
#define SDIO_CHIP_CLOCK_CSR ( (uint32_t) 0x1000E )
#define SDIO_PULL_UP ( (uint32_t) 0x1000F )
#define SDIO_READ_FRAME_BC_LOW ( (uint32_t) 0x1001B )
#define SDIO_READ_FRAME_BC_HIGH ( (uint32_t) 0x1001C )
#define I_HMB_SW_MASK ( (uint32_t) 0x000000F0 )
#define I_HMB_FRAME_IND ( 1<<6 )
#define FRAME_AVAILABLE_MASK I_HMB_SW_MASK
/******************************************************
* SPI Constants
******************************************************/
/* GSPI v1 */
#define SPI_FRAME_CONTROL ( (uint32_t) 0x1000D )
/* Register addresses */
#define SPI_BUS_CONTROL ( (uint32_t) 0x0000 )
#define SPI_RESPONSE_DELAY ( (uint32_t) 0x0001 )
#define SPI_STATUS_ENABLE ( (uint32_t) 0x0002 )
#define SPI_RESET_BP ( (uint32_t) 0x0003 ) /* (corerev >= 1) */
#define SPI_INTERRUPT_REGISTER ( (uint32_t) 0x0004 ) /* 16 bits - Interrupt status */
#define SPI_INTERRUPT_ENABLE_REGISTER ( (uint32_t) 0x0006 ) /* 16 bits - Interrupt mask */
#define SPI_STATUS_REGISTER ( (uint32_t) 0x0008 ) /* 32 bits */
#define SPI_FUNCTION1_INFO ( (uint32_t) 0x000C ) /* 16 bits */
#define SPI_FUNCTION2_INFO ( (uint32_t) 0x000E ) /* 16 bits */
#define SPI_FUNCTION3_INFO ( (uint32_t) 0x0010 ) /* 16 bits */
#define SPI_READ_TEST_REGISTER ( (uint32_t) 0x0014 ) /* 32 bits */
#define SPI_RESP_DELAY_F0 ( (uint32_t) 0x001c ) /* 8 bits (corerev >= 3) */
#define SPI_RESP_DELAY_F1 ( (uint32_t) 0x001d ) /* 8 bits (corerev >= 3) */
#define SPI_RESP_DELAY_F2 ( (uint32_t) 0x001e ) /* 8 bits (corerev >= 3) */
#define SPI_RESP_DELAY_F3 ( (uint32_t) 0x001f ) /* 8 bits (corerev >= 3) */
/******************************************************
* Bit Masks
******************************************************/
/* SDIOD_CCCR_REV Bits */
#define SDIO_REV_SDIOID_MASK ( (uint32_t) 0xF0 ) /* SDIO spec revision number */
#define SDIO_REV_CCCRID_MASK ( (uint32_t) 0x0F ) /* CCCR format version number */
/* SDIOD_CCCR_SDREV Bits */
#define SD_REV_PHY_MASK ( (uint32_t) 0x0F ) /* SD format version number */
/* SDIOD_CCCR_IOEN Bits */
#define SDIO_FUNC_ENABLE_1 ( (uint32_t) 0x02 ) /* function 1 I/O enable */
#define SDIO_FUNC_ENABLE_2 ( (uint32_t) 0x04 ) /* function 2 I/O enable */
#define SDIO_FUNC_ENABLE_3 ( (uint32_t) 0x08 ) /* function 3 I/O enable */
/* SDIOD_CCCR_IORDY Bits */
#define SDIO_FUNC_READY_1 ( (uint32_t) 0x02 ) /* function 1 I/O ready */
#define SDIO_FUNC_READY_2 ( (uint32_t) 0x04 ) /* function 2 I/O ready */
#define SDIO_FUNC_READY_3 ( (uint32_t) 0x08 ) /* function 3 I/O ready */
/* SDIOD_CCCR_INTEN Bits */
#define INTR_CTL_MASTER_EN ( (uint32_t) 0x01 ) /* interrupt enable master */
#define INTR_CTL_FUNC1_EN ( (uint32_t) 0x02 ) /* interrupt enable for function 1 */
#define INTR_CTL_FUNC2_EN ( (uint32_t) 0x04 ) /* interrupt enable for function 2 */
/* SDIOD_SEP_INT_CTL Bits */
#define SEP_INTR_CTL_MASK ( (uint32_t) 0x01 ) /* out-of-band interrupt mask */
#define SEP_INTR_CTL_EN ( (uint32_t) 0x02 ) /* out-of-band interrupt output enable */
#define SEP_INTR_CTL_POL ( (uint32_t) 0x04 ) /* out-of-band interrupt polarity */
/* SDIOD_CCCR_INTPEND Bits */
#define INTR_STATUS_FUNC1 ( (uint32_t) 0x02 ) /* interrupt pending for function 1 */
#define INTR_STATUS_FUNC2 ( (uint32_t) 0x04 ) /* interrupt pending for function 2 */
#define INTR_STATUS_FUNC3 ( (uint32_t) 0x08 ) /* interrupt pending for function 3 */
/* SDIOD_CCCR_IOABORT Bits */
#define IO_ABORT_RESET_ALL ( (uint32_t) 0x08 ) /* I/O card reset */
#define IO_ABORT_FUNC_MASK ( (uint32_t) 0x07 ) /* abort selction: function x */
/* SDIOD_CCCR_BICTRL Bits */
#define BUS_CARD_DETECT_DIS ( (uint32_t) 0x80 ) /* Card Detect disable */
#define BUS_SPI_CONT_INTR_CAP ( (uint32_t) 0x40 ) /* support continuous SPI interrupt */
#define BUS_SPI_CONT_INTR_EN ( (uint32_t) 0x20 ) /* continuous SPI interrupt enable */
#define BUS_SD_DATA_WIDTH_MASK ( (uint32_t) 0x03 ) /* bus width mask */
#define BUS_SD_DATA_WIDTH_4BIT ( (uint32_t) 0x02 ) /* bus width 4-bit mode */
#define BUS_SD_DATA_WIDTH_1BIT ( (uint32_t) 0x00 ) /* bus width 1-bit mode */
/* SDIOD_CCCR_CAPABLITIES Bits */
#define SDIO_CAP_4BLS ( (uint32_t) 0x80 ) /* 4-bit support for low speed card */
#define SDIO_CAP_LSC ( (uint32_t) 0x40 ) /* low speed card */
#define SDIO_CAP_E4MI ( (uint32_t) 0x20 ) /* enable interrupt between block of data in 4-bit mode */
#define SDIO_CAP_S4MI ( (uint32_t) 0x10 ) /* support interrupt between block of data in 4-bit mode */
#define SDIO_CAP_SBS ( (uint32_t) 0x08 ) /* support suspend/resume */
#define SDIO_CAP_SRW ( (uint32_t) 0x04 ) /* support read wait */
#define SDIO_CAP_SMB ( (uint32_t) 0x02 ) /* support multi-block transfer */
#define SDIO_CAP_SDC ( (uint32_t) 0x01 ) /* Support Direct commands during multi-byte transfer */
/* SDIOD_CCCR_POWER_CONTROL Bits */
#define SDIO_POWER_SMPC ( (uint32_t) 0x01 ) /* supports master power control (RO) */
#define SDIO_POWER_EMPC ( (uint32_t) 0x02 ) /* enable master power control (allow > 200mA) (RW) */
/* SDIOD_CCCR_SPEED_CONTROL Bits */
#define SDIO_SPEED_SHS ( (uint32_t) 0x01 ) /* supports high-speed [clocking] mode (RO) */
#define SDIO_SPEED_EHS ( (uint32_t) 0x02 ) /* enable high-speed [clocking] mode (RW) */
/* GSPI */
#define SPI_READ_TEST_REGISTER_VALUE ( (uint32_t) 0xFEEDBEAD )
#define SPI_READ_TEST_REG_LSB ( ( ( SPI_READ_TEST_REGISTER_VALUE ) ) & 0xff )
#define SPI_READ_TEST_REG_LSB_SFT1 ( ( ( SPI_READ_TEST_REGISTER_VALUE << 1 ) ) & 0xff )
#define SPI_READ_TEST_REG_LSB_SFT2 ( ( ( SPI_READ_TEST_REGISTER_VALUE << 1 ) + 1 ) & 0xff )
#define SPI_READ_TEST_REG_LSB_SFT3 ( ( ( SPI_READ_TEST_REGISTER_VALUE +1 ) << 1 ) & 0xff )
/* SPI_BUS_CONTROL Bits */
#define WORD_LENGTH_32 ( (uint32_t) 0x01 ) /* 0/1 16/32 bit word length */
#define ENDIAN_BIG ( (uint32_t) 0x02 ) /* 0/1 Little/Big Endian */
#define CLOCK_PHASE ( (uint32_t) 0x04 ) /* 0/1 clock phase delay */
#define CLOCK_POLARITY ( (uint32_t) 0x08 ) /* 0/1 Idle state clock polarity is low/high */
#define HIGH_SPEED_MODE ( (uint32_t) 0x10 ) /* 1/0 High Speed mode / Normal mode */
#define INTR_POLARITY_HIGH ( (uint32_t) 0x20 ) /* 1/0 Interrupt active polarity is high/low */
#define WAKE_UP ( (uint32_t) 0x80 ) /* 0/1 Wake-up command from Host to WLAN */
/* SPI_RESPONSE_DELAY Bit mask */
#define RESPONSE_DELAY_MASK 0xFF /* Configurable rd response delay in multiples of 8 bits */
/* SPI_STATUS_ENABLE Bits */
#define STATUS_ENABLE ( (uint32_t) 0x01 ) /* 1/0 Status sent/not sent to host after read/write */
#define INTR_WITH_STATUS ( (uint32_t) 0x02 ) /* 0/1 Do-not / do-interrupt if status is sent */
#define RESP_DELAY_ALL ( (uint32_t) 0x04 ) /* Applicability of resp delay to F1 or all func's read */
#define DWORD_PKT_LEN_EN ( (uint32_t) 0x08 ) /* Packet len denoted in dwords instead of bytes */
#define CMD_ERR_CHK_EN ( (uint32_t) 0x20 ) /* Command error check enable */
#define DATA_ERR_CHK_EN ( (uint32_t) 0x40 ) /* Data error check enable */
/* SPI_RESET_BP Bits*/
#define RESET_ON_WLAN_BP_RESET ( (uint32_t) 0x04 ) /* enable reset for WLAN backplane */
#define RESET_ON_BT_BP_RESET ( (uint32_t) 0x08 ) /* enable reset for BT backplane */
#define RESET_SPI ( (uint32_t) 0x80 ) /* reset the above enabled logic */
/* SPI_INTERRUPT_REGISTER and SPI_INTERRUPT_ENABLE_REGISTER Bits */
#define DATA_UNAVAILABLE ( (uint32_t) 0x0001 ) /* Requested data not available; Clear by writing a "1" */
#define F2_F3_FIFO_RD_UNDERFLOW ( (uint32_t) 0x0002 )
#define F2_F3_FIFO_WR_OVERFLOW ( (uint32_t) 0x0004 )
#define COMMAND_ERROR ( (uint32_t) 0x0008 ) /* Cleared by writing 1 */
#define DATA_ERROR ( (uint32_t) 0x0010 ) /* Cleared by writing 1 */
#define F2_PACKET_AVAILABLE ( (uint32_t) 0x0020 )
#define F3_PACKET_AVAILABLE ( (uint32_t) 0x0040 )
#define F1_OVERFLOW ( (uint32_t) 0x0080 ) /* Due to last write. Bkplane has pending write requests */
#define MISC_INTR0 ( (uint32_t) 0x0100 )
#define MISC_INTR1 ( (uint32_t) 0x0200 )
#define MISC_INTR2 ( (uint32_t) 0x0400 )
#define MISC_INTR3 ( (uint32_t) 0x0800 )
#define MISC_INTR4 ( (uint32_t) 0x1000 )
#define F1_INTR ( (uint32_t) 0x2000 )
#define F2_INTR ( (uint32_t) 0x4000 )
#define F3_INTR ( (uint32_t) 0x8000 )
/* SPI_STATUS_REGISTER Bits */
#define STATUS_DATA_NOT_AVAILABLE ( (uint32_t) 0x00000001 )
#define STATUS_UNDERFLOW ( (uint32_t) 0x00000002 )
#define STATUS_OVERFLOW ( (uint32_t) 0x00000004 )
#define STATUS_F2_INTR ( (uint32_t) 0x00000008 )
#define STATUS_F3_INTR ( (uint32_t) 0x00000010 )
#define STATUS_F2_RX_READY ( (uint32_t) 0x00000020 )
#define STATUS_F3_RX_READY ( (uint32_t) 0x00000040 )
#define STATUS_HOST_CMD_DATA_ERR ( (uint32_t) 0x00000080 )
#define STATUS_F2_PKT_AVAILABLE ( (uint32_t) 0x00000100 )
#define STATUS_F2_PKT_LEN_MASK ( (uint32_t) 0x000FFE00 )
#define STATUS_F2_PKT_LEN_SHIFT ( (uint32_t) 9 )
#define STATUS_F3_PKT_AVAILABLE ( (uint32_t) 0x00100000 )
#define STATUS_F3_PKT_LEN_MASK ( (uint32_t) 0xFFE00000 )
#define STATUS_F3_PKT_LEN_SHIFT ( (uint32_t) 21 )
/* SDIO_CHIP_CLOCK_CSR Bits */
#define SBSDIO_FORCE_ALP ( (uint32_t) 0x01 ) /* Force ALP request to backplane */
#define SBSDIO_FORCE_HT ( (uint32_t) 0x02 ) /* Force HT request to backplane */
#define SBSDIO_FORCE_ILP ( (uint32_t) 0x04 ) /* Force ILP request to backplane */
#define SBSDIO_ALP_AVAIL_REQ ( (uint32_t) 0x08 ) /* Make ALP ready (power up xtal) */
#define SBSDIO_HT_AVAIL_REQ ( (uint32_t) 0x10 ) /* Make HT ready (power up PLL) */
#define SBSDIO_FORCE_HW_CLKREQ_OFF ( (uint32_t) 0x20 ) /* Squelch clock requests from HW */
#define SBSDIO_ALP_AVAIL ( (uint32_t) 0x40 ) /* Status: ALP is ready */
#define SBSDIO_HT_AVAIL ( (uint32_t) 0x80 ) /* Status: HT is ready */
#define SBSDIO_Rev8_HT_AVAIL ( (uint32_t) 0x40 )
#define SBSDIO_Rev8_ALP_AVAIL ( (uint32_t) 0x80 )
/* SDIO_FRAME_CONTROL Bits */
#define SFC_RF_TERM ( (uint32_t) (1 << 0) ) /* Read Frame Terminate */
#define SFC_WF_TERM ( (uint32_t) (1 << 1) ) /* Write Frame Terminate */
#define SFC_CRC4WOOS ( (uint32_t) (1 << 2) ) /* HW reports CRC error for write out of sync */
#define SFC_ABORTALL ( (uint32_t) (1 << 3) ) /* Abort cancels all in-progress frames */
/* SDIO_TO_SB_MAIL_BOX bits corresponding to intstatus bits */
#define SMB_NAK ( (uint32_t) (1 << 0) ) /* To SB Mailbox Frame NAK */
#define SMB_INT_ACK ( (uint32_t) (1 << 1) ) /* To SB Mailbox Host Interrupt ACK */
#define SMB_USE_OOB ( (uint32_t) (1 << 2) ) /* To SB Mailbox Use OOB Wakeup */
#define SMB_DEV_INT ( (uint32_t) (1 << 3) ) /* To SB Mailbox Miscellaneous Interrupt */
#define WL_CHANSPEC_BAND_MASK (0xf000)
#define WL_CHANSPEC_BAND_5G (0x1000)
#define WL_CHANSPEC_BAND_2G (0x2000)
#define WL_CHANSPEC_CTL_SB_MASK (0x0300)
#define WL_CHANSPEC_CTL_SB_LOWER (0x0100)
#define WL_CHANSPEC_CTL_SB_UPPER (0x0200)
#define WL_CHANSPEC_CTL_SB_NONE (0x0300)
#define WL_CHANSPEC_BW_MASK (0x0C00)
#define WL_CHANSPEC_BW_10 (0x0400)
#define WL_CHANSPEC_BW_20 (0x0800)
#define WL_CHANSPEC_BW_40 (0x0C00)
// /* CIS accesses require backpane clock */
//
//
// #define CHIP_HAS_BSSID_CNT_IN_ASSOC_PARAMS
// #define CHIP_FIRMWARE_SUPPORTS_PM_LIMIT_IOVAR
//
// struct ether_addr;
// struct wl_join_scan_params;
//
// typedef struct wl_assoc_params
// {
// struct ether_addr bssid;
// #ifdef CHIP_HAS_BSSID_CNT_IN_ASSOC_PARAMS
// uint16_t bssid_cnt;
// #endif /* ifdef CHIP_HAS_BSSID_CNT_IN_ASSOC_PARAMS */
// uint32_t chanspec_num;
// chanspec_t chanspec_list[1];
// } wl_assoc_params_t;
// #define WL_ASSOC_PARAMS_FIXED_SIZE (sizeof(wl_assoc_params_t) - sizeof(wl_chanspec_t))
// typedef wl_assoc_params_t wl_reassoc_params_t;
// #define WL_REASSOC_PARAMS_FIXED_SIZE WL_ASSOC_PARAMS_FIXED_SIZE
// typedef wl_assoc_params_t wl_join_assoc_params_t;
// #define WL_JOIN_ASSOC_PARAMS_FIXED_SIZE WL_ASSOC_PARAMS_FIXED_SIZE
// typedef struct wl_join_params
// {
// wlc_ssid_t ssid;
// struct wl_assoc_params params;
// } wl_join_params_t;
// #define WL_JOIN_PARAMS_FIXED_SIZE (sizeof(wl_join_params_t) - sizeof(wl_chanspec_t))
//
// /* extended join params */
// typedef struct wl_extjoin_params
// {
// wlc_ssid_t ssid; /* {0, ""}: wildcard scan */
// struct wl_join_scan_params scan_params;
// wl_join_assoc_params_t assoc_params; /* optional field, but it must include the fixed portion of the wl_join_assoc_params_t struct when it does present. */
// } wl_extjoin_params_t;
// #define WL_EXTJOIN_PARAMS_FIXED_SIZE (sizeof(wl_extjoin_params_t) - sizeof(chanspec_t))
//
// typedef wl_cnt_ver_six_t wiced_counters_t;
#ifdef __cplusplus
} /* extern "C" */
#endif
#endif /* ifndef INCLUDED_CHIP_CONSTANTS_H_ */

19
drivers/wireless/ieee80211/mmc_sdio.c

@ -78,7 +78,14 @@ int sdio_io_rw_direct(FAR struct sdio_dev_s *dev, bool write,
/* Setup CMD52 argument */
arg.cmd52.write_data = inb;
if (write)
{
arg.cmd52.write_data = inb;
}
else
{
arg.cmd52.write_data = 0;
}
arg.cmd52.register_address = address & 0x1ffff;
arg.cmd52.raw_flag = (write && outb);
arg.cmd52.function_number = function & 7;
@ -128,18 +135,18 @@ int sdio_io_rw_extended(FAR struct sdio_dev_s *dev, bool write,
/* Setup CMD53 argument */
arg.cmd53.byte_block_count = blocklen;
arg.cmd53.register_address = address & 0x1ffff;
arg.cmd53.op_code = inc_addr;
arg.cmd53.function_number = function & 7;
arg.cmd53.rw_flag = write;
if (nblocks <= 1 && blocklen < 512)
if (nblocks == 0 && blocklen < 512)
{
/* Use byte mode */
_info("byte mode\n");
// _info("byte mode\n");
arg.cmd53.block_mode = 0;
arg.cmd53.byte_block_count = blocklen;
nblocks = 1;
}
else
@ -147,6 +154,7 @@ int sdio_io_rw_extended(FAR struct sdio_dev_s *dev, bool write,
/* Use block mode */
arg.cmd53.block_mode = 1;
arg.cmd53.byte_block_count = nblocks;
}
/* Send CMD53 command */
@ -157,6 +165,7 @@ int sdio_io_rw_extended(FAR struct sdio_dev_s *dev, bool write,
if (write)
{
// _info("prep write %d %d\n", blocklen, nblocks);
sdio_sendcmdpoll(dev, SDIO_ACMD53, (uint32_t)arg.value);
ret = SDIO_RECVR5(dev, SDIO_ACMD53, (uint32_t*)&resp);
@ -165,7 +174,7 @@ int sdio_io_rw_extended(FAR struct sdio_dev_s *dev, bool write,
}
else
{
_info("prep read %d\n", blocklen * nblocks);
// _info("prep read %d\n", blocklen * nblocks);
SDIO_RECVSETUP(dev, buf, blocklen * nblocks);
SDIO_SENDCMD(dev, SDIO_ACMD53, (uint32_t)arg.value);

16
include/nuttx/wireless/ieee80211/bcmf_board.h

@ -102,6 +102,22 @@ void bcmf_board_power(int minor, bool power);
void bcmf_board_reset(int minor, bool reset);
/************************************************************************************
* Function: bcmf_board_setup_oob_irq
*
* Description:
* Board specific function called from Broadcom FullMAC driver
* that must be implemented to use WLAN chip interrupt signal
*
* Parameters:
* minor - zero based minor device number which is unique
* for each wlan device.
* func - WLAN chip callback function that must be called on gpio event
* arg - WLAN chip internal structure that must be passed to callback
************************************************************************************/
void bcmf_board_setup_oob_irq(int minor, xcpt_t func, void *arg);
#undef EXTERN
#ifdef __cplusplus
}

2
include/nuttx/wireless/ieee80211/mmc_sdio.h

@ -12,6 +12,8 @@ int sdio_set_blocksize(FAR struct sdio_dev_s *dev, uint8_t function,
int sdio_enable_function(FAR struct sdio_dev_s *dev, uint8_t function);
int sdio_enable_interrupt(FAR struct sdio_dev_s *dev, uint8_t function);
int sdio_sendcmdpoll(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t arg);
int sdio_io_rw_direct(FAR struct sdio_dev_s *dev, bool write,