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stm32f7:Use inttypes in printing macro

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stm32f7:SDMMC Use inttypes in printing macro

stm32f7:CAN Use inttypes in printing macro

stm32f7:DMA Use inttypes in printing macro

stm32f7:serial fix compile error from UNUSED() change
This commit is contained in:
David Sidrane 2021-04-23 12:30:57 -07:00 committed by Xiang Xiao
parent cbe3e120d5
commit e5ceb062f9
4 changed files with 53 additions and 44 deletions
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82
arch/arm/src/stm32f7/stm32_can.c
View File

@ -43,6 +43,7 @@
#include <nuttx/config.h>
#include <inttypes.h>
#include <stdio.h>
#include <sys/types.h>
#include <stdint.h>
@ -322,7 +323,7 @@ static uint32_t stm32can_vgetreg(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
caninfo("[repeats %d more times]\n", count - 3);
caninfo("[repeats %" PRIu32 " more times]\n", count - 3);
}
/* Save the new address, value, and count */
@ -334,7 +335,7 @@ static uint32_t stm32can_vgetreg(uint32_t addr)
/* Show the register value read */
caninfo("%08x->%08x\n", addr, val);
caninfo("%08" PRIx32 "->%08" PRIx32 "\n", addr, val);
return val;
}
@ -383,7 +384,7 @@ static void stm32can_vputreg(uint32_t addr, uint32_t value)
{
/* Show the register value being written */
caninfo("%08x<-%08x\n", addr, value);
caninfo("%08" PRIx32 "->%08" PRIx32 "\n", addr, val);
/* Write the value */
@ -445,16 +446,16 @@ static void stm32can_dumpctrlregs(FAR struct stm32_can_s *priv,
/* CAN control and status registers */
caninfo(" MCR: %08x MSR: %08x TSR: %08x\n",
caninfo(" MCR: %08" PRIx32 " MSR: %08" PRIx32 " TSR: %08" PRIx32 "\n",
getreg32(priv->base + STM32_CAN_MCR_OFFSET),
getreg32(priv->base + STM32_CAN_MSR_OFFSET),
getreg32(priv->base + STM32_CAN_TSR_OFFSET));
caninfo(" RF0R: %08x RF1R: %08x\n",
caninfo(" RF0R: %08" PRIx32 " RF1R: %08" PRIx32 "\n",
getreg32(priv->base + STM32_CAN_RF0R_OFFSET),
getreg32(priv->base + STM32_CAN_RF1R_OFFSET));
caninfo(" IER: %08x ESR: %08x BTR: %08x\n",
caninfo(" IER: %08" PRIx32 " ESR: %08" PRIx32 " BTR: %08" PRIx32 "\n",
getreg32(priv->base + STM32_CAN_IER_OFFSET),
getreg32(priv->base + STM32_CAN_ESR_OFFSET),
getreg32(priv->base + STM32_CAN_BTR_OFFSET));
@ -490,31 +491,36 @@ static void stm32can_dumpmbregs(FAR struct stm32_can_s *priv,
/* CAN mailbox registers (3 TX and 2 RX) */
caninfo(" TI0R: %08x TDT0R: %08x TDL0R: %08x TDH0R: %08x\n",
caninfo(" TI0R: %08" PRIx32 " TDT0R: %08" PRIx32 " TDL0R: %08"
PRIx32 " TDH0R: %08" PRIx32 "\n",
getreg32(priv->base + STM32_CAN_TI0R_OFFSET),
getreg32(priv->base + STM32_CAN_TDT0R_OFFSET),
getreg32(priv->base + STM32_CAN_TDL0R_OFFSET),
getreg32(priv->base + STM32_CAN_TDH0R_OFFSET));
caninfo(" TI1R: %08x TDT1R: %08x TDL1R: %08x TDH1R: %08x\n",
caninfo(" TI1R: %08" PRIx32 " TDT1R: %08" PRIx32 " TDL1R: %08"
PRIx32 " TDH1R: %08" PRIx32 "\n",
getreg32(priv->base + STM32_CAN_TI1R_OFFSET),
getreg32(priv->base + STM32_CAN_TDT1R_OFFSET),
getreg32(priv->base + STM32_CAN_TDL1R_OFFSET),
getreg32(priv->base + STM32_CAN_TDH1R_OFFSET));
caninfo(" TI2R: %08x TDT2R: %08x TDL2R: %08x TDH2R: %08x\n",
caninfo(" TI2R: %08" PRIx32 " TDT2R: %08" PRIx32 " TDL2R: %08"
PRIx32 " TDH2R: %08" PRIx32 "\n",
getreg32(priv->base + STM32_CAN_TI2R_OFFSET),
getreg32(priv->base + STM32_CAN_TDT2R_OFFSET),
getreg32(priv->base + STM32_CAN_TDL2R_OFFSET),
getreg32(priv->base + STM32_CAN_TDH2R_OFFSET));
caninfo(" RI0R: %08x RDT0R: %08x RDL0R: %08x RDH0R: %08x\n",
caninfo(" RI0R: %08" PRIx32 " RDT0R: %08" PRIx32 " RDL0R: %08"
PRIx32 " RDH0R: %08" PRIx32 "\n",
getreg32(priv->base + STM32_CAN_RI0R_OFFSET),
getreg32(priv->base + STM32_CAN_RDT0R_OFFSET),
getreg32(priv->base + STM32_CAN_RDL0R_OFFSET),
getreg32(priv->base + STM32_CAN_RDH0R_OFFSET));
caninfo(" RI1R: %08x RDT1R: %08x RDL1R: %08x RDH1R: %08x\n",
caninfo(" RI1R: %08" PRIx32 " RDT1R: %08" PRIx32 " RDL1R: %08"
PRIx32 " RDH1R: %08" PRIx32 "\n",
getreg32(priv->base + STM32_CAN_RI1R_OFFSET),
getreg32(priv->base + STM32_CAN_RDT1R_OFFSET),
getreg32(priv->base + STM32_CAN_RDL1R_OFFSET),
@ -551,7 +557,8 @@ static void stm32can_dumpfiltregs(FAR struct stm32_can_s *priv,
caninfo("Filter Registers:\n");
}
caninfo(" FMR: %08x FM1R: %08x FS1R: %08x FFA1R: %08x FA1R: %08x\n",
caninfo(" FMR: %08" PRIx32 " FM1R: %08" PRIx32 " FS1R: %08"
PRIx32 " FFA1R: %08" PRIx32 " FA1R: %08" PRIx32 "\n",
getreg32(priv->base + STM32_CAN_FMR_OFFSET),
getreg32(priv->base + STM32_CAN_FM1R_OFFSET),
getreg32(priv->base + STM32_CAN_FS1R_OFFSET),
@ -560,7 +567,7 @@ static void stm32can_dumpfiltregs(FAR struct stm32_can_s *priv,
for (i = 0; i < CAN_NFILTERS; i++)
{
caninfo(" F%dR1: %08x F%dR2: %08x\n",
caninfo(" F%dR1: %08" PRIx32 " F%dR2: %08" PRIx32 "\n",
i, getreg32(priv->base + STM32_CAN_FIR_OFFSET(i, 1)),
i, getreg32(priv->base + STM32_CAN_FIR_OFFSET(i, 2)));
}
@ -589,7 +596,7 @@ static void stm32can_reset(FAR struct can_dev_s *dev)
uint32_t regbit = 0;
irqstate_t flags;
caninfo("CAN%d\n", priv->port);
caninfo("CAN%" PRIu8 "\n", priv->port);
/* Get the bits in the AHB1RSTR register needed to reset this CAN device */
@ -615,7 +622,7 @@ static void stm32can_reset(FAR struct can_dev_s *dev)
else
#endif
{
canerr("ERROR: Unsupported port %d\n", priv->port);
canerr("ERROR: Unsupported port %" PRIu8 "\n", priv->port);
return;
}
@ -658,7 +665,8 @@ static int stm32can_setup(FAR struct can_dev_s *dev)
FAR struct stm32_can_s *priv = dev->cd_priv;
int ret;
caninfo("CAN%d RX0 irq: %d RX1 irq: %d TX irq: %d\n",
caninfo("CAN%" PRIu8 " RX0 irq: %" PRIu8 " RX1 irq: %" PRIu8
" TX irq: %" PRIu8 "\n",
priv->port, priv->canrx[0], priv->canrx[1], priv->cantx);
/* CAN cell initialization */
@ -666,7 +674,7 @@ static int stm32can_setup(FAR struct can_dev_s *dev)
ret = stm32can_cellinit(priv);
if (ret < 0)
{
canerr("ERROR: CAN%d cell initialization failed: %d\n",
canerr("ERROR: CAN%" PRId8 " cell initialization failed: %d\n",
priv->port, ret);
return ret;
}
@ -679,7 +687,7 @@ static int stm32can_setup(FAR struct can_dev_s *dev)
ret = stm32can_filterinit(priv);
if (ret < 0)
{
canerr("ERROR: CAN%d filter initialization failed: %d\n",
canerr("ERROR: CAN%" PRIu8 " filter initialization failed: %d\n",
priv->port, ret);
return ret;
}
@ -693,7 +701,7 @@ static int stm32can_setup(FAR struct can_dev_s *dev)
ret = irq_attach(priv->canrx[0], stm32can_rx0interrupt, dev);
if (ret < 0)
{
canerr("ERROR: Failed to attach CAN%d RX0 IRQ (%d)",
canerr("ERROR: Failed to attach CAN%" PRIu8 " RX0 IRQ (%" PRIu8 ")",
priv->port, priv->canrx[0]);
return ret;
}
@ -701,7 +709,7 @@ static int stm32can_setup(FAR struct can_dev_s *dev)
ret = irq_attach(priv->canrx[1], stm32can_rx1interrupt, dev);
if (ret < 0)
{
canerr("ERROR: Failed to attach CAN%d RX1 IRQ (%d)",
canerr("ERROR: Failed to attach CAN%" PRIu8 " RX1 IRQ (%" PRIu8 ")",
priv->port, priv->canrx[1]);
return ret;
}
@ -709,7 +717,7 @@ static int stm32can_setup(FAR struct can_dev_s *dev)
ret = irq_attach(priv->cantx, stm32can_txinterrupt, dev);
if (ret < 0)
{
canerr("ERROR: Failed to attach CAN%d TX IRQ (%d)",
canerr("ERROR: Failed to attach CAN%" PRIu8 " TX IRQ (%" PRIu8 ")",
priv->port, priv->cantx);
return ret;
}
@ -744,7 +752,7 @@ static void stm32can_shutdown(FAR struct can_dev_s *dev)
{
FAR struct stm32_can_s *priv = dev->cd_priv;
caninfo("CAN%d\n", priv->port);
caninfo("CAN%" PRIu8 "\n", priv->port);
/* Disable the RX FIFO 0/1 and TX interrupts */
@ -782,7 +790,7 @@ static void stm32can_rxint(FAR struct can_dev_s *dev, bool enable)
FAR struct stm32_can_s *priv = dev->cd_priv;
uint32_t regval;
caninfo("CAN%d enable: %d\n", priv->port, enable);
caninfo("CAN%" PRIu8 " enable: %d\n", priv->port, enable);
/* Enable/disable the FIFO 0/1 message pending interrupt */
@ -818,7 +826,7 @@ static void stm32can_txint(FAR struct can_dev_s *dev, bool enable)
FAR struct stm32_can_s *priv = dev->cd_priv;
uint32_t regval;
caninfo("CAN%d enable: %d\n", priv->port, enable);
caninfo("CAN%" PRIu8 " enable: %d\n", priv->port, enable);
/* Support only disabling the transmit mailbox interrupt */
@ -850,7 +858,7 @@ static int stm32can_ioctl(FAR struct can_dev_s *dev, int cmd,
FAR struct stm32_can_s *priv;
int ret = -ENOTTY;
caninfo("cmd=%04x arg=%" PRIu32 "\n", cmd, arg);
caninfo("cmd=%04x arg=%lu\n", cmd, arg);
DEBUGASSERT(dev && dev->cd_priv);
priv = dev->cd_priv;
@ -956,7 +964,7 @@ static int stm32can_ioctl(FAR struct can_dev_s *dev, int cmd,
DEBUGASSERT(brp >= 1 && brp <= CAN_BTR_BRP_MAX);
}
caninfo("TS1: %"PRId8 " TS2: %" PRId8 " BRP: %" PRIu32 "\n",
caninfo("TS1: %"PRIu8 " TS2: %" PRIu8 " BRP: %" PRIu32 "\n",
bt->bt_tseg1, bt->bt_tseg2, brp);
/* Configure bit timing. */
@ -1252,8 +1260,8 @@ static int stm32can_send(FAR struct can_dev_s *dev,
int dlc;
int txmb;
caninfo("CAN%d ID: %d DLC: %d\n",
priv->port, msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc);
caninfo("CAN%" PRIu8 " ID: %" PRIu32 " DLC: %" PRIu8 "\n",
priv->port, (uint32_t)msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc);
/* Select one empty transmit mailbox */
@ -1414,7 +1422,7 @@ static bool stm32can_txready(FAR struct can_dev_s *dev)
/* Return true if any mailbox is available */
regval = stm32can_getreg(priv, STM32_CAN_TSR_OFFSET);
caninfo("CAN%d TSR: %08" PRIx32 "\n", priv->port, regval);
caninfo("CAN%" PRIu8 " TSR: %08" PRIx32 "\n", priv->port, regval);
return stm32can_txmb0empty(regval) || stm32can_txmb1empty(regval) ||
stm32can_txmb2empty(regval);
@ -1446,7 +1454,7 @@ static bool stm32can_txempty(FAR struct can_dev_s *dev)
/* Return true if all mailboxes are available */
regval = stm32can_getreg(priv, STM32_CAN_TSR_OFFSET);
caninfo("CAN%d TSR: %08" PRIx32 "\n", priv->port, regval);
caninfo("CAN%" PRIu8 " TSR: %08" PRIx32 "\n", priv->port, regval);
return stm32can_txmb0empty(regval) && stm32can_txmb1empty(regval) &&
stm32can_txmb2empty(regval);
@ -1752,8 +1760,8 @@ static int stm32can_bittiming(FAR struct stm32_can_s *priv)
uint32_t ts1;
uint32_t ts2;
caninfo("CAN%d PCLK1: %" PRId32 " baud: %" PRId32 "\n",
priv->port, STM32_PCLK1_FREQUENCY, priv->baud);
caninfo("CAN%" PRIu8 " PCLK1: %lu baud: %" PRIu32 "\n",
priv->port, (unsigned long) STM32_PCLK1_FREQUENCY, priv->baud);
/* Try to get CAN_BIT_QUANTA quanta in one bit_time.
*
@ -1805,7 +1813,7 @@ static int stm32can_bittiming(FAR struct stm32_can_s *priv)
DEBUGASSERT(brp >= 1 && brp <= CAN_BTR_BRP_MAX);
}
caninfo("TS1: %" PRId32 " TS2: %" PRId32 " BRP: %" PRId32 "\n",
caninfo("TS1: %" PRIu32 " TS2: %" PRIu32 " BRP: %" PRIu32 "\n",
ts1, ts2, brp);
/* Configure bit timing. This also does the following, less obvious
@ -1851,7 +1859,7 @@ static int stm32can_enterinitmode(FAR struct stm32_can_s *priv)
uint32_t regval;
volatile uint32_t timeout;
caninfo("CAN%d\n", priv->port);
caninfo("CAN%" PRIu8 "\n", priv->port);
/* Enter initialization mode */
@ -1952,7 +1960,7 @@ static int stm32can_cellinit(FAR struct stm32_can_s *priv)
uint32_t regval;
int ret;
caninfo("CAN%d\n", priv->port);
caninfo("CAN%" PRIu8 "\n", priv->port);
/* Exit from sleep mode */
@ -2035,7 +2043,7 @@ static int stm32can_filterinit(FAR struct stm32_can_s *priv)
uint32_t regval;
uint32_t bitmask;
caninfo("CAN%d filter: %d\n", priv->port, priv->filter);
caninfo("CAN%" PRIu8 " filter: %" PRIu8 "\n", priv->port, priv->filter);
/* Get the bitmask associated with the filter used by this CAN block */
@ -2268,7 +2276,7 @@ FAR struct can_dev_s *stm32_caninitialize(int port)
{
FAR struct can_dev_s *dev = NULL;
caninfo("CAN%d\n", port);
caninfo("CAN%" PRIu8 "\n", port);
/* NOTE: Peripherical clocking for CAN1 and/or CAN2 was already provided
* by stm32_clockconfig() early in the reset sequence.

4
arch/arm/src/stm32f7/stm32_dma.c
View File

@ -921,8 +921,8 @@ bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr)
((mend + 1) & (ARMV7M_DCACHE_LINESIZE - 1)) != 0)
{
dmawarn("stm32_dmacapable:"
" dcache unaligned maddr:0x%08x mend:0x%08x\n",
maddr, mend);
" dcache unaligned maddr:0x%08" PRIxPTR " mend:0x%08"
PRIx32 "\n", maddr, mend);
#if !defined(CONFIG_STM32F7_DMACAPABLE_ASSUME_CACHE_ALIGNED)
return false;
#endif

7
arch/arm/src/stm32f7/stm32_sdmmc.c
View File

@ -2510,7 +2510,7 @@ static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd,
(cmd & MMCSD_RESPONSE_MASK) != MMCSD_R5_RESPONSE &&
(cmd & MMCSD_RESPONSE_MASK) != MMCSD_R6_RESPONSE)
{
mcerr("ERROR: Wrong response CMD=%08x\n", cmd);
mcerr("ERROR: Wrong response CMD=%08" PRIx32 "\n", cmd);
ret = -EINVAL;
}
else
@ -2538,7 +2538,8 @@ static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd,
if ((uint8_t)(respcmd & STM32_SDMMC_RESPCMD_MASK) !=
(cmd & MMCSD_CMDIDX_MASK))
{
mcerr("ERROR: RESCMD=%02x CMD=%08x\n", respcmd, cmd);
mcerr("ERROR: RESCMD=%02" PRIx32 " CMD=%08" PRIx32 "\n",
respcmd, cmd);
ret = -EINVAL;
}
}
@ -2576,7 +2577,7 @@ static int stm32_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd,
if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R2_RESPONSE)
{
mcerr("ERROR: Wrong response CMD=%08x\n", cmd);
mcerr("ERROR: Wrong response CMD=%08" PRIx32 "\n", cmd);
ret = -EINVAL;
}
else

4
arch/arm/src/stm32f7/stm32_serial.c
View File

@ -3641,10 +3641,10 @@ void arm_serialinit(void)
#if !defined(SERIAL_HAVE_ONLY_DMA)
# if defined(SERIAL_HAVE_RXDMA)
UNUSED(g_uart_rxdma_ops);
UNUSED(&g_uart_rxdma_ops);
# endif
# if defined(SERIAL_HAVE_TXDMA)
UNUSED(g_uart_txdma_ops);
UNUSED(&g_uart_txdma_ops);
# endif
#endif