ifup() is partially complete
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3103 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
451bfc3f93
commit
e5e5d8f404
@ -107,20 +107,83 @@
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/* Select PHY-specific values. Add more PHYs as needed. */
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#ifdef CONFIG_PHY_KS8721
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# define LPC17_PHYNAME "KS8721"
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# define LPC17_PHYID1 MII_PHYID1_KS8721
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# define LPC17_PHYID2 MII_PHYID2_KS8721
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# define LPC17_HAVE_PHY 1
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# define LPC17_PHYNAME "KS8721"
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# define LPC17_PHYID1 MII_PHYID1_KS8721
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# define LPC17_PHYID2 MII_PHYID2_KS8721
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# define LPC17_HAVE_PHY 1
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#else
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# warning "No PHY specified!"
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# undef LPC17_HAVE_PHY
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#endif
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#define MII_BIG_TIMEOUT 666666
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#define MII_BIG_TIMEOUT 666666
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/* These definitions are used to remember the speed/duplex settings */
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#define LPC17_SPEED_MASK 0x01
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#define LPC17_SPEED_100 0x01
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#define LPC17_SPEED_10 0x00
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#define LPC17_DUPLEX_MASK 0x02
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#define LPC17_DUPLEX_FULL 0x02
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#define LPC17_DUPLEX_HALF 0x00
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#define LPC17_10BASET_HD (LPC17_SPEED_10 | LPC17_DUPLEX_HALF)
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#define LPC17_10BASET_FD (LPC17_SPEED_10 | LPC17_DUPLEX_FULL)
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#define LPC17_100BASET_HD (LPC17_SPEED_100 | LPC17_DUPLEX_HALF)
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#define LPC17_100BASET_FD (LPC17_SPEED_100 | LPC17_DUPLEX_FULL)
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#ifdef CONFIG_PHY_SPEED100
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# ifdef CONFIG_PHY_FDUPLEX
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# define LPC17_MODE_DEFLT LPC17_100BASET_FD
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# else
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# define LPC17_MODE_DEFLT LPC17_100BASET_HD
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# endif
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#else
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# ifdef CONFIG_PHY_FDUPLEX
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# define LPC17_MODE_DEFLT LPC17_10BASET_FD
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# else
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# define LPC17_MODE_DEFLT LPC17_10BASET_HD
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# endif
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#endif
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/* This is the number of ethernet GPIO pins that must be configured */
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#define GPIO_NENET_PINS 10
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#define GPIO_NENET_PINS 10
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/* EMAC DMA RAM and descriptor definitions.
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*
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* All of AHB SRAM, Bank 0 is set aside for EMAC Tx and Rx descriptors.
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*/
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#define LPC17_BANK0_SIZE 0x00004000
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#warning "Need to exclude bank0 from the heap"
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/* Numbers of descriptors and sizes of descriptor and status regions */
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#ifdef CONFIG_ETH_NTXDESC
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# define CONFIG_ETH_NTXDESC 16
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#endif
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#define LPC17_TXDESC_SIZE (8*CONFIG_ETH_NTXDESC)
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#define LPC17_TXSTAT_SIZE (4*CONFIG_ETH_NTXDESC)
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#ifdef CONFIG_ETH_NRXDESC
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# define CONFIG_ETH_NRXDESC 16
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#endif
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#define LPC17_RXDESC_SIZE (8*CONFIG_ETH_NRXDESC)
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#define LPC17_RXSTAT_SIZE (8*CONFIG_ETH_NRXDESC)
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/* Descriptor Memory Organization. Descriptors are packed
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* at the end of AHB SRAM, Bank 0.
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*/
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#define LPC17_DESC_SIZE (LPC17_TXDESC_SIZE+LPC17_RXDESC_SIZE+LPC17_TXSTAT_SIZE+LPC17_RXSTAT_SIZE)
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#define LPC17_DESC_BASE (LPC17_SRAM_BANK0+LPC17_BANK0_SIZE-LPC17_DESC_SIZE)
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#define LPC17_TXDESC_BASE LPC17_DESC_BASE
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#define LPC17_TXSTAT_BASE (LPC17_TXDESC_BASE+LPC17_TXDESC_SIZE)
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#define LPC17_RXDESC_BASE (LPC17_TXSTAT_BASE+LPC17_TXSTAT_SIZE)
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#define LPC17_RXSTAT_BASE (LPC17_RXDESC_BASE + LPC17_RXDESC_SIZE)
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/* Register debug */
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@ -148,8 +211,7 @@ struct lpc17_driver_s
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#endif
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bool lp_ifup; /* true:ifup false:ifdown */
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bool lp_speed100; /* true:100Mbps false:10Mbps */
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bool lp_fullduplex; /* true:full duplex false:half duplex */
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bool lp_mode; /* speed/duplex */
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#ifdef LPC17_HAVE_PHY
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uint8_t lp_phyaddr; /* PHY device address */
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#endif
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@ -248,15 +310,15 @@ static inline int lpc17_phyreset(uint8_t phyaddr);
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# ifdef CONFIG_PHY_AUTONEG
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static inline int lpc17_phyautoneg(uint8_t phyaddr);
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# endif
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static int lpc17_phyfixed(uint8_t phyaddr, bool speed100, bool fullduplex);
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static void lpc17_phyduplex(uint8_t phyaddr, bool fullduplex);
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static int lpc17_phymode(uint8_t phyaddr, uint8_t mode);
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static inline int lpc17_phyinit(struct lpc17_driver_s *priv);
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#else
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# define lpc17_phyinit()
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# define lpc17_phyinit(priv)
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#endif
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/* EMAC Initialization functions */
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static void lpc17_macmode(uint8_t mode);
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static void lpc17_ethreset(struct lpc17_driver_s *priv);
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/****************************************************************************
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@ -274,7 +336,7 @@ static void lpc17_ethreset(struct lpc17_driver_s *priv);
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#ifdef CONFIG_LPC17_ENET_REGDEBUG
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static void lpc17_printreg(uint32_t addr, uint32_t val, bool iswrite)
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{
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lldbg("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val);
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dbg("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val);
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}
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#endif
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@ -324,7 +386,7 @@ static void lpc17_checkreg(uint32_t addr, uint32_t val, bool iswrite)
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{
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/* No.. More than one. */
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lldbg("[repeats %d more times]\n", count);
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dbg("[repeats %d more times]\n", count);
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}
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}
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@ -695,12 +757,24 @@ static int lpc17_ifup(struct uip_driver_s *dev)
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{
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FAR struct lpc17_driver_s *priv = (FAR struct lpc17_driver_s *)dev->d_private;
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uint32_t regval;
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int ret;
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ndbg("Bringing up: %d.%d.%d.%d\n",
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dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
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(dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24 );
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/* Initilize Ethernet interface */
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/* Reset the Ethernet controller (again) */
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lpc17_ethreset(priv);
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/* Initialize the PHY and wait for the link to be established */
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ret = lpc17_phyinit(priv);
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if (ret != 0)
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{
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ndbg("lpc17_phyinit failed: %d\n", ret);
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return ret;
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}
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/* Configure the MAC station address */
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@ -716,6 +790,16 @@ static int lpc17_ifup(struct uip_driver_s *dev)
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(uint32_t)priv->lp_dev.d_mac.ether_addr_octet[4];
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lpc17_putreg(regval, LPC17_ETH_SA2);
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/* Initialize Ethernet interface for the PHY setup */
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lpc17_macmode(priv->lp_mode);
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/* Initialize EMAC DMA memory */
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/* Set up RX filter and configure to accept broadcast address and perfect
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* station address matches.
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*/
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/* Set and activate a timer process */
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(void)wd_start(priv->lp_txpoll, LPC17_WDDELAY, lpc17_polltimer, 1, (uint32_t)priv);
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@ -760,6 +844,7 @@ static int lpc17_ifdown(struct uip_driver_s *dev)
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/* Reset the device */
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lpc17_ethreset(priv);
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priv->lp_ifup = false;
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irqrestore(flags);
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return OK;
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@ -908,14 +993,14 @@ static void lpc17_showpins(void)
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#if defined(CONFIG_LPC17_ENET_REGDEBUG) && defined(LPC17_HAVE_PHY)
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static void lpc17_showmii(uint8_t phyaddr, const char *msg)
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{
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lldbg("PHY " LPC17_PHYNAME ": %s\n", msg);
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lldbg(" MCR: %04x\n", lpc17_getreg(MII_MCR));
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lldbg(" MSR: %04x\n", lpc17_getreg(MII_MSR));
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lldbg(" ADVERTISE: %04x\n", lpc17_getreg(MII_ADVERTISE));
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lldbg(" LPA: %04x\n", lpc17_getreg(MII_LPA));
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lldbg(" EXPANSION: %04x\n", lpc17_getreg(MII_EXPANSION));
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dbg("PHY " LPC17_PHYNAME ": %s\n", msg);
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dbg(" MCR: %04x\n", lpc17_getreg(MII_MCR));
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dbg(" MSR: %04x\n", lpc17_getreg(MII_MSR));
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dbg(" ADVERTISE: %04x\n", lpc17_getreg(MII_ADVERTISE));
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dbg(" LPA: %04x\n", lpc17_getreg(MII_LPA));
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dbg(" EXPANSION: %04x\n", lpc17_getreg(MII_EXPANSION));
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#ifdef CONFIG_PHY_KS8721
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lldbg(" 10BTCR: %04x\n", lpc17_getreg(MII_KS8721_10BTCR));
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dbg(" 10BTCR: %04x\n", lpc17_getreg(MII_KS8721_10BTCR));
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#endif
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}
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#endif
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@ -1051,7 +1136,7 @@ static inline int lpc17_phyreset(uint8_t phyaddr)
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}
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}
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nlldbg("Reset failed. MCR: %04x\n", phyreg);
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ndbg("Reset failed. MCR: %04x\n", phyreg);
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return -ETIMEDOUT;
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}
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#endif
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@ -1099,19 +1184,20 @@ static inline int lpc17_phyautoneg(uint8_t phyaddr)
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}
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}
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nlldbg("Auto-negotiation failed. MSR: %04x\n", phyreg);
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ndbg("Auto-negotiation failed. MSR: %04x\n", phyreg);
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return -ETIMEDOUT;
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}
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#endif
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/****************************************************************************
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* Function: lpc17_phyfixed
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* Function: lpc17_phymode
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*
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* Description:
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* Set fixed PHY configuration.
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* Set the PHY to operate at a selected speed/duplex mode.
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*
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* Parameters:
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* phyaddr - The device address where the PHY was discovered
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* mode - speed/duplex mode
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*
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* Returned Value:
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* None
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@ -1121,7 +1207,7 @@ static inline int lpc17_phyautoneg(uint8_t phyaddr)
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****************************************************************************/
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#ifdef LPC17_HAVE_PHY
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static int lpc17_phyfixed(uint8_t phyaddr, bool speed100, bool fullduplex)
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static int lpc17_phymode(uint8_t phyaddr, uint8_t mode)
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{
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int32_t timeout;
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uint16_t phyreg;
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@ -1129,12 +1215,12 @@ static int lpc17_phyfixed(uint8_t phyaddr, bool speed100, bool fullduplex)
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/* Disable auto-negotiation and set fixed Speed and Duplex settings */
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phyreg = 0;
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if (speed100)
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if ((mode & LPC17_SPEED_MASK) == LPC17_SPEED_100)
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{
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phyreg = MII_MCR_SPEED100;
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}
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if (fullduplex)
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if ((mode & LPC17_DUPLEX_MASK) == LPC17_DUPLEX_FULL)
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{
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phyreg |= MII_MCR_FULLDPLX;
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}
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@ -1154,72 +1240,11 @@ static int lpc17_phyfixed(uint8_t phyaddr, bool speed100, bool fullduplex)
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}
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}
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nlldbg("Link failed. MSR: %04x\n", phyreg);
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ndbg("Link failed. MSR: %04x\n", phyreg);
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return -ETIMEDOUT;
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}
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#endif
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/****************************************************************************
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* Function: lpc17_phyfulldplex
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*
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* Description:
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* Tweak a few things for full/half duplex.
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*
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* Parameters:
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* phyaddr - The device address where the PHY was discovered
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* fullduplex - TRUE: full duplex
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*
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* Returned Value:
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* None
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*
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* Assumptions:
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*
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****************************************************************************/
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#ifdef LPC17_HAVE_PHY
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static void lpc17_phyduplex(uint8_t phyaddr, bool fullduplex)
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{
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uint32_t regval;
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if (fullduplex)
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{
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/* Set the inter-packet gap */
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lpc17_putreg(21, LPC17_ETH_IPGT);
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/* Set MAC to operate in full duplex mode */
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regval = lpc17_getreg(LPC17_ETH_MAC2);
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regval |= ETH_MAC2_FD;
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lpc17_putreg(regval, LPC17_ETH_MAC2);
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/* Select full duplex operation for ethernet controller */
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regval = lpc17_getreg(LPC17_ETH_CMD);
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regval |= ETH_CMD_FD;
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lpc17_putreg(regval, LPC17_ETH_CMD);
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}
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else
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{
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/* Set the inter-packet gap */
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lpc17_putreg(18, LPC17_ETH_IPGT);
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/* Set MAC to operate in half duplex mode */
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regval = lpc17_getreg(LPC17_ETH_MAC2);
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regval &= ~ETH_MAC2_FD;
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lpc17_putreg(regval, LPC17_ETH_MAC2);
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/* Select half duplex operation for ethernet controller */
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regval = lpc17_getreg(LPC17_ETH_CMD);
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regval &= ~ETH_CMD_FD;
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lpc17_putreg(regval, LPC17_ETH_CMD);
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}
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}
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#endif
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/****************************************************************************
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* Function: lpc17_phyinit
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*
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@ -1230,7 +1255,9 @@ static void lpc17_phyduplex(uint8_t phyaddr, bool fullduplex)
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* priv - Pointer to EMAC device driver structure
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*
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* Returned Value:
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* None
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* None directory.
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* As a side-effect, it will initialize priv->lp_phyaddr and
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* priv->lp_phymode.
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*
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* Assumptions:
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*
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@ -1277,7 +1304,7 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv)
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}
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}
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}
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nlldbg("phyaddr: %d\n", phyaddr);
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nvdbg("phyaddr: %d\n", phyaddr);
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/* Check if the PHY device address was found */
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@ -1333,19 +1360,7 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv)
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#else
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/* Set up the fixed PHY configuration */
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#ifdef CONFIG_PHY_SPEED100
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priv->lp_speed100 = true;
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#else
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priv->lp_speed100 = false;
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#endif
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#ifdef CONFIG_PHY_FDUPLEX
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priv->lp_fullduplex = true;
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#else
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priv->lp_fullduplex = false;
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#endif
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ret = lpc17_phyfixed(phyaddr, priv->lp_speed100, priv->lp_fullduplex);
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ret = lpc17_phymode(phyaddr, LPC17_MODE_DEFLT);
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if (ret < 0)
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{
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return ret;
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@ -1364,42 +1379,119 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv)
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switch (phyreg & KS8721_10BTCR_MODE_MASK)
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{
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case KS8721_10BTCR_MODE_10BTHD: /* 10BASE-T half duplex */
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priv->lp_fullduplex = false;
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priv->lp_speed100 = false;
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priv->lp_mode = LPC17_10BASET_HD;
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lpc17_putreg(0, LPC17_ETH_SUPP);
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break;
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case KS8721_10BTCR_MODE_100BTHD: /* 100BASE-T half duplex */
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priv->lp_fullduplex = false;
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priv->lp_speed100 = true;
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priv->lp_mode = LPC17_100BASET_HD;
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break;
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case KS8721_10BTCR_MODE_10BTFD: /* 10BASE-T full duplex */
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priv->lp_fullduplex = true;
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priv->lp_speed100 = false;
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priv->lp_mode = LPC17_10BASET_FD;
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lpc17_putreg(0, LPC17_ETH_SUPP);
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break;
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case KS8721_10BTCR_MODE_100BTFD: /* 100BASE-T full duplex */
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priv->lp_fullduplex = true;
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priv->lp_speed100 = true;
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priv->lp_mode = LPC17_100BASET_FD;
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break;
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default:
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lldbg("Unrecognized mode: %04x\n", phyreg);
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dbg("Unrecognized mode: %04x\n", phyreg);
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return -ENODEV;
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}
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#else
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# warning "PHY Unknown: speed and duplex are bogus"
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#endif
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nlldbg("%dBase-T %s duplex\n",
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priv->lp_speed100 ? 10 : 100,
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priv->lp_fullduplex ? "full" : "half");
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ndbg("%dBase-T %s duplex\n",
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priv->lp_mode & LPC17_SPEED_MASK == LPC17_SPEED_100 ? 100 : 10,
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priv->lp_mode & LPC17_DUPLEX_MASK == LPC17_DUPLEX_FULL ?"full" : "half");
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/* Configure the MAC for this speed */
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/* Disable auto-configuration. Set the fixed speed/duplex mode.
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* (probably more than little redundant).
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*/
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lpc17_phyduplex(phyaddr, priv->lp_fullduplex);
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lpc17_phyfixed(phyaddr, priv->lp_speed100, priv->lp_fullduplex);
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lpc17_showmii(phyaddr, "At completion");
|
||||
ret = lpc17_phymode(phyaddr, LPC17_MODE_DEFLT);
|
||||
lpc17_showmii(phyaddr, "After final configuration");
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
return OK;
|
||||
/****************************************************************************
|
||||
* Function: lpc17_macmode
|
||||
*
|
||||
* Description:
|
||||
* Set the MAC to operate at a selected speed/duplex mode.
|
||||
*
|
||||
* Parameters:
|
||||
* mode - speed/duplex mode
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
* Assumptions:
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef LPC17_HAVE_PHY
|
||||
static void lpc17_macmode(uint8_t mode)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Set up for full or half duplex operation */
|
||||
|
||||
if ((mode & LPC17_DUPLEX_MASK) == LPC17_DUPLEX_FULL)
|
||||
{
|
||||
/* Set the back-to-back inter-packet gap */
|
||||
|
||||
lpc17_putreg(21, LPC17_ETH_IPGT);
|
||||
|
||||
/* Set MAC to operate in full duplex mode with CRC and Pad enabled */
|
||||
|
||||
regval = lpc17_getreg(LPC17_ETH_MAC2);
|
||||
regval |= (ETH_MAC2_FD | ETH_MAC2_CRCEN | ETH_MAC2_PADCRCEN);
|
||||
lpc17_putreg(regval, LPC17_ETH_MAC2);
|
||||
|
||||
/* Select full duplex operation for ethernet controller */
|
||||
|
||||
regval = lpc17_getreg(LPC17_ETH_CMD);
|
||||
regval |= (ETH_CMD_FD | ETH_CMD_RMII | ETH_CMD_PRFRAME);
|
||||
lpc17_putreg(regval, LPC17_ETH_CMD);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Set the back-to-back inter-packet gap */
|
||||
|
||||
lpc17_putreg(18, LPC17_ETH_IPGT);
|
||||
|
||||
/* Set MAC to operate in half duplex mode with CRC and Pad enabled */
|
||||
|
||||
regval = lpc17_getreg(LPC17_ETH_MAC2);
|
||||
regval &= ~ETH_MAC2_FD;
|
||||
regval |= (ETH_MAC2_CRCEN | ETH_MAC2_PADCRCEN);
|
||||
lpc17_putreg(regval, LPC17_ETH_MAC2);
|
||||
|
||||
/* Select half duplex operation for ethernet controller */
|
||||
|
||||
regval = lpc17_getreg(LPC17_ETH_CMD);
|
||||
regval &= ~ETH_CMD_FD;
|
||||
regval |= (ETH_CMD_RMII | ETH_CMD_PRFRAME);
|
||||
lpc17_putreg(regval, LPC17_ETH_CMD);
|
||||
}
|
||||
|
||||
/* This is currently done in lpc17_phyinit(). That doesn't
|
||||
* seem like the right place. It should be done here.
|
||||
*/
|
||||
|
||||
#if 0
|
||||
regval = lpc17_getreg(LPC17_ETH_SUPP);
|
||||
if ((mode & LPC17_SPEED_MASK) == LPC17_SPEED_100)
|
||||
{
|
||||
regval |= ETH_SUPP_SPEED;
|
||||
}
|
||||
else
|
||||
{
|
||||
regval &= ~ETH_SUPP_SPEED;
|
||||
}
|
||||
lpc17_putreg(regval, LPC17_ETH_SUPP);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -1422,28 +1514,51 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv)
|
||||
static void lpc17_ethreset(struct lpc17_driver_s *priv)
|
||||
{
|
||||
irqstate_t flags;
|
||||
uint32_t regval;
|
||||
|
||||
#if LPC17_NETHCONTROLLERS > 1
|
||||
# error "If multiple interfaces are supported, this function would have to be redesigned"
|
||||
#endif
|
||||
/* Reset the MAC */
|
||||
|
||||
/* Make sure that clocking is enabled for the Ethernet (and PHY) peripherals */
|
||||
flags = irqsave();
|
||||
|
||||
flags = irqsave();
|
||||
/* Put the MAC into the reset state */
|
||||
|
||||
/* Put the Ethernet controller into the reset state */
|
||||
lpc17_putreg((ETH_MAC1_TXRST | ETH_MAC1_MCSTXRST |ETH_MAC1_RXRST |
|
||||
ETH_MAC1_MCSRXRST | ETH_MAC1_SIMRST | ETH_MAC1_SOFTRST),
|
||||
LPC17_ETH_MAC1);
|
||||
|
||||
/* Wait just a bit. This is a much longer delay than necessary */
|
||||
/* Disable RX/RX, clear modes, reset all control registers */
|
||||
|
||||
up_mdelay(2);
|
||||
lpc17_putreg((ETH_CMD_REGRST | ETH_CMD_TXRST | ETH_CMD_RXRST),
|
||||
LPC17_ETH_CMD);
|
||||
|
||||
/* Then take the Ethernet controller out of the reset state */
|
||||
/* Take the MAC out of the reset state */
|
||||
|
||||
up_udelay(50);
|
||||
lpc17_putreg(0, LPC17_ETH_MAC1);
|
||||
|
||||
/* The RMII bit must be set on initialization (I'm not sure
|
||||
* this needs to be done here but... oh well.
|
||||
*/
|
||||
|
||||
lpc17_putreg(ETH_CMD_RMII, LPC17_ETH_CMD);
|
||||
|
||||
/* Set other misc configuration-related registers to default values */
|
||||
|
||||
lpc17_putreg(0, LPC17_ETH_MAC2);
|
||||
lpc17_putreg(0, LPC17_ETH_SUPP);
|
||||
lpc17_putreg(0, LPC17_ETH_TEST);
|
||||
|
||||
lpc17_putreg(18, LPC17_ETH_IPGR);
|
||||
lpc17_putreg(((15 << ETH_CLRT_RMAX_SHIFT) | (55 << ETH_CLRT_COLWIN_SHIFT)),
|
||||
LPC17_ETH_CLRT);
|
||||
lpc17_putreg(0x0600, LPC17_ETH_MAXF);
|
||||
|
||||
/* Disable all Ethernet controller interrupts */
|
||||
|
||||
lpc17_putreg(0, LPC17_ETH_INTEN);
|
||||
|
||||
/* Clear any pending interrupts (shouldn't be any) */
|
||||
|
||||
lpc17_putreg(0xffffffff, LPC17_ETH_INTCLR);
|
||||
irqrestore(flags);
|
||||
}
|
||||
|
||||
@ -1518,12 +1633,11 @@ static inline int lpc17_ethinitialize(int intf)
|
||||
priv->lp_txpoll = wd_create(); /* Create periodic poll timer */
|
||||
priv->lp_txtimeout = wd_create(); /* Create TX timeout timer */
|
||||
|
||||
/* Perform minimal, one-time initialization -- just reset the controller and
|
||||
* leave it disabled. The Ethernet controller will be reset and properly
|
||||
* re-initialized each time lpc17_ifup() is called.
|
||||
/* Reset the Ethernet controller and leave in the ifdown statue. The
|
||||
* Ethernet controller will be properly re-initialized each time
|
||||
* lpc17_ifup() is called.
|
||||
*/
|
||||
|
||||
lpc17_ethreset(priv);
|
||||
lpc17_ifdown(&priv->lp_dev);
|
||||
|
||||
/* Attach the IRQ to the driver */
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user