The commit corrects the gpioirq when mismatch mode is selected and adds support for edge detect mode. Slew Rate was also added for completeness.
This commit is contained in:
Abdelatif Guettouche
Gregory Nutt
parent
6f408b87bf
commit
e5f84dca39
@ -1,7 +1,7 @@
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/********************************************************************************************
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* arch/mips/src/pic32mz/pic32mz-ioport.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Copyright (C) 2015, 2019 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -121,10 +121,30 @@
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#define PIC32MZ_IOPORT_CNENSET_OFFSET 0x0088 /* Change Notice Interrupt Enable set register */
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#define PIC32MZ_IOPORT_CNENINV_OFFSET 0x008c /* Change Notice Interrupt Enable invert register */
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#define PIC32MZ_IOPORT_CNSTAT_OFFSET 0x0080 /* Change Notice Control register */
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#define PIC32MZ_IOPORT_CNSTATCLR_OFFSET 0x0084 /* Change Notice Control clear register*/
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#define PIC32MZ_IOPORT_CNSTATSET_OFFSET 0x0088 /* Change Notice Control set register */
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#define PIC32MZ_IOPORT_CNSTATINV_OFFSET 0x008c /* Change Notice Control invert register */
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#define PIC32MZ_IOPORT_CNSTAT_OFFSET 0x0090 /* Change Notice Status register */
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#define PIC32MZ_IOPORT_CNSTATCLR_OFFSET 0x0094 /* Change Notice Status clear register*/
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#define PIC32MZ_IOPORT_CNSTATSET_OFFSET 0x0098 /* Change Notice Status set register */
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#define PIC32MZ_IOPORT_CNSTATINV_OFFSET 0x009c /* Change Notice Status invert register */
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#define PIC32MZ_IOPORT_CNNE_OFFSET 0x00a0 /* Change Notice Interrupt Enable register */
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#define PIC32MZ_IOPORT_CNNECLR_OFFSET 0x00a4 /* Change Notice Interrupt Enable clear register */
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#define PIC32MZ_IOPORT_CNNESET_OFFSET 0x00a8 /* Change Notice Interrupt Enable set register */
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#define PIC32MZ_IOPORT_CNNEINV_OFFSET 0x00ac /* Change Notice Interrupt Enable invert register */
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#define PIC32MZ_IOPORT_CNF_OFFSET 0x00b0 /* Change Notice Status register */
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#define PIC32MZ_IOPORT_CNFCLR_OFFSET 0x00b4 /* Change Notice Status clear register */
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#define PIC32MZ_IOPORT_CNFSET_OFFSET 0x00b8 /* Change Notice Status set register */
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#define PIC32MZ_IOPORT_CNFINV_OFFSET 0x00bc /* Change Notice Status invert register */
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#define PIC32MZ_IOPORT_SRCON0_OFFSET 0x00c0 /* Slew Rate Control0 register */
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#define PIC32MZ_IOPORT_SRCON0CLR_OFFSET 0x00c4 /* Slew Rate Control0 clear register */
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#define PIC32MZ_IOPORT_SRCON0SET_OFFSET 0x00c8 /* Slew Rate Control0 set register */
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#define PIC32MZ_IOPORT_SRCON0INV_OFFSET 0x00cc /* Slew Rate Control0 invert register */
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#define PIC32MZ_IOPORT_SRCON1_OFFSET 0x00d0 /* Slew Rate Control1 register */
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#define PIC32MZ_IOPORT_SRCON1CLR_OFFSET 0x00d4 /* Slew Rate Control1 clear register */
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#define PIC32MZ_IOPORT_SRCON1SET_OFFSET 0x00d8 /* Slew Rate Control1 set register */
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#define PIC32MZ_IOPORT_SRCON1INV_OFFSET 0x00dc /* Slew Rate Control1 invert register */
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/* IOPort Peripheral Addresses **************************************************************/
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@ -823,7 +843,8 @@
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/* Change Notice Control register */
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#define IOPORT_CNCON_SIDL (1 << 13) /* Bit 13: Stop in idle mode */
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#define IOPORT_CNCON_EDGEDETECT (1 << 11) /* Bit 11: Change Notification Style bit */
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#define IOPORT_CNCON_SIDL (1 << 13) /* Bit 13: Stop in Idle Control bit */
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#define IOPORT_CNCON_ON (1 << 15) /* Bit 15: Change notice module enable */
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/* Change Notice Interrupt Enable register */
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@ -836,6 +857,26 @@
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#define IOPORT_CNSTAT(n) (1 << (n)) /* Bits 0-15: Change notice control pin n */
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#define IOPORT_CNSTAT_ALL 0x0000ffff
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/* Change Notice Interrupt Enable register (Negative edge) */
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#define IOPORT_CNNE(n) (1 << (n)) /* Bits 0-15: 1=Interrupt enabled */
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#define IOPORT_CNNE_ALL 0x0000ffff
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/* Change Notice Status register */
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#define IOPORT_CNF(n) (1 << (n)) /* Bits 0-15: Change notice control pin n */
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#define IOPORT_CNF_ALL 0x0000ffff
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/* Slew Rate Control0 register */
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#define IOPORT_SRCON0(n) (1 << (n)) /* Bits 0-15: Slew Rate control pin n */
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#define IOPORT_SRCON0_ALL 0x0000ffff
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/* Slew Rate Control1 register */
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#define IOPORT_SRCON1(n) (1 << (n)) /* Bits 0-15: Slew Rate control pin n */
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#define IOPORT_SRCON1_ALL 0x0000ffff
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/********************************************************************************************
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* Public Types
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********************************************************************************************/
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@ -507,7 +507,7 @@
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#undef CONFIG_PIC32MZ_FWDTEN
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#ifdef CONFIG_PIC32MZ_WDTENABLE
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# define CONFIG_PIC32MZ_FWDTEN DEVCFG1_FWDT_ENSABLED
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# define CONFIG_PIC32MZ_FWDTEN DEVCFG1_FWDT_ENABLED
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#else
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# define CONFIG_PIC32MZ_FWDTEN DEVCFG1_FWDT_DISABLED
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#endif
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@ -113,7 +113,7 @@ static inline bool pic32mz_output(pinset_t pinset)
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static inline bool pic32mz_opendrain(pinset_t pinset)
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{
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return ((pinset & GPIO_MODE_MASK) == GPIO_OPENDRAN);
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return ((pinset & GPIO_MODE_MASK) == GPIO_OPENDRAIN);
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}
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static inline bool pic32mz_outputhigh(pinset_t pinset)
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@ -141,6 +141,21 @@ static inline unsigned int pic32mz_analog(pinset_t pinset)
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return ((pinset & GPIO_ANALOG_MASK) != 0);
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}
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static inline unsigned int pic32mz_slewrate(pinset_t pinset)
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{
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return ((pinset & GPIO_SR_MASK) >> GPIO_SR_SHIFT);
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}
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static inline unsigned int pic32mz_slewratecon0(pinset_t pinset)
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{
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return (pic32mz_slewrate(pinset) & GPIO_SR_CON0_MASK) >> GPIO_SR_CON0_SHIFT;
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}
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static inline unsigned int pic32mz_slewratecon1(pinset_t pinset)
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{
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return (pic32mz_slewrate(pinset) & GPIO_SR_CON1_MASK) >> GPIO_SR_CON1_SHIFT;
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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@ -172,9 +187,24 @@ int pic32mz_configgpio(pinset_t cfgset)
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base = g_gpiobase[port];
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sched_lock();
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/* Is Slew Rate control enabled? */
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if (pic32mz_slewrate(cfgset) != GPIO_FASTEST)
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{
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/* Note: not every port nor every pin has the Slew Rate feature.
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* Writing to an unimplemented port/pin will have no effect.
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*/
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putreg32(pic32mz_slewratecon0(cfgset),
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base + PIC32MZ_IOPORT_SRCON0_OFFSET);
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putreg32(pic32mz_slewratecon1(cfgset),
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base + PIC32MZ_IOPORT_SRCON1_OFFSET);
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}
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/* Is this an input or an output? */
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sched_lock();
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if (pic32mz_output(cfgset))
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{
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/* Not analog */
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@ -308,7 +338,7 @@ bool pic32mz_gpioread(pinset_t pinset)
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****************************************************************************/
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#ifdef CONFIG_DEBUG_GPIO_INFO
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void pic32mz_dumpgpio(uint32_t pinset, const char *msg)
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void pic32mz_dumpgpio(pinset_t pinset, const char *msg)
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{
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unsigned int port = pic32mz_portno(pinset);
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irqstate_t flags;
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@ -51,28 +51,84 @@
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/* GPIO settings used in the configport, readport, writeport, etc.
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*
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* General encoding:
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* MMAV IIDR RRRx PPPP
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* xxxx xxxx xxxx xSSM MAVI IIII RRRR PPPP
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*
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* x = Not implemented
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* S = Slew Rate
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* M = Mode (input/output)
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* I = Interrupt
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* R = Register
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* P = Pin
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*/
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#define GPIO_MODE_SHIFT (14) /* Bits 14-15: I/O mode */
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/* Slew Rate Control.
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*
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* .... .... .... .SS. .... .... .... ....
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*/
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#define GPIO_SR_SHIFT (17) /* Bits 17-18: Slew Rate Control */
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#define GPIO_SR_MASK (3 << GPIO_SR_SHIFT)
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# define GPIO_FASTEST (0 << GPIO_SR_SHIFT) /* 00: Disabled and set to fastest */
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# define GPIO_MEDIUM (1 << GPIO_SR_SHIFT) /* 01: Enabled and set to medium */
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# define GPIO_SLOW (2 << GPIO_SR_SHIFT) /* 10: Enabled and set to slow */
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# define GPIO_SLOWEST (3 << GPIO_SR_SHIFT) /* 11: Enabled and set to slowest */
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#define GPIO_SR_CON0_SHIFT (0) /* Bit 0: SRCON0x */
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#define GPIO_SR_CON0_MASK (1 << GPIO_SR_CON0_SHIFT)
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#define GPIO_SR_CON1_SHIFT (1) /* Bit 1: SRCON1x */
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#define GPIO_SR_CON1_MASK (1 << GPIO_SR_CON1_SHIFT)
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/* Input/Output mode:
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*
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* .... .... .... ...M M... .... .... ....
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*/
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#define GPIO_MODE_SHIFT (15) /* Bits 15-16: I/O mode */
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#define GPIO_MODE_MASK (3 << GPIO_MODE_SHIFT)
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# define GPIO_INPUT (0 << GPIO_MODE_SHIFT) /* 00 Normal input */
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# define GPIO_OUTPUT (2 << GPIO_MODE_SHIFT) /* 10 Normal output */
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# define GPIO_OPENDRAN (3 << GPIO_MODE_SHIFT) /* 11 Open drain output */
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# define GPIO_OPENDRAIN (3 << GPIO_MODE_SHIFT) /* 11 Open drain output */
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#define GPIO_ANALOG_MASK (1 << 13) /* Bit 13: Analog */
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# define GPIO_ANALOG (1 << 13)
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/* Analog mode.
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*
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* .... .... .... .... .A.. .... .... ....
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*/
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#define GPIO_ANALOG_SHIFT (14) /* Bit 14: Analog */
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#define GPIO_ANALOG_MASK (1 << GPIO_ANALOG_SHIFT)
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# define GPIO_ANALOG (1 << GPIO_ANALOG_SHIFT)
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# define GPIO_DIGITAL (0)
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#define GPIO_VALUE_MASK (1 << 12) /* Bit 12: Initial output value */
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# define GPIO_VALUE_ONE (1 << 12)
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/* Pin Value.
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*
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* .... .... .... .... ..V. .... .... ....
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*/
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#define GPIO_VALUE_SHIFT (13) /* Bit 13: Initializetial output value */
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#define GPIO_VALUE_MASK (1 << GPIO_VALUE_SHIFT)
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# define GPIO_VALUE_ONE (1 << GPIO_VALUE_SHIFT)
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# define GPIO_VALUE_ZERO (0)
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#define GPIO_INTERRUPT (1 << 11) /* Bit 11: Change notification enable */
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#define GPIO_PULLUP (1 << 10) /* Bit 10: Change notification pull-up */
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#define GPIO_PULLDOWN (1 << 9) /* Bit 9: Change notification pull-down */
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/* Change Notification config.
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*
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* .... .... .... .... ...I IIII .... ....
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*/
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#define GPIO_PORT_SHIFT (5) /* Bits 5-8: Port number */
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#define GPIO_CN_SHIFT (8) /* Bit 8 - 12: Change notification bits */
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#define GPIO_CN_MASK (31 << GPIO_CN_SHIFT)
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# define GPIO_INTERRUPT (1 << GPIO_CN_SHIFT) /* Bit 8: Change notification enable bit */
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# define GPIO_PULLUP (2 << GPIO_CN_SHIFT) /* Bit 9: Change notification pull-up */
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# define GPIO_PULLDOWN (4 << GPIO_CN_SHIFT) /* Bit 10: Change notification pull-down */
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# define GPIO_EDGE_DETECT (8 << GPIO_CN_SHIFT) /* Bit 11: Change notification interrupt mode */
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# define GPIO_MISMATCH (0)
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# define GPIO_EDGE_RISING (12 << GPIO_CN_SHIFT) /* Bit 12: Change notification edge type */
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# define GPIO_EDGE_FALLING (0)
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/* GPIO Port.
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*
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* .... .... .... .... .... .... RRRR ....
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*/
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#define GPIO_PORT_SHIFT (4) /* Bits 4-7: Port number */
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#define GPIO_PORT_MASK (15 << GPIO_PORT_SHIFT)
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# define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
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# define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
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@ -85,6 +141,11 @@
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# define GPIO_PORTJ (8 << GPIO_PORT_SHIFT)
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# define GPIO_PORTK (9 << GPIO_PORT_SHIFT)
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/* GPIO Pin.
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*
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* .... .... .... .... .... .... .... PPPP
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*/
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#define GPIO_PIN_SHIFT 0 /* Bits 0-3: GPIO number: 0-15 */
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#define GPIO_PIN_MASK (15 << GPIO_PIN_SHIFT)
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#define GPIO_PIN0 (0 << GPIO_PIN_SHIFT)
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@ -110,7 +171,7 @@
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#ifndef __ASSEMBLY__
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typedef uint16_t pinset_t;
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typedef uint32_t pinset_t;
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/************************************************************************************
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* Public Data
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@ -210,7 +271,7 @@ void pic32mz_gpioirqinitialize(void);
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****************************************************************************/
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#ifdef CONFIG_PIC32MZ_GPIOIRQ
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int pic32mz_gpioattach(uint32_t pinset, xcpt_t handler, void *arg);
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int pic32mz_gpioattach(pinset_t pinset, xcpt_t handler, void *arg);
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#else
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# define pic32mz_gpioattach(p,h,a) (0)
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#endif
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@ -252,7 +313,7 @@ void pic32mz_gpioirqdisable(pinset_t pinset);
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************************************************************************************/
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#ifdef CONFIG_DEBUG_GPIO_INFO
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void pic32mz_dumpgpio(uint32_t pinset, const char *msg);
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void pic32mz_dumpgpio(pinset_t pinset, const char *msg);
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#else
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# define pic32mz_dumpgpio(p,m)
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#endif
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@ -70,6 +70,8 @@ static inline unsigned int pic32mz_ioport(pinset_t pinset);
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static inline unsigned int pic32mz_pin(pinset_t pinset);
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static inline bool pic32mz_input(pinset_t pinset);
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static inline bool pic32mz_interrupt(pinset_t pinset);
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static inline bool pic32mz_edgedetect(pinset_t pinset);
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static inline unsigned int pic32mz_edgemode(pinset_t pinset);
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static inline bool pic32mz_pullup(pinset_t pinset);
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static inline bool pic32mz_pulldown(pinset_t pinset);
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static int pic32mz_cninterrupt(int irq, FAR void *context, FAR void *arg);
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@ -174,7 +176,7 @@ static struct ioport_level2_s * const g_level2_handlers[CHIP_NPORTS] =
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static inline bool pic32mz_input(pinset_t pinset)
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{
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return ((pinset & GPIO_MODE_MASK) != GPIO_INPUT);
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return (((pinset & GPIO_MODE_MASK) >> GPIO_MODE_SHIFT) == GPIO_INPUT);
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}
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static inline bool pic32mz_interrupt(pinset_t pinset)
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@ -182,6 +184,16 @@ static inline bool pic32mz_interrupt(pinset_t pinset)
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return ((pinset & GPIO_INTERRUPT) != 0);
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}
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static inline bool pic32mz_edgedetect(pinset_t pinset)
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{
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return ((pinset & GPIO_EDGE_DETECT) != 0);
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}
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static inline unsigned int pic32mz_edgemode(pinset_t pinset)
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{
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return ((pinset & GPIO_EDGE_RISING));
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}
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static inline bool pic32mz_pullup(pinset_t pinset)
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{
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return ((pinset & GPIO_PULLUP) != 0);
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@ -215,8 +227,11 @@ static int pic32mz_cninterrupt(int irq, FAR void *context, FAR void *arg)
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struct ioport_level2_s *handlers;
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xcpt_t handler;
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uintptr_t base;
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uint32_t cnstat;
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uint32_t cncon;
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uint32_t cnen;
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uint32_t cnne;
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uint32_t cnstat;
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uint32_t cnf;
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uint32_t pending;
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uint32_t regval;
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int ioport;
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@ -240,29 +255,29 @@ static int pic32mz_cninterrupt(int irq, FAR void *context, FAR void *arg)
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base = g_gpiobase[ioport];
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DEBUGASSERT(handlers && base);
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/* Get the control registers. It will be used to get the interrupt type. */
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cncon = getreg32(base + PIC32MZ_IOPORT_CNCON_OFFSET);
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if (handlers && base)
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{
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/* Mismatch mode selected? */
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if ((cncon & IOPORT_CNCON_EDGEDETECT) == 0)
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{
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/* Get the interrupt status associated with this interrupt */
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cnstat = getreg32(base + PIC32MZ_IOPORT_CNSTAT_OFFSET);
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cnen = getreg32(base + PIC32MZ_IOPORT_CNSTAT_OFFSET);
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cnen = getreg32(base + PIC32MZ_IOPORT_CNEN_OFFSET);
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pending = cnstat & cnen;
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/* Hmmm.. the data sheet implies that the status will pend
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* until the corresponding PORTx registers is read? Clear
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* pending status.
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*/
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regval = getreg32(base + PIC32MZ_IOPORT_PORT_OFFSET);
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UNUSED(regval);
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/* Call all attached handlers for each pending interrupt */
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for (i = 0; i < 16; i++)
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{
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/* Is this interrupt pending */
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if ((pending & (1 << IOPORT_CNSTAT(i))) != 0)
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if ((pending & (IOPORT_CNSTAT(i))) != 0)
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{
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/* Yes.. Has the user attached a handler? */
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@ -284,6 +299,61 @@ static int pic32mz_cninterrupt(int irq, FAR void *context, FAR void *arg)
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}
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}
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}
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/* Clear pending status. */
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regval = getreg32(base + PIC32MZ_IOPORT_PORT_OFFSET);
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UNUSED(regval);
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}
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/* Edge detect mode selected. */
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else
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{
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/* Get the interrupt status associated with this interrupt.
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* The interrupt is controlled by either CNEN (positive edge)
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* or CNNE (negative edge).
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*/
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cnen = getreg32(base + PIC32MZ_IOPORT_CNEN_OFFSET);
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cnne = getreg32(base + PIC32MZ_IOPORT_CNNE_OFFSET);
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cnf = getreg32(base + PIC32MZ_IOPORT_CNF_OFFSET);
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pending = cnf & (cnen | cnne);
|
||||
|
||||
/* Call all attached handlers for each pending interrupt */
|
||||
|
||||
for (i = 0; i < 16; i++)
|
||||
{
|
||||
/* Is this interrupt pending */
|
||||
|
||||
if ((pending & (IOPORT_CNF(i))) != 0)
|
||||
{
|
||||
/* Yes.. Has the user attached a handler? */
|
||||
|
||||
handler = handlers->handler[i].entry;
|
||||
if (handler)
|
||||
{
|
||||
/* Yes.. call the attached handler */
|
||||
|
||||
status = handler(irq, context, handlers->handler[i].arg);
|
||||
|
||||
/* Keep track of the status of the last handler that
|
||||
* failed.
|
||||
*/
|
||||
|
||||
if (status < 0)
|
||||
{
|
||||
ret = status;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Clear pending status. */
|
||||
|
||||
putreg32(pending, base + PIC32MZ_IOPORT_CNFCLR_OFFSET);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/* Clear the pending interrupt */
|
||||
@ -309,6 +379,7 @@ static int pic32mz_cninterrupt(int irq, FAR void *context, FAR void *arg)
|
||||
void pic32mz_gpioirqinitialize(void)
|
||||
{
|
||||
uintptr_t base;
|
||||
uint32_t regval;
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
@ -327,6 +398,7 @@ void pic32mz_gpioirqinitialize(void)
|
||||
/* Reset all registers and disable the CN module */
|
||||
|
||||
putreg32(IOPORT_CNEN_ALL, base + PIC32MZ_IOPORT_CNENCLR_OFFSET);
|
||||
putreg32(IOPORT_CNNE_ALL, base + PIC32MZ_IOPORT_CNNECLR_OFFSET);
|
||||
putreg32(IOPORT_CNPU_ALL, base + PIC32MZ_IOPORT_CNPUCLR_OFFSET);
|
||||
putreg32(IOPORT_CNPD_ALL, base + PIC32MZ_IOPORT_CNPDCLR_OFFSET);
|
||||
putreg32(0, base + PIC32MZ_IOPORT_CNCON_OFFSET);
|
||||
@ -350,9 +422,14 @@ void pic32mz_gpioirqinitialize(void)
|
||||
|
||||
putreg32(IOPORT_CNCON_ON, base + PIC32MZ_IOPORT_CNCON_OFFSET);
|
||||
|
||||
/* And enable the GPIO interrupt. Same assumption as above. */
|
||||
/* Read the port to clear the interrupt. */
|
||||
|
||||
up_enable_irq(PIC32MZ_IRQ_PORTA + i);
|
||||
regval = getreg32(base + PIC32MZ_IOPORT_PORT_OFFSET);
|
||||
UNUSED(regval);
|
||||
|
||||
/* Clear the CN interrupt flag. Same assumption as above. */
|
||||
|
||||
up_clrpend_irq(PIC32MZ_IRQ_PORTA + i);
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -382,8 +459,7 @@ void pic32mz_gpioirqinitialize(void)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_PIC32MZ_GPIOIRQ
|
||||
int pic32mz_gpioattach(uint32_t pinset, xcpt_t handler, void *arg)
|
||||
int pic32mz_gpioattach(pinset_t pinset, xcpt_t handler, void *arg)
|
||||
{
|
||||
struct ioport_level2_s *handlers;
|
||||
irqstate_t flags;
|
||||
@ -391,8 +467,6 @@ int pic32mz_gpioattach(uint32_t pinset, xcpt_t handler, void *arg)
|
||||
int ioport;
|
||||
int pin;
|
||||
|
||||
DEBUGASSERT(pin < IOPORT_NUMCN);
|
||||
|
||||
/* First verify that the pinset is configured as an interrupting input */
|
||||
|
||||
if (pic32mz_input(pinset) && pic32mz_interrupt(pinset))
|
||||
@ -468,6 +542,7 @@ int pic32mz_gpioattach(uint32_t pinset, xcpt_t handler, void *arg)
|
||||
*/
|
||||
|
||||
putreg32(1 << pin, base + PIC32MZ_IOPORT_CNENCLR_OFFSET);
|
||||
putreg32(1 << pin, base + PIC32MZ_IOPORT_CNNECLR_OFFSET);
|
||||
|
||||
/* Set the new handler (perhaps NULLifying the current handler) */
|
||||
|
||||
@ -506,13 +581,44 @@ void pic32mz_gpioirqenable(pinset_t pinset)
|
||||
DEBUGASSERT(base);
|
||||
if (base)
|
||||
{
|
||||
/* And enable the interrupt. NOTE that we don't actually check if
|
||||
/* Enable the correct CN interrupt.
|
||||
* NOTE that we don't actually check if
|
||||
* interrupts are configured for this IO port. If not, this operation
|
||||
* should do nothing.
|
||||
*/
|
||||
|
||||
if (!pic32mz_edgedetect(pinset))
|
||||
{
|
||||
/* If Edge detect is not selected, then CNEN
|
||||
* controls the interrupt.
|
||||
*/
|
||||
|
||||
putreg32(1 << pin, base + PIC32MZ_IOPORT_CNENSET_OFFSET);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Enable edge detect. */
|
||||
|
||||
putreg32(IOPORT_CNCON_EDGEDETECT, base + PIC32MZ_IOPORT_CNCONSET_OFFSET);
|
||||
|
||||
if (pic32mz_edgemode(pinset) == GPIO_EDGE_RISING)
|
||||
{
|
||||
/* Rising edge selected. CNEN controls the interrupt. */
|
||||
|
||||
putreg32(1 << pin, base + PIC32MZ_IOPORT_CNENSET_OFFSET);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Falling edge selected. CNNE controls the interrupt. */
|
||||
|
||||
putreg32(1 << pin, base + PIC32MZ_IOPORT_CNNESET_OFFSET);
|
||||
}
|
||||
}
|
||||
|
||||
/* And enable the interrupt. */
|
||||
|
||||
up_enable_irq(ioport + PIC32MZ_IRQ_PORTA);
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@ -541,13 +647,40 @@ void pic32mz_gpioirqdisable(pinset_t pinset)
|
||||
DEBUGASSERT(base);
|
||||
if (base)
|
||||
{
|
||||
/* And disable the interrupt. NOTE that we don't actually check if
|
||||
/* And disable the correct interrupt.
|
||||
* NOTE that we don't actually check if
|
||||
* interrupts are configured for this IO port. If not, this operation
|
||||
* should do nothing.
|
||||
*/
|
||||
|
||||
if (!pic32mz_edgedetect(pinset))
|
||||
{
|
||||
/* If Edge detect is not selected, then CNEN
|
||||
* controls the interrupt.
|
||||
*/
|
||||
|
||||
putreg32(1 << pin, base + PIC32MZ_IOPORT_CNENCLR_OFFSET);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (pic32mz_edgemode(pinset) == GPIO_EDGE_RISING)
|
||||
{
|
||||
/* Rising edge selected.
|
||||
* CNEN controls the interrupt.
|
||||
*/
|
||||
|
||||
putreg32(1 << pin, base + PIC32MZ_IOPORT_CNENCLR_OFFSET);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Falling edge selected.
|
||||
* CNNE controls the interrupt.
|
||||
*/
|
||||
|
||||
putreg32(1 << pin, base + PIC32MZ_IOPORT_CNNECLR_OFFSET);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* CONFIG_PIC32MZ_GPIOIRQ */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user