Costmetic changes from the review of the last PR
This commit is contained in:
Gregory Nutt
parent
1c0faf69a1
commit
e65bcccaa2
@ -117,131 +117,131 @@
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/* Control register 1 */
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#define I2C_CR1_PE (1 << 0) /* Bit 0: Peripheral Enable */
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#define I2C_CR1_TXIE (1 << 1) /* Bit 1: TX Interrupt enable */
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#define I2C_CR1_RXIE (1 << 2) /* Bit 2: RX Interrupt enable */
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#define I2C_CR1_ADDRIE (1 << 3) /* Bit 3: Address match interrupt enable (slave) */
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#define I2C_CR1_NACKIE (1 << 4) /* Bit 4: Not acknowledge received interrupt enable */
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#define I2C_CR1_STOPIE (1 << 5) /* Bit 5: STOP detection interrupt enable */
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#define I2C_CR1_TCIE (1 << 6) /* Bit 6: Transfer Complete interrupt enable */
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#define I2C_CR1_ERRIE (1 << 7) /* Bit 7: Error interrupts enable */
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#define I2C_CR1_DNF_SHIFT (8) /* Bits 8-11: Digital noise filter */
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#define I2C_CR1_DNF_MASK (0xf << I2C_CR1_DNF_SHIFT)
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# define I2C_CR1_DNF_DISABLE (0 << I2C_CR1_DNF_SHIFT)
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# define I2C_CR1_DNF(n) ((n) << I2C_CR1_DNF_SHIFT) /* Up to n * Ti2cclk, n=1..15 */
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#define I2C_CR1_ANFOFF (1 << 12) /* Bit 12: Analog noise filter OFF */
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#define I2C_CR1_TXDMAEN (1 << 14) /* Bit 14: DMA transmission requests enable */
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#define I2C_CR1_RXDMAEN (1 << 15) /* Bit 15: DMA reception requests enable */
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#define I2C_CR1_SBC (1 << 16) /* Bit 16: Slave byte control */
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#define I2C_CR1_NOSTRETCH (1 << 17) /* Bit 17: Clock stretching disable */
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#define I2C_CR1_GCEN (1 << 19) /* Bit 19: General call enable */
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#define I2C_CR1_SMBHEN (1 << 20) /* Bit 20: SMBus Host address enable */
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#define I2C_CR1_SMBDEN (1 << 21) /* Bit 21: SMBus Device Default address enable */
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#define I2C_CR1_ALERTEN (1 << 22) /* Bit 22: SMBus alert enable */
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#define I2C_CR1_PECEN (1 << 23) /* Bit 23: PEC enable */
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#define I2C_CR1_PE (1 << 0) /* Bit 0: Peripheral Enable */
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#define I2C_CR1_TXIE (1 << 1) /* Bit 1: TX Interrupt enable */
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#define I2C_CR1_RXIE (1 << 2) /* Bit 2: RX Interrupt enable */
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#define I2C_CR1_ADDRIE (1 << 3) /* Bit 3: Address match interrupt enable (slave) */
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#define I2C_CR1_NACKIE (1 << 4) /* Bit 4: Not acknowledge received interrupt enable */
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#define I2C_CR1_STOPIE (1 << 5) /* Bit 5: STOP detection interrupt enable */
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#define I2C_CR1_TCIE (1 << 6) /* Bit 6: Transfer Complete interrupt enable */
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#define I2C_CR1_ERRIE (1 << 7) /* Bit 7: Error interrupts enable */
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#define I2C_CR1_DNF_SHIFT (8) /* Bits 8-11: Digital noise filter */
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#define I2C_CR1_DNF_MASK (0xf << I2C_CR1_DNF_SHIFT)
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# define I2C_CR1_DNF_DISABLE (0 << I2C_CR1_DNF_SHIFT)
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# define I2C_CR1_DNF(n) ((n) << I2C_CR1_DNF_SHIFT) /* Up to n * Ti2cclk, n=1..15 */
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#define I2C_CR1_ANFOFF (1 << 12) /* Bit 12: Analog noise filter OFF */
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#define I2C_CR1_TXDMAEN (1 << 14) /* Bit 14: DMA transmission requests enable */
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#define I2C_CR1_RXDMAEN (1 << 15) /* Bit 15: DMA reception requests enable */
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#define I2C_CR1_SBC (1 << 16) /* Bit 16: Slave byte control */
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#define I2C_CR1_NOSTRETCH (1 << 17) /* Bit 17: Clock stretching disable */
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#define I2C_CR1_GCEN (1 << 19) /* Bit 19: General call enable */
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#define I2C_CR1_SMBHEN (1 << 20) /* Bit 20: SMBus Host address enable */
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#define I2C_CR1_SMBDEN (1 << 21) /* Bit 21: SMBus Device Default address enable */
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#define I2C_CR1_ALERTEN (1 << 22) /* Bit 22: SMBus alert enable */
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#define I2C_CR1_PECEN (1 << 23) /* Bit 23: PEC enable */
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/* Control register 2 */
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#define I2C_CR2_SADD10_SHIFT (0) /* Bits 0-9: Slave 10-bit address (master) */
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#define I2C_CR2_SADD10_MASK (0x3ff << I2C_CR2_SADD10_SHIFT)
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#define I2C_CR2_SADD7_SHIFT (1) /* Bits 1-7: Slave 7-bit address (master) */
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#define I2C_CR2_SADD7_MASK (0x7f << I2C_CR2_SADD7_SHIFT)
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#define I2C_CR2_RD_WRN (1 << 10) /* Bit 10: Transfer direction (master) */
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#define I2C_CR2_ADD10 (1 << 11) /* Bit 11: 10-bit addressing mode (master) */
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#define I2C_CR2_HEAD10R (1 << 12) /* Bit 12: 10-bit address header only read direction (master) */
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#define I2C_CR2_START (1 << 13) /* Bit 13: Start generation */
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#define I2C_CR2_STOP (1 << 14) /* Bit 14: Stop generation (master) */
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#define I2C_CR2_NACK (1 << 15) /* Bit 15: NACK generation (slave) */
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#define I2C_CR2_NBYTES_SHIFT (16) /* Bits 16-23: Number of bytes */
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#define I2C_CR2_NBYTES_MASK (0xff << I2C_CR2_NBYTES_SHIFT)
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#define I2C_CR2_RELOAD (1 << 24) /* Bit 24: NBYTES reload mode */
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#define I2C_CR2_AUTOEND (1 << 25) /* Bit 25: Automatic end mode (master) */
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#define I2C_CR2_PECBYTE (1 << 26) /* Bit 26: Packet error checking byte */
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#define I2C_CR2_SADD10_SHIFT (0) /* Bits 0-9: Slave 10-bit address (master) */
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#define I2C_CR2_SADD10_MASK (0x3ff << I2C_CR2_SADD10_SHIFT)
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#define I2C_CR2_SADD7_SHIFT (1) /* Bits 1-7: Slave 7-bit address (master) */
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#define I2C_CR2_SADD7_MASK (0x7f << I2C_CR2_SADD7_SHIFT)
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#define I2C_CR2_RD_WRN (1 << 10) /* Bit 10: Transfer direction (master) */
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#define I2C_CR2_ADD10 (1 << 11) /* Bit 11: 10-bit addressing mode (master) */
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#define I2C_CR2_HEAD10R (1 << 12) /* Bit 12: 10-bit address header only read direction (master) */
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#define I2C_CR2_START (1 << 13) /* Bit 13: Start generation */
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#define I2C_CR2_STOP (1 << 14) /* Bit 14: Stop generation (master) */
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#define I2C_CR2_NACK (1 << 15) /* Bit 15: NACK generation (slave) */
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#define I2C_CR2_NBYTES_SHIFT (16) /* Bits 16-23: Number of bytes */
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#define I2C_CR2_NBYTES_MASK (0xff << I2C_CR2_NBYTES_SHIFT)
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#define I2C_CR2_RELOAD (1 << 24) /* Bit 24: NBYTES reload mode */
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#define I2C_CR2_AUTOEND (1 << 25) /* Bit 25: Automatic end mode (master) */
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#define I2C_CR2_PECBYTE (1 << 26) /* Bit 26: Packet error checking byte */
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/* Own address register 1 */
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#define I2C_OAR1_OA1_10_SHIFT (0) /* Bits 0-9: 10-bit interface address */
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#define I2C_OAR1_OA1_10_MASK (0x3ff << I2C_OAR1_OA1_10_SHIFT)
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#define I2C_OAR1_OA1_7_SHIFT (1) /* Bits 1-7: 7-bit interface address */
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#define I2C_OAR1_OA1_7_MASK (0x7f << I2C_OAR1_OA1_7_SHIFT)
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#define I2C_OAR1_OA1MODE (1 << 10) /* Bit 10: Own Address 1 10-bit mode */
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#define I2C_OAR1_OA1EN (1 << 15) /* Bit 15: Own Address 1 enable */
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#define I2C_OAR1_OA1_10_SHIFT (0) /* Bits 0-9: 10-bit interface address */
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#define I2C_OAR1_OA1_10_MASK (0x3ff << I2C_OAR1_OA1_10_SHIFT)
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#define I2C_OAR1_OA1_7_SHIFT (1) /* Bits 1-7: 7-bit interface address */
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#define I2C_OAR1_OA1_7_MASK (0x7f << I2C_OAR1_OA1_7_SHIFT)
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#define I2C_OAR1_OA1MODE (1 << 10) /* Bit 10: Own Address 1 10-bit mode */
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#define I2C_OAR1_OA1EN (1 << 15) /* Bit 15: Own Address 1 enable */
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/* Own address register 2 */
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#define I2C_OAR2_OA2_SHIFT (1) /* Bits 1-7: 7-bit interface address */
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#define I2C_OAR2_OA2_MASK (0x7f << I2C_OAR2_OA2_SHIFT)
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#define I2C_OAR2_OA2MSK_SHIFT (8) /* Bits 8-10: Own Address 2 masks */
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#define I2C_OAR2_OA2MSK_MASK (7 << I2C_OAR2_OA2MSK_SHIFT)
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# define I2C_OAR2_OA2MSK_NONE (0 << I2C_OAR2_OA2MSK_SHIFT) /* No mask */
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# define I2C_OAR2_OA2MSK_2_7 (1 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:2] are compared */
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# define I2C_OAR2_OA2MSK_3_7 (2 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:3] are compared */
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# define I2C_OAR2_OA2MSK_4_7 (3 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:4] are compared */
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# define I2C_OAR2_OA2MSK_5_7 (4 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:5] are compared */
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# define I2C_OAR2_OA2MSK_6_7 (5 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:6] are compared */
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# define I2C_OAR2_OA2MSK_7 (6 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7] is compared */
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# define I2C_OAR2_OA2MSK_ALL (7 << I2C_OAR2_OA2MSK_SHIFT) /* All 7-bit addresses acknowledged */
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#define I2C_OAR2_OA2EN (1 << 15) /* Bit 15: Own Address 2 enable */
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#define I2C_OAR2_OA2_SHIFT (1) /* Bits 1-7: 7-bit interface address */
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#define I2C_OAR2_OA2_MASK (0x7f << I2C_OAR2_OA2_SHIFT)
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#define I2C_OAR2_OA2MSK_SHIFT (8) /* Bits 8-10: Own Address 2 masks */
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#define I2C_OAR2_OA2MSK_MASK (7 << I2C_OAR2_OA2MSK_SHIFT)
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# define I2C_OAR2_OA2MSK_NONE (0 << I2C_OAR2_OA2MSK_SHIFT) /* No mask */
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# define I2C_OAR2_OA2MSK_2_7 (1 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:2] are compared */
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# define I2C_OAR2_OA2MSK_3_7 (2 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:3] are compared */
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# define I2C_OAR2_OA2MSK_4_7 (3 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:4] are compared */
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# define I2C_OAR2_OA2MSK_5_7 (4 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:5] are compared */
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# define I2C_OAR2_OA2MSK_6_7 (5 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:6] are compared */
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# define I2C_OAR2_OA2MSK_7 (6 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7] is compared */
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# define I2C_OAR2_OA2MSK_ALL (7 << I2C_OAR2_OA2MSK_SHIFT) /* All 7-bit addresses acknowledged */
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#define I2C_OAR2_OA2EN (1 << 15) /* Bit 15: Own Address 2 enable */
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/* Timing register */
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#define I2C_TIMINGR_SCLL_SHIFT (0) /* Bits 0-7: SCL low period (master) */
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#define I2C_TIMINGR_SCLL_MASK (0xff << I2C_TIMINGR_SCLL_SHIFT)
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# define I2C_TIMINGR_SCLL(n) (((n)-1) << I2C_TIMINGR_SCLL_SHIFT) /* tSCLL = n x tPRESC */
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#define I2C_TIMINGR_SCLL_SHIFT (0) /* Bits 0-7: SCL low period (master) */
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#define I2C_TIMINGR_SCLL_MASK (0xff << I2C_TIMINGR_SCLL_SHIFT)
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# define I2C_TIMINGR_SCLL(n) (((n)-1) << I2C_TIMINGR_SCLL_SHIFT) /* tSCLL = n x tPRESC */
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#define I2C_TIMINGR_SCLH_SHIFT (8) /* Bits 8-15: SCL high period (master) */
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#define I2C_TIMINGR_SCLH_MASK (0xff << I2C_TIMINGR_SCLH_SHIFT)
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# define I2C_TIMINGR_SCLH(n) (((n)-1) << I2C_TIMINGR_SCLH_SHIFT) /* tSCLH = n x tPRESC */
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#define I2C_TIMINGR_SCLH_SHIFT (8) /* Bits 8-15: SCL high period (master) */
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#define I2C_TIMINGR_SCLH_MASK (0xff << I2C_TIMINGR_SCLH_SHIFT)
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# define I2C_TIMINGR_SCLH(n) (((n)-1) << I2C_TIMINGR_SCLH_SHIFT) /* tSCLH = n x tPRESC */
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#define I2C_TIMINGR_SDADEL_SHIFT (16) /* Bits 16-19: Data hold time */
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#define I2C_TIMINGR_SDADEL_MASK (0xf << I2C_TIMINGR_SDADEL_SHIFT)
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# define I2C_TIMINGR_SDADEL(n) ((n) << I2C_TIMINGR_SDADEL_SHIFT) /* tSDADEL= n x tPRESC */
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#define I2C_TIMINGR_SDADEL_SHIFT (16) /* Bits 16-19: Data hold time */
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#define I2C_TIMINGR_SDADEL_MASK (0xf << I2C_TIMINGR_SDADEL_SHIFT)
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# define I2C_TIMINGR_SDADEL(n) ((n) << I2C_TIMINGR_SDADEL_SHIFT) /* tSDADEL= n x tPRESC */
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#define I2C_TIMINGR_SCLDEL_SHIFT (20) /* Bits 20-23: Data setup time */
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#define I2C_TIMINGR_SCLDEL_MASK (0xf << I2C_TIMINGR_SCLDEL_SHIFT)
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# define I2C_TIMINGR_SCLDEL(n) (((n)-1) << I2C_TIMINGR_SCLDEL_SHIFT) /* tSCLDEL = n x tPRESC */
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#define I2C_TIMINGR_SCLDEL_SHIFT (20) /* Bits 20-23: Data setup time */
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#define I2C_TIMINGR_SCLDEL_MASK (0xf << I2C_TIMINGR_SCLDEL_SHIFT)
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# define I2C_TIMINGR_SCLDEL(n) (((n)-1) << I2C_TIMINGR_SCLDEL_SHIFT) /* tSCLDEL = n x tPRESC */
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#define I2C_TIMINGR_PRESC_SHIFT (28) /* Bits 28-31: Timing prescaler */
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#define I2C_TIMINGR_PRESC_MASK (0xf << I2C_TIMINGR_PRESC_SHIFT)
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# define I2C_TIMINGR_PRESC(n) (((n)-1) << I2C_TIMINGR_PRESC_SHIFT) /* tPRESC = n x tI2CCLK */
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#define I2C_TIMINGR_PRESC_SHIFT (28) /* Bits 28-31: Timing prescaler */
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#define I2C_TIMINGR_PRESC_MASK (0xf << I2C_TIMINGR_PRESC_SHIFT)
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# define I2C_TIMINGR_PRESC(n) (((n)-1) << I2C_TIMINGR_PRESC_SHIFT) /* tPRESC = n x tI2CCLK */
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/* Timeout register */
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#define I2C_TIMEOUTR_A_SHIFT (0) /* Bits 0-11: Bus Timeout A */
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#define I2C_TIMEOUTR_A_MASK (0x0fff << I2C_TIMEOUTR_A_SHIFT)
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# define I2C_TIMEOUTR_A(n) ((n) << I2C_TIMEOUTR_A_SHIFT)
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#define I2C_TIMEOUTR_TIDLE (1 << 12) /* Bit 12: Idle clock timeout detection */
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#define I2C_TIMEOUTR_TIMOUTEN (1 << 15) /* Bit 15: Clock timeout enable */
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#define I2C_TIMEOUTR_B_SHIFT (16) /* Bits 16-27: Bus Timeout B */
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#define I2C_TIMEOUTR_B_MASK (0x0fff << I2C_TIMEOUTR_B_SHIFT)
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# define I2C_TIMEOUTR_B(n) ((n) << I2C_TIMEOUTR_B_SHIFT)
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#define I2C_TIMEOUTR_TEXTEN (1 << 31) /* Bits 31: Extended clock timeout enable */
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#define I2C_TIMEOUTR_A_SHIFT (0) /* Bits 0-11: Bus Timeout A */
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#define I2C_TIMEOUTR_A_MASK (0x0fff << I2C_TIMEOUTR_A_SHIFT)
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# define I2C_TIMEOUTR_A(n) ((n) << I2C_TIMEOUTR_A_SHIFT)
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#define I2C_TIMEOUTR_TIDLE (1 << 12) /* Bit 12: Idle clock timeout detection */
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#define I2C_TIMEOUTR_TIMOUTEN (1 << 15) /* Bit 15: Clock timeout enable */
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#define I2C_TIMEOUTR_B_SHIFT (16) /* Bits 16-27: Bus Timeout B */
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#define I2C_TIMEOUTR_B_MASK (0x0fff << I2C_TIMEOUTR_B_SHIFT)
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# define I2C_TIMEOUTR_B(n) ((n) << I2C_TIMEOUTR_B_SHIFT)
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#define I2C_TIMEOUTR_TEXTEN (1 << 31) /* Bits 31: Extended clock timeout enable */
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/* Fields unique to the Interrupt and Status register */
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#define I2C_ISR_TXE (1 << 0) /* Bit 0: Transmit data register empty (transmitters) */
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#define I2C_ISR_TXIS (1 << 1) /* Bit 1: Transmit interrupt status (transmitters) */
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#define I2C_ISR_RXNE (1 << 2) /* Bit 2: Receive data register not empty (receivers) */
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#define I2C_ISR_TC (1 << 6) /* Bit 6: Transfer Complete (master) */
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#define I2C_ISR_TCR (1 << 7) /* Bit 7: Transfer Complete Reload */
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#define I2C_ISR_BUSY (1 << 15) /* Bit 15: Bus busy */
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#define I2C_ISR_DIR (1 << 16) /* Bit 16: Transfer direction (slave) */
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#define I2C_ISR_ADDCODE_SHIFT (17) /* Bits 17-23: Address match code (slave) */
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#define I2C_ISR_ADDCODE_MASK (0x7f << I2C_ISR_ADDCODE_SHIFT)
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#define I2C_ISR_TXE (1 << 0) /* Bit 0: Transmit data register empty (transmitters) */
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#define I2C_ISR_TXIS (1 << 1) /* Bit 1: Transmit interrupt status (transmitters) */
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#define I2C_ISR_RXNE (1 << 2) /* Bit 2: Receive data register not empty (receivers) */
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#define I2C_ISR_TC (1 << 6) /* Bit 6: Transfer Complete (master) */
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#define I2C_ISR_TCR (1 << 7) /* Bit 7: Transfer Complete Reload */
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#define I2C_ISR_BUSY (1 << 15) /* Bit 15: Bus busy */
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#define I2C_ISR_DIR (1 << 16) /* Bit 16: Transfer direction (slave) */
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#define I2C_ISR_ADDCODE_SHIFT (17) /* Bits 17-23: Address match code (slave) */
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#define I2C_ISR_ADDCODE_MASK (0x7f << I2C_ISR_ADDCODE_SHIFT)
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/* Interrupt and Status register and interrupt clear register */
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/* Common interrupt bits */
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#define I2C_INT_ADDR (1 << 3) /* Bit 3: Address matched (slave) */
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#define I2C_INT_NACK (1 << 4) /* Bit 4: Not Acknowledge received flag */
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#define I2C_INT_STOP (1 << 5) /* Bit 5: Stop detection flag */
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#define I2C_INT_BERR (1 << 8) /* Bit 8: Bus error */
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#define I2C_INT_ARLO (1 << 9) /* Bit 9: Arbitration lost */
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#define I2C_INT_OVR (1 << 10) /* Bit 10: Overrun/Underrun (slave) */
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#define I2C_INT_PECERR (1 << 11) /* Bit 11: PEC Error in reception */
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#define I2C_INT_TIMEOUT (1 << 12) /* Bit 12: Timeout or tLOW detection flag */
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#define I2C_INT_ALERT (1 << 13) /* Bit 13: SMBus alert */
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#define I2C_INT_ADDR (1 << 3) /* Bit 3: Address matched (slave) */
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#define I2C_INT_NACK (1 << 4) /* Bit 4: Not Acknowledge received flag */
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#define I2C_INT_STOP (1 << 5) /* Bit 5: Stop detection flag */
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#define I2C_INT_BERR (1 << 8) /* Bit 8: Bus error */
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#define I2C_INT_ARLO (1 << 9) /* Bit 9: Arbitration lost */
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#define I2C_INT_OVR (1 << 10) /* Bit 10: Overrun/Underrun (slave) */
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#define I2C_INT_PECERR (1 << 11) /* Bit 11: PEC Error in reception */
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#define I2C_INT_TIMEOUT (1 << 12) /* Bit 12: Timeout or tLOW detection flag */
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#define I2C_INT_ALERT (1 << 13) /* Bit 13: SMBus alert */
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#define I2C_ISR_ERRORMASK (I2C_INT_BERR | I2C_INT_ARLO | I2C_INT_OVR | I2C_INT_PECERR | I2C_INT_TIMEOUT)
|
||||
|
||||
@ -250,15 +250,15 @@
|
||||
|
||||
/* Packet error checking register */
|
||||
|
||||
#define I2C_PECR_MASK (0xff)
|
||||
#define I2C_PECR_MASK (0xff)
|
||||
|
||||
/* Receive data register */
|
||||
|
||||
#define I2C_RXDR_MASK (0xff)
|
||||
#define I2C_RXDR_MASK (0xff)
|
||||
|
||||
/* Transmit data register */
|
||||
|
||||
#define I2C_TXDR_MASK (0xff)
|
||||
#define I2C_TXDR_MASK (0xff)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_I2C_H */
|
||||
|
||||
|
||||
@ -51,22 +51,22 @@
|
||||
/* Maximum allowed speed as per data sheet for all SPIs (both pclk1 and pclk2)*/
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
|
||||
# define STM32_SPI_CLK_MAX 50000000UL
|
||||
# define STM32_SPI_CLK_MAX 50000000UL
|
||||
#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||
# define STM32_SPI_CLK_MAX 54000000UL
|
||||
# define STM32_SPI_CLK_MAX 54000000UL
|
||||
#endif
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */
|
||||
#define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */
|
||||
#define STM32_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */
|
||||
#define STM32_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */
|
||||
#define STM32_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */
|
||||
#define STM32_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */
|
||||
#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */
|
||||
#define STM32_SPI_I2SCFGR_OFFSET 0x001c /* I2S configuration register */
|
||||
#define STM32_SPI_I2SPR_OFFSET 0x0020 /* I2S prescaler register */
|
||||
#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */
|
||||
#define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */
|
||||
#define STM32_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */
|
||||
#define STM32_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */
|
||||
#define STM32_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */
|
||||
#define STM32_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */
|
||||
#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */
|
||||
#define STM32_SPI_I2SCFGR_OFFSET 0x001c /* I2S configuration register */
|
||||
#define STM32_SPI_I2SPR_OFFSET 0x0020 /* I2S prescaler register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
@ -209,18 +209,18 @@
|
||||
#define SPI_SR_OVR (1 << 6) /* Bit 6: Overrun flag */
|
||||
#define SPI_SR_BSY (1 << 7) /* Bit 7: Busy flag */
|
||||
#define SPI_SR_FRE (1 << 8) /* Bit 8: Frame format error */
|
||||
#define SPI_SR_FRLVL_SHIFT (9) /* Bits 9-10: FIFO reception level */
|
||||
#define SPI_SR_FRLVL_MASK (0x3 << SPI_SR_FRLVL_SHIFT)
|
||||
# define SPI_SR_FRLVL_EMPTY (0 << SPI_SR_FRLVL_SHIFT) /* FIFO empty */
|
||||
# define SPI_SR_FRLVL_QUARTER (1 << SPI_SR_FRLVL_SHIFT) /* 1/4 FIFO */
|
||||
# define SPI_SR_FRLVL_HALF (2 << SPI_SR_FRLVL_SHIFT) /* 1/2 FIFO */
|
||||
# define SPI_SR_FRLVL_FULL (3 << SPI_SR_FRLVL_SHIFT) /* FIFO full */
|
||||
#define SPI_SR_FTLVL_SHIFT (11) /* Bits 11-12: FIFO transmission level */
|
||||
#define SPI_SR_FTLVL_MASK (0x3 << SPI_SR_FTLVL_SHIFT)
|
||||
# define SPI_SR_FTLVL_EMPTY (0 << SPI_SR_FTLVL_SHIFT) /* FIFO empty */
|
||||
# define SPI_SR_FTLVL_QUARTER (1 << SPI_SR_FTLVL_SHIFT) /* 1/4 FIFO */
|
||||
# define SPI_SR_FTLVL_HALF (2 << SPI_SR_FTLVL_SHIFT) /* 1/2 FIFO */
|
||||
# define SPI_SR_FTLVL_FULL (3 << SPI_SR_FTLVL_SHIFT) /* FIFO full */
|
||||
#define SPI_SR_FRLVL_SHIFT (9) /* Bits 9-10: FIFO reception level */
|
||||
#define SPI_SR_FRLVL_MASK (3 << SPI_SR_FRLVL_SHIFT)
|
||||
# define SPI_SR_FRLVL_EMPTY (0 << SPI_SR_FRLVL_SHIFT) /* FIFO empty */
|
||||
# define SPI_SR_FRLVL_QUARTER (1 << SPI_SR_FRLVL_SHIFT) /* 1/4 FIFO */
|
||||
# define SPI_SR_FRLVL_HALF (2 << SPI_SR_FRLVL_SHIFT) /* 1/2 FIFO */
|
||||
# define SPI_SR_FRLVL_FULL (3 << SPI_SR_FRLVL_SHIFT) /* FIFO full */
|
||||
#define SPI_SR_FTLVL_SHIFT (11) /* Bits 11-12: FIFO transmission level */
|
||||
#define SPI_SR_FTLVL_MASK (3 << SPI_SR_FTLVL_SHIFT)
|
||||
# define SPI_SR_FTLVL_EMPTY (0 << SPI_SR_FTLVL_SHIFT) /* FIFO empty */
|
||||
# define SPI_SR_FTLVL_QUARTER (1 << SPI_SR_FTLVL_SHIFT) /* 1/4 FIFO */
|
||||
# define SPI_SR_FTLVL_HALF (2 << SPI_SR_FTLVL_SHIFT) /* 1/2 FIFO */
|
||||
# define SPI_SR_FTLVL_FULL (3 << SPI_SR_FTLVL_SHIFT) /* FIFO full */
|
||||
|
||||
/* I2S configuration register */
|
||||
|
||||
@ -233,10 +233,10 @@
|
||||
#define SPI_I2SCFGR_CKPOL (1 << 3) /* Bit 3: Steady state clock polarity */
|
||||
#define SPI_I2SCFGR_I2SSTD_SHIFT (4) /* Bit 4-5: I2S standard selection */
|
||||
#define SPI_I2SCFGR_I2SSTD_MASK (3 << SPI_I2SCFGR_I2SSTD_SHIFT)
|
||||
# define SPI_I2SCFGR_I2SSTD_PHILLIPS (00 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 00: I2S Phillips standard. */
|
||||
# define SPI_I2SCFGR_I2SSTD_MSB (1 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 01: MSB justified standard (left justified) */
|
||||
# define SPI_I2SCFGR_I2SSTD_LSB (2 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 10: LSB justified standard (right justified) */
|
||||
# define SPI_I2SCFGR_I2SSTD_PCM (3 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 11: PCM standard */
|
||||
# define SPI_I2SCFGR_I2SSTD_PHILLIPS (0 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 00: I2S Phillips standard. */
|
||||
# define SPI_I2SCFGR_I2SSTD_MSB (1 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 01: MSB justified standard (left justified) */
|
||||
# define SPI_I2SCFGR_I2SSTD_LSB (2 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 10: LSB justified standard (right justified) */
|
||||
# define SPI_I2SCFGR_I2SSTD_PCM (3 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 11: PCM standard */
|
||||
#define SPI_I2SCFGR_PCMSYNC (1 << 7) /* Bit 7: PCM frame synchronization */
|
||||
#define SPI_I2SCFGR_I2SCFG_SHIFT (8) /* Bit 8-9: I2S configuration mode */
|
||||
#define SPI_I2SCFGR_I2SCFG_MASK (3 << SPI_I2SCFGR_I2SCFG_SHIFT)
|
||||
@ -250,9 +250,9 @@
|
||||
|
||||
/* I2S prescaler register */
|
||||
|
||||
#define SPI_I2SPR_I2SDIV_SHIFT (0) /* Bit 0-7: I2S Linear prescaler */
|
||||
#define SPI_I2SPR_I2SDIV_MASK (0xff << SPI_I2SPR_I2SDIV_SHIFT)
|
||||
#define SPI_I2SPR_ODD (1 << 8) /* Bit 8: Odd factor for the prescaler */
|
||||
#define SPI_I2SPR_MCKOE (1 << 9) /* Bit 9: Master clock output enable */
|
||||
#define SPI_I2SPR_I2SDIV_SHIFT (0) /* Bit 0-7: I2S Linear prescaler */
|
||||
#define SPI_I2SPR_I2SDIV_MASK (0xff << SPI_I2SPR_I2SDIV_SHIFT)
|
||||
#define SPI_I2SPR_ODD (1 << 8) /* Bit 8: Odd factor for the prescaler */
|
||||
#define SPI_I2SPR_MCKOE (1 << 9) /* Bit 9: Master clock output enable */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_SPI_H */
|
||||
|
||||
@ -1445,11 +1445,14 @@ static inline void stm32_i2c_sendstart(FAR struct stm32_i2c_priv_s *priv)
|
||||
* exceed the hardware maximum allowed.
|
||||
*/
|
||||
|
||||
if (priv->dcnt > 255) {
|
||||
if (priv->dcnt > 255)
|
||||
{
|
||||
stm32_i2c_set_bytes_to_transfer(priv, 255);
|
||||
} else {
|
||||
}
|
||||
else
|
||||
{
|
||||
stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt);
|
||||
}
|
||||
}
|
||||
|
||||
/* Set the (7 bit) address.
|
||||
* 10 bit addressing is not yet supported.
|
||||
@ -1475,7 +1478,7 @@ static inline void stm32_i2c_sendstart(FAR struct stm32_i2c_priv_s *priv)
|
||||
*/
|
||||
|
||||
i2cinfo("Sending START: dcnt=%i msgc=%i flags=0x%04x\n",
|
||||
priv->dcnt, priv->msgc, priv->flags);
|
||||
priv->dcnt, priv->msgc, priv->flags);
|
||||
|
||||
stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_START);
|
||||
}
|
||||
@ -2019,7 +2022,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
|
||||
* we receive a TC event next time which will allow us to
|
||||
* either RESTART and continue sending the contents of the
|
||||
* next message or send a STOP condition and exit the ISR.
|
||||
*/
|
||||
*/
|
||||
|
||||
i2cinfo("TCR: DISABLE RELOAD: NBYTES = dcnt = %i msgc = %i\n",
|
||||
priv->dcnt, priv->msgc);
|
||||
@ -2057,7 +2060,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
|
||||
* in one of the supported states when polled.
|
||||
*/
|
||||
|
||||
else
|
||||
else
|
||||
{
|
||||
#ifdef CONFIG_I2C_POLLED
|
||||
stm32_i2c_traceevent(priv, I2CEVENT_POLL_DEV_NOT_RDY, 0);
|
||||
@ -2107,7 +2110,8 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
|
||||
* vs data) to the upper layers once we exit the ISR.
|
||||
*
|
||||
* Note: We do this prior to clearing interrupts because the NACKF
|
||||
* flag will naturally be cleared by that process. */
|
||||
* flag will naturally be cleared by that process.
|
||||
*/
|
||||
|
||||
priv->status = status;
|
||||
|
||||
@ -2367,6 +2371,7 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s
|
||||
UNUSED(cr1);
|
||||
UNUSED(cr2);
|
||||
#endif
|
||||
|
||||
/* Status after a normal / good exit is usually 0x00000001, meaning the TXE
|
||||
* bit is set. That occurs as a result of the I2C_TXDR register being
|
||||
* empty, and it naturally will be after the last byte is transmitted.
|
||||
|
||||
@ -360,9 +360,9 @@
|
||||
#define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_1
|
||||
#define GPIO_SPI2_SCK GPIO_SPI2_SCK_3
|
||||
|
||||
#define GPIO_SPI3_MISO GPIO_SPI3_MISO_1
|
||||
#define GPIO_SPI3_MOSI GPIO_SPI3_MOSI_2
|
||||
#define GPIO_SPI3_SCK GPIO_SPI3_SCK_1
|
||||
#define GPIO_SPI3_MISO GPIO_SPI3_MISO_1
|
||||
#define GPIO_SPI3_MOSI GPIO_SPI3_MOSI_2
|
||||
#define GPIO_SPI3_SCK GPIO_SPI3_SCK_1
|
||||
|
||||
/* I2C
|
||||
*
|
||||
|
||||
@ -95,9 +95,8 @@
|
||||
|
||||
#define GPIO_BTN_USER (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | GPIO_PORTC | GPIO_PIN13)
|
||||
|
||||
/* SPI ***************************************************************************
|
||||
*
|
||||
*/
|
||||
/* SPI ***************************************************************************/
|
||||
|
||||
#define GPIO_SPI_CS (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \
|
||||
GPIO_OUTPUT_SET)
|
||||
|
||||
@ -197,7 +196,5 @@ int stm32_dma_alloc_init(void);
|
||||
int board_adc_initialize(void);
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __CONFIGS_NUCLEO_144_SRC_NUCLEO_144_H */
|
||||
|
||||
@ -251,12 +251,13 @@
|
||||
#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1
|
||||
#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1
|
||||
|
||||
#define GPIO_I2C1_SCL GPIO_I2C1_SCL_1
|
||||
#define GPIO_I2C1_SDA GPIO_I2C1_SDA_1
|
||||
#define GPIO_I2C1_SCL GPIO_I2C1_SCL_1
|
||||
#define GPIO_I2C1_SDA GPIO_I2C1_SDA_1
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
|
||||
@ -20,7 +20,7 @@ CONFIG_WINDOWS_CYGWIN=y
|
||||
#
|
||||
# Build Configuration
|
||||
#
|
||||
CONFIG_APPS_DIR="../apps"
|
||||
# CONFIG_APPS_DIR="../apps"
|
||||
CONFIG_BUILD_FLAT=y
|
||||
# CONFIG_BUILD_2PASS is not set
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user