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SAMA5 clock configuration should now agree with Atmel sample code; Added header file with macros to enable and disable peripheral clocking

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This commit is contained in:
Gregory Nutt 2013-07-22 17:00:02 -06:00
parent a9b0f304e6
commit e67d610347
5 changed files with 460 additions and 132 deletions
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2
ChangeLog
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@ -5154,4 +5154,6 @@
* arch/arm/src/sama5/sam_clockconfig.c: Add SAMA5 PLL configuration
logic (plus associated header files). Initiali checkin is for the
SAM3U which is very similar but needs to be verified (2013-7-22).
* arch/arm/src/sama5/sam_periphclks.h: Add macros to enable and
disable SAMA5 peripheral clocks (2013-7-22).

7
arch/arm/src/sama5/chip/sam_pmc.h
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@ -201,10 +201,7 @@
#define PMC_CKGR_MCFR_MAINF_SHIFT (0) /* Bits 0-15: Main Clock Frequency */
#define PMC_CKGR_MCFR_MAINF_MASK (0xffff << PMC_CKGR_MCFR_MAINF_SHIFT)
#define PMC_CKGR_MCFR_MAINFRDY (1 << 16) /* Bit 16: Main Clock Ready */
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define PMC_CKGR_MCFR_RCMEAS (1 << 20) /* Bit 20: RC Oscillator Frequency Measure (write-only) */
#endif
#define PMC_CKGR_MCFR_RCMEAS (1 << 20) /* Bit 20: RC Oscillator Frequency Measure (write-only) */
/* PMC Clock Generator PLLA Register */
@ -244,7 +241,7 @@
# define PMC_MCKR_MDIV_PCKDIV1 (0 << PMC_MCKR_MDIV_SHIFT) /* Prescaler Output Clock divided by 1 */
# define PMC_MCKR_MDIV_PCKDIV2 (1 << PMC_MCKR_MDIV_SHIFT) /* Prescaler Output Clock divided by 2 */
# define PMC_MCKR_MDIV_PCKDIV4 (2 << PMC_MCKR_MDIV_SHIFT) /* Prescaler Output Clock divided by 4 */
# define PMC_MCKR_MDIV_MASPCK1DIV3K (3 << PMC_MCKR_MDIV_SHIFT) /* Prescaler Output Clock divided by 3 */
# define PMC_MCKR_MDIV_PCKDIV3 (3 << PMC_MCKR_MDIV_SHIFT) /* Prescaler Output Clock divided by 3 */
#define PMC_MCKR_PLLADIV2 (1 << 12) /* Bit 12: PLLA Divider */
/* USB Clock Register PMC_USB */

356
arch/arm/src/sama5/sam_clockconfig.c
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@ -57,18 +57,6 @@
* Pre-processor Definitions
****************************************************************************/
/* PMC register settings based on the board configuration values defined
* in board.h
*/
#define BOARD_CKGR_MOR (PMC_CKGR_MOR_KEY | BOARD_CKGR_MOR_MOSCXTST | \
PMC_CKGR_MOR_MOSCRCEN | PMC_CKGR_MOR_MOSCXTEN)
#define BOARD_CKGR_PLLAR (PMC_CKGR_PLLAR_ONE | BOARD_CKGR_PLLAR_MUL | \
BOARD_CKGR_PLLAR_COUNT | BOARD_CKGR_PLLAR_DIV)
#define BOARD_PMC_MCKR_FAST (BOARD_PMC_MCKR_PRES | PMC_MCKR_CSS_MAIN)
#define BOARD_PMC_MCKR (BOARD_PMC_MCKR_PRES | BOARD_PMC_MCKR_CSS)
#define BOARD_CKGR_UCKR (BOARD_CKGR_UCKR_UPLLCOUNT | PMC_CKGR_UCKR_UPLLEN)
/****************************************************************************
* Public Data
****************************************************************************/
@ -104,152 +92,262 @@ static inline void sam_wdtsetup(void)
static void sam_pmcwait(uint32_t bit)
{
volatile uint32_t delay;
/* There is no timeout on this wait. Why not? Because the symptoms there
* is no fallback if the wait times out and if the wait does time out, it
* can be very difficult to determine what happened. Much better to just
* hang here.
*/
for (delay = 0;
(getreg32(SAM_PMC_SR) & bit) == 0 && delay < UINT32_MAX;
delay++);
while ((getreg32(SAM_PMC_SR) & bit) == 0);
}
/****************************************************************************
* Name: sam_pmcsetup
* Name: sam_enablemosc
*
* Description:
* Initialize clocking
* Enable the main osciallator
*
****************************************************************************/
static inline void sam_pmcsetup(void)
static inline void sam_enablemosc(void)
{
uint32_t regval;
/* Enable main oscillator (if it has not already been selected) */
/* Switch from the internal 12MHz RC to the main external oscillator */
if ((getreg32(SAM_PMC_CKGR_MOR) & PMC_CKGR_MOR_MOSCSEL) == 0)
{
/* "When the MOSCXTEN bit and the MOSCXTCNT are written in CKGR_MOR to
* enable the main oscillator, the MOSCXTS bit in the Power Management
* Controller Status Register (PMC_SR) is cleared and the counter starts
* counting down on the slow clock divided by 8 from the MOSCXTCNT
* value. ... When the counter reaches 0, the MOSCXTS bit is set,
* indicating that the main clock is valid."
/* Enable main external oscillator */
regval = getreg32(SAM_PMC_CKGR_MOR);
regval |= PMC_CKGR_MOR_MOSCXTEN | PMC_CKGR_MOR_KEY;
putreg32(regval, SAM_PMC_CKGR_MOR);
/* Wait for the main clock to become ready */
while ((getreg32(SAM_PMC_CKGR_MCFR) & PMC_CKGR_MCFR_MAINFRDY) == 0);
/* Disable external OSC 12 MHz bypass */
regval = getreg32(SAM_PMC_CKGR_MOR);
regval &= ~PMC_CKGR_MOR_MOSCXTBY;
regval |= PMC_CKGR_MOR_KEY;
putreg32(regval, SAM_PMC_CKGR_MOR);
/* Switch main clock source to the external oscillator */
regval = getreg32(SAM_PMC_CKGR_MOR);
regval |= (PMC_CKGR_MOR_MOSCSEL | PMC_CKGR_MOR_KEY);
putreg32(regval, SAM_PMC_CKGR_MOR);
/* Wait for the main clock status change for the external oscillator
* selection.
*/
putreg32(BOARD_CKGR_MOR, SAM_PMC_CKGR_MOR);
sam_pmcwait(PMC_INT_MOSCXTS);
sam_pmcwait(PMC_INT_MOSCSELS);
/* And handle the case where MCK is running on main CLK */
sam_pmcwait(PMC_INT_MCKRDY);
}
}
/* "Switch to the main oscillator. The selection is made by writing the
* MOSCSEL bit in the Main Oscillator Register (CKGR_MOR). The switch of
* the Main Clock source is glitch free, so there is no need to run out
* of SLCK, PLLACK or UPLLCK in order to change the selection. The MOSCSELS
* bit of the power Management Controller Status Register (PMC_SR) allows
* knowing when the switch sequence is done."
*
* MOSCSELS: Main Oscillator Selection Status
* 0 = Selection is done
* 1 = Selection is in progress
*/
/****************************************************************************
* Name: sam_selectmosc
*
* Description:
* Select the main oscillator as the input clock for processor clock (PCK)
* and the main clock (MCK). The PCK and MCK differ only by the MDIV
* divisor that permits the MCK to run at a lower rate.
*
****************************************************************************/
putreg32((BOARD_CKGR_MOR | PMC_CKGR_MOR_MOSCSEL), SAM_PMC_CKGR_MOR);
sam_pmcwait(PMC_INT_MOSCSELS);
static inline void sam_selectmosc(void)
{
uint32_t regval;
/* "Select the master clock. "The Master Clock selection is made by writing
* the CSS field (Clock Source Selection) in PMC_MCKR (Master Clock Register).
* The prescaler supports the division by a power of 2 of the selected clock
* between 1 and 64, and the division by 3. The PRES field in PMC_MCKR programs
* the prescaler. Each time PMC_MCKR is written to define a new Master Clock,
* the MCKRDY bit is cleared in PMC_SR. It reads 0 until the Master Clock is
* established.
*/
/* Select the main oscillator as the input clock for PCK and MCK */
regval = getreg32(SAM_PMC_MCKR);
regval = getreg32(SAM_PMC_MCKR);
regval &= ~PMC_MCKR_CSS_MASK;
regval |= PMC_MCKR_CSS_MAIN;
putreg32(regval, SAM_PMC_MCKR);
sam_pmcwait(PMC_INT_MCKRDY);
/* Setup PLLA and wait for LOCKA */
/* Wait for main clock to be ready */
putreg32(BOARD_CKGR_PLLAR, SAM_PMC_CKGR_PLLAR);
sam_pmcwait(PMC_INT_LOCKA);
/* Setup UTMI for USB and wait for LOCKU */
#ifdef CONFIG_USBDEV
regval = getreg32(SAM_PMC_CKGR_UCKR);
regval |= BOARD_CKGR_UCKR;
putreg32(regval, SAM_PMC_CKGR_UCKR);
sam_pmcwait(PMC_INT_LOCKU);
#endif
/* Switch to the fast clock and wait for MCKRDY */
putreg32(BOARD_PMC_MCKR_FAST, SAM_PMC_MCKR);
sam_pmcwait(PMC_INT_MCKRDY);
putreg32(BOARD_PMC_MCKR, SAM_PMC_MCKR);
sam_pmcwait(PMC_INT_MCKRDY);
}
/****************************************************************************
* Name: sam_enabledefaultmaster and sam_disabledefaultmaster
* Name: sam_pllasetup
*
* Description:
* Enable/disable default master access
* Select the main oscillator as the input clock for processor clock (PCK)
* and the main clock (MCK). The PCK and MCK differ only by the MDIV
* divisor that permits the MCK to run at a lower rate.
*
****************************************************************************/
static inline void sam_enabledefaultmaster(void)
{
#warning Missing Logic
#if 0
uint32_t regval;
/* Set default master: SRAM0 -> Cortex-A5 System */
regval = getreg32(SAM_MATRIX_SCFG0);
regval |= (MATRIX_SCFG0_FIXEDDEFMSTR_ARMS|MATRIX_SCFG_DEFMSTRTYPE_FIXED);
putreg32(regval, SAM_MATRIX_SCFG0);
/* Set default master: SRAM1 -> Cortex-A5 System */
regval = getreg32(SAM_MATRIX_SCFG1);
regval |= (MATRIX_SCFG1_FIXEDDEFMSTR_ARMS|MATRIX_SCFG_DEFMSTRTYPE_FIXED);
putreg32(regval, SAM_MATRIX_SCFG1);
/* Set default master: Internal flash0 -> Cortex-A5 Instruction/Data */
regval = getreg32(SAM_MATRIX_SCFG3);
regval |= (MATRIX_SCFG3_FIXEDDEFMSTR_ARMC|MATRIX_SCFG_DEFMSTRTYPE_FIXED);
putreg32(regval, SAM_MATRIX_SCFG3);
#endif
}
#if 0 /* Not used */
static inline void sam_disabledefaultmaster(void)
static inline void sam_pllasetup(void)
{
uint32_t regval;
/* Clear default master: SRAM0 -> Cortex-A5 System */
/* Configure PLLA */
regval = getreg32(SAM_MATRIX_SCFG0);
regval &= ~MATRIX_SCFG_DEFMSTRTYPE_MASK;
putreg32(regval, SAM_MATRIX_SCFG0);
regval = (BOARD_CKGR_PLLAR_DIV | BOARD_CKGR_PLLAR_COUNT |
BOARD_CKGR_PLLAR_OUT | BOARD_CKGR_PLLAR_MUL |
PMC_CKGR_PLLAR_ONE);
putreg32(regval, SAM_PMC_CKGR_PLLAR);
/* Clear default master: SRAM1 -> Cortex-A5 System */
/* Set the PLL Charge Pump Current Register to zero */
regval = getreg32(SAM_MATRIX_SCFG1);
regval &= ~MATRIX_SCFG_DEFMSTRTYPE_MASK;
putreg32(regval, SAM_MATRIX_SCFG1);
putreg32(0, SAM_PMC_PLLICPR);
/* Clear default master: Internal flash0 -> Cortex-A5 Instruction/Data */
/* And wait for the PLL to lock on */
regval = getreg32(SAM_MATRIX_SCFG3);
regval &= ~MATRIX_SCFG_DEFMSTRTYPE_MASK;
putreg32(regval, SAM_MATRIX_SCFG3);
sam_pmcwait(PMC_INT_LOCKA);
}
/****************************************************************************
* Name: sam_plladivider
*
* Description:
* Configure MCK PLLA divider
*
****************************************************************************/
static inline void sam_plladivider(void)
{
uint32_t regval;
/* Is the PLLA divider currently set? */
regval = getreg32(SAM_PMC_MCKR);
if ((regval & PMC_MCKR_PLLADIV2) != 0)
{
#if BOARD_PMC_MCKR_PLLADIV == 0
/* The divider is set and we are configured to clear it */
regval &= ~PMC_MCKR_PLLADIV2;
#else
/* The divider is already set */
return;
#endif
}
else
{
#if BOARD_PMC_MCKR_PLLADIV == 0
/* The divider is already cleared */
return;
#else
/* The divider is clear and we are configured to set it */
regval |= PMC_MCKR_PLLADIV2;
#endif
}
/* We changed the PLLA divider. Wait for the main clock to be ready again */
sam_pmcwait(PMC_INT_MCKRDY);
}
/****************************************************************************
* Name: sam_mckprescaler
*
* Description:
* Configure main clock (MCK) Prescaler
*
****************************************************************************/
static inline void sam_mckprescaler(void)
{
uint32_t regval;
/* Set the main clock prescaler */
regval = getreg32(SAM_PMC_MCKR);
regval &= ~PMC_MCKR_PRES_MASK;
regval |= BOARD_PMC_MCKR_PRES;
putreg32(regval, SAM_PMC_MCKR);
/* Wait for the main clock to be ready again */
sam_pmcwait(PMC_INT_MCKRDY);
}
/****************************************************************************
* Name: sam_mckdivider
*
* Description:
* Configure main clock (MCK) divider (MDIV). This divider allows the MCK
* to run at a lower rate then PCK.
*
****************************************************************************/
static inline void sam_mckdivider(void)
{
uint32_t regval;
/* Set the main clock divider */
regval = getreg32(SAM_PMC_MCKR);
regval &= ~PMC_MCKR_MDIV_MASK;
regval |= BOARD_PMC_MCKR_MDIV;
putreg32(regval, SAM_PMC_MCKR);
/* Wait for the main clock to be ready again */
sam_pmcwait(PMC_INT_MCKRDY);
}
/****************************************************************************
* Name: sam_selectplla
*
* Description:
* Select the PLLA output as the input clock for PCK and MCK.
*
****************************************************************************/
static inline void sam_selectplla(void)
{
uint32_t regval;
/* Select the PLLA output as the main clock input */
regval = getreg32(SAM_PMC_MCKR);
regval &= ~PMC_MCKR_CSS_MASK;
regval |= PMC_MCKR_CSS_PLLA;
putreg32(regval, SAM_PMC_MCKR);
/* Wait for the main clock to be ready again */
sam_pmcwait(PMC_INT_MCKRDY);
}
/****************************************************************************
* Name: sam_upllsetup
*
* Description:
* Select the PLLA output as the input clock for PCK and MCK.
*
****************************************************************************/
static inline void sam_upllsetup(void)
{
#ifdef CONFIG_USBDEV
uint32_t regval;
/* Setup UTMI for USB and wait for LOCKU */
regval = getreg32(SAM_PMC_CKGR_UCKR);
regval |= (BOARD_CKGR_UCKR_UPLLCOUNT | PMC_CKGR_UCKR_UPLLEN);
putreg32(regval, SAM_PMC_CKGR_UCKR);
sam_pmcwait(PMC_INT_LOCKU);
#endif
}
/****************************************************************************
* Public Functions
@ -275,10 +373,38 @@ void sam_clockconfig(void)
sam_wdtsetup();
/* Initialize clocking */
/* Enable main oscillator (if it has not already been selected) */
sam_pmcsetup();
sam_enablemosc();
/* Optimize CPU setting for speed */
/* Select the main oscillator as the input clock for processor clock (PCK)
* and the main clock (MCK). The PCK and MCK differ only by the MDIV
* divisor that permits the MCK to run at a lower rate.
*/
sam_enabledefaultmaster();
sam_selectmosc();
/* Setup PLLA */
sam_pllasetup();
/* Configure the MCK PLLA divider. */
sam_plladivider();
/* Configure the MCK Prescaler */
sam_mckprescaler();
/* Configure MCK Divider */
sam_mckdivider();
/* Finally, elect the PLLA output as the input clock for PCK and MCK. */
sam_selectplla();
/* Setup UTMI for USB */
sam_upllsetup();
}

191
arch/arm/src/sama5/sam_periphclks.h Normal file
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@ -0,0 +1,191 @@
/************************************************************************************
* arch/arm/src/sama5/sam_periphclks.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMA5_SAMS_PERIPHCLKS_H
#define __ARCH_ARM_SRC_SAMA5_SAMS_PERIPHCLKS_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <arch/irq.h>
#include "chip/sam3u_pmc.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Helper macros */
#define sam_enableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCER0)
#define sam_enableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCER1)
#define sam_disableperiph0(s) putreg32((1 << (s)), SAM_PMC_PDER0)
#define sam_disableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PDER1)
#define sam_dbgu_enableclk() sam_enableperiph0(SAM_PID_DBGU)
#define sam_pit_enableclk() sam_enableperiph0(SAM_PID_PIT)
#define sam_wdt_enableclk() sam_enableperiph0(SAM_PID_WDT)
#define sam_hsmc_enableclk() sam_enableperiph0(SAM_PID_HSMC)
#define sam_pioa_enableclk() sam_enableperiph0(SAM_PID_PIOA)
#define sam_piob_enableclk() sam_enableperiph0(SAM_PID_PIOB)
#define sam_pioc_enableclk() sam_enableperiph0(SAM_PID_PIOC)
#define sam_piod_enableclk() sam_enableperiph0(SAM_PID_PIOD)
#define sam_pioe_enableclk() sam_enableperiph0(SAM_PID_PIOE)
#define sam_smd_enableclk() sam_enableperiph0(SAM_PID_SMD)
#define sam_usart0_enableclk() sam_enableperiph0(SAM_PID_USART0)
#define sam_usart1_enableclk() sam_enableperiph0(SAM_PID_USART1)
#define sam_usart2_enableclk() sam_enableperiph0(SAM_PID_USART2)
#define sam_usart3_enableclk() sam_enableperiph0(SAM_PID_USART3)
#define sam_uart0_enableclk() sam_enableperiph0(SAM_PID_UART0)
#define sam_uart1_enableclk() sam_enableperiph0(SAM_PID_UART1)
#define sam_twi0_enableclk() sam_enableperiph0(SAM_PID_TWI0)
#define sam_twi1_enableclk() sam_enableperiph0(SAM_PID_TWI1)
#define sam_twi2_enableclk() sam_enableperiph0(SAM_PID_TWI2)
#define sam_hsmci0_enableclk() sam_enableperiph0(SAM_PID_HSMCI0)
#define sam_hsmci1_enableclk() sam_enableperiph0(SAM_PID_HSMCI1)
#define sam_hsmci2_enableclk() sam_enableperiph0(SAM_PID_HSMCI2)
#define sam_spi0_enableclk() sam_enableperiph0(SAM_PID_SPI0)
#define sam_spi1_enableclk() sam_enableperiph0(SAM_PID_SPI1)
#define sam_tc0_enableclk() sam_enableperiph0(SAM_PID_TC0)
#define sam_tc1_enableclk() sam_enableperiph0(SAM_PID_TC1)
#define sam_pwm_enableclk() sam_enableperiph0(SAM_PID_PWM)
#define sam_adc_enableclk() sam_enableperiph0(SAM_PID_ADC)
#define sam_dmac0_enableclk() sam_enableperiph0(SAM_PID_DMAC0)
#define sam_dmac1_enableclk() sam_enableperiph0(SAM_PID_DMAC1)
#define sam_uhphs_enableclk() sam_enableperiph1(SAM_PID_UHPHS)
#define sam_udphs_enableclk() sam_enableperiph1(SAM_PID_UDPHS)
#define sam_gmac_enableclk() sam_enableperiph1(SAM_PID_GMAC)
#define sam_emac_enableclk() sam_enableperiph1(SAM_PID_EMAC)
#define sam_lcdc_enableclk() sam_enableperiph1(SAM_PID_LCDC)
#define sam_isi_enableclk() sam_enableperiph1(SAM_PID_ISI)
#define sam_ssc0_enableclk() sam_enableperiph1(SAM_PID_SSC0)
#define sam_ssc1_enableclk() sam_enableperiph1(SAM_PID_SSC1)
#define sam_can0_enableclk() sam_enableperiph1(SAM_PID_CAN0)
#define sam_can1_enableclk() sam_enableperiph1(SAM_PID_CAN1)
#define sam_sha_enableclk() sam_enableperiph1(SAM_PID_SHA)
#define sam_aes_enableclk() sam_enableperiph1(SAM_PID_AES)
#define sam_tdes_enableclk() sam_enableperiph1(SAM_PID_TDES)
#define sam_trng_enableclk() sam_enableperiph1(SAM_PID_TRNG)
#define sam_arm_enableclk() sam_enableperiph1(SAM_PID_ARM)
#define sam_aic_enableclk() sam_enableperiph1(SAM_PID_AIC)
#define sam_fuse_enableclk() sam_enableperiph1(SAM_PID_FUSE)
#define sam_mpddrc_enableclk() sam_enableperiph1(SAM_PID_MPDDRC)
#define sam_dbgu_disableclk() sam_disableperiph0(SAM_PID_DBGU)
#define sam_pit_disableclk() sam_disableperiph0(SAM_PID_PIT)
#define sam_wdt_disableclk() sam_disableperiph0(SAM_PID_WDT)
#define sam_hsmc_disableclk() sam_disableperiph0(SAM_PID_HSMC)
#define sam_pioa_disableclk() sam_disableperiph0(SAM_PID_PIOA)
#define sam_piob_disableclk() sam_disableperiph0(SAM_PID_PIOB)
#define sam_pioc_disableclk() sam_disableperiph0(SAM_PID_PIOC)
#define sam_piod_disableclk() sam_disableperiph0(SAM_PID_PIOD)
#define sam_pioe_disableclk() sam_disableperiph0(SAM_PID_PIOE)
#define sam_smd_disableclk() sam_disableperiph0(SAM_PID_SMD)
#define sam_usart0_disableclk() sam_disableperiph0(SAM_PID_USART0)
#define sam_usart1_disableclk() sam_disableperiph0(SAM_PID_USART1)
#define sam_usart2_disableclk() sam_disableperiph0(SAM_PID_USART2)
#define sam_usart3_disableclk() sam_disableperiph0(SAM_PID_USART3)
#define sam_uart0_disableclk() sam_disableperiph0(SAM_PID_UART0)
#define sam_uart1_disableclk() sam_disableperiph0(SAM_PID_UART1)
#define sam_twi0_disableclk() sam_disableperiph0(SAM_PID_TWI0)
#define sam_twi1_disableclk() sam_disableperiph0(SAM_PID_TWI1)
#define sam_twi2_disableclk() sam_disableperiph0(SAM_PID_TWI2)
#define sam_hsmci0_disableclk() sam_disableperiph0(SAM_PID_HSMCI0)
#define sam_hsmci1_disableclk() sam_disableperiph0(SAM_PID_HSMCI1)
#define sam_hsmci2_disableclk() sam_disableperiph0(SAM_PID_HSMCI2)
#define sam_spi0_disableclk() sam_disableperiph0(SAM_PID_SPI0)
#define sam_spi1_disableclk() sam_disableperiph0(SAM_PID_SPI1)
#define sam_tc0_disableclk() sam_disableperiph0(SAM_PID_TC0)
#define sam_tc1_disableclk() sam_disableperiph0(SAM_PID_TC1)
#define sam_pwm_disableclk() sam_disableperiph0(SAM_PID_PWM)
#define sam_adc_disableclk() sam_disableperiph0(SAM_PID_ADC)
#define sam_dmac0_disableclk() sam_disableperiph0(SAM_PID_DMAC0)
#define sam_dmac1_disableclk() sam_disableperiph0(SAM_PID_DMAC1)
#define sam_uhphs_disableclk() sam_disableperiph1(SAM_PID_UHPHS)
#define sam_udphs_disableclk() sam_disableperiph1(SAM_PID_UDPHS)
#define sam_gmac_disableclk() sam_disableperiph1(SAM_PID_GMAC)
#define sam_emac_disableclk() sam_disableperiph1(SAM_PID_EMAC)
#define sam_lcdc_disableclk() sam_disableperiph1(SAM_PID_LCDC)
#define sam_isi_disableclk() sam_disableperiph1(SAM_PID_ISI)
#define sam_ssc0_disableclk() sam_disableperiph1(SAM_PID_SSC0)
#define sam_ssc1_disableclk() sam_disableperiph1(SAM_PID_SSC1)
#define sam_can0_disableclk() sam_disableperiph1(SAM_PID_CAN0)
#define sam_can1_disableclk() sam_disableperiph1(SAM_PID_CAN1)
#define sam_sha_disableclk() sam_disableperiph1(SAM_PID_SHA)
#define sam_aes_disableclk() sam_disableperiph1(SAM_PID_AES)
#define sam_tdes_disableclk() sam_disableperiph1(SAM_PID_TDES)
#define sam_trng_disableclk() sam_disableperiph1(SAM_PID_TRNG)
#define sam_arm_disableclk() sam_disableperiph1(SAM_PID_ARM)
#define sam_aic_disableclk() sam_disableperiph1(SAM_PID_AIC)
#define sam_fuse_disableclk() sam_disableperiph1(SAM_PID_FUSE)
#define sam_mpddrc_disableclk() sam_disableperiph1(SAM_PID_MPDDRC)
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Inline Functions
************************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
* Public Data
************************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_SAMA5_SAMS_PERIPHCLKS_H */

36
configs/sama5d3x-ek/include/board.h
View File

@ -51,9 +51,10 @@
* definitions will configure clocking
*
* MAINOSC: Frequency = 12MHz (crysta)
* PLLA: PLL Divider = 1, Multiplier = 16 to generate PLLACK = 192MHz
* Master Clock (MCK): Source = PLLACK, Prescalar = 1 to generate MCK = 96MHz
* CPU clock: 96MHz
* PLLA: PLL Divider = 1, Multiplier = 66 to generate PLLACK = 792MHz
* Master Clock (MCK): Source = PLLACK/2, Prescalar = 1, MDIV = to generate
* MCK = 132MHz
* CPU clock = 396MHz
*/
/* Main oscillator register settings.
@ -67,22 +68,33 @@
/* PLLA configuration.
*
* Divider = 1
* Multipler = 16
* Multipler = 66
*/
#define BOARD_CKGR_PLLAR_MUL (15 << PMC_CKGR_PLLAR_MUL_SHIFT)
#define BOARD_CKGR_PLLAR_STMODE PMC_CKGR_PLLAR_STMODE_FAST
#define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT)
#define BOARD_CKGR_PLLAR_OUT (0)
#define BOARD_CKGR_PLLAR_MUL (65 << PMC_CKGR_PLLAR_MUL_SHIFT)
#define BOARD_CKGR_PLLAR_DIV PMC_CKGR_PLLAR_DIV_BYPASS
/* PMC master clock register settings.
*
* Source = PLLA
* Divider = 2
* Master/Processor Clock Source Selection = PLLA
* Master/Processor Clock Prescaler = 1
* PLLA Divider = 2
* Master Clock Division (MDIV) = 3
*
* NOTE: Bit PLLADIV2 must always be set to 1 when MDIV is set to 3.
*
* Prescaler input = 792MHz / 2 = 396MHz
* Prescaler output = 792MHz / 1 = 396MHz
* Processor Clock (PCK) = 396MHz
* Master clock (MCK) = 396MHz / 3 = 132MHz
*/
#define BOARD_PMC_MCKR_CSS PMC_MCKR_CSS_PLLA
#define BOARD_PMC_MCKR_PRES PMC_MCKR_PRES_DIV2
#define BOARD_PMC_MCKR_PRES PMC_MCKR_PRES_DIV1
#define BOARD_PMC_MCKR_PLLADIV PMC_MCKR_PLLADIV2
#define BOARD_PMC_MCKR_MDIV PMC_MCKR_MDIV_PCKDIV3
/* USB UTMI PLL start-up time */
@ -91,9 +103,9 @@
/* Resulting frequencies */
#define BOARD_MAINOSC_FREQUENCY (12000000) /* MAINOSC: 12MHz crystal on-board */
#define BOARD_PLLA_FREQUENCY (192000000) /* PLLACK: 16 * 12Mhz / 1 */
#define BOARD_MCK_FREQUENCY (96000000) /* MCK: PLLACK / 2 */
#define BOARD_CPU_FREQUENCY (96000000) /* CPU: MCK */
#define BOARD_PLLA_FREQUENCY (792000000) /* PLLACK: 66 * 12Mhz / 1 */
#define BOARD_PCK_FREQUENCY (396000000) /* CPU: PLLACK / 2 / 1 */
#define BOARD_MCK_FREQUENCY (132000000) /* MCK: PLLACK / 2 / 1 / 3 */
/* HSMCI clocking
*