SAMA5D2 add Flexcom SPI
Flexcom working, DMA not looked at for SAMA5D2 Update sam_flexcom_spi.c Update sam_flexcom_spi.h Update sam_config.h Update hardware/sam_flexcom_spi.h pkarashchenko reviews SAMA5 serial and flexcom serial corrections
This commit is contained in:
TimJTi
Xiang Xiao
parent
8b5078fc36
commit
e6bfaa14ee
@ -80,6 +80,10 @@ ifeq ($(CONFIG_SAMA5_FLEXCOM_USART),y)
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CHIP_CSRCS += sam_flexcom_serial.c
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endif
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ifeq ($(CONFIG_SAMA5_FLEXCOM_SPI), y)
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CHIP_CSRCS += sam_flexcom_spi.c
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endif
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ifeq ($(CONFIG_SAMA5_SPI0),y)
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CHIP_CSRCS += sam_spi.c
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else
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@ -34,10 +34,263 @@
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* Pre-processor Definitions
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****************************************************************************/
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#define SAM_FLEXCOM_SPI_NCS 2 /* Two chip selects */
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/* Flexcom SPI Register Offsets *********************************************/
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/* SPI register offsets *****************************************************/
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#define SAM_FLEXCOM_SPI_CR_OFFSET 0x0400 /* Control Register */
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#define SAM_FLEXCOM_SPI_MR_OFFSET 0x0404 /* Mode Register */
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#define SAM_FLEXCOM_SPI_RDR_OFFSET 0x0408 /* Receive Data Register */
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#define SAM_FLEXCOM_SPI_TDR_OFFSET 0x040c /* Transmit Data Register */
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#define SAM_FLEXCOM_SPI_SR_OFFSET 0x0410 /* Status Register */
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#define SAM_FLEXCOM_SPI_IER_OFFSET 0x0414 /* Interrupt Enable Register */
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#define SAM_FLEXCOM_SPI_IDR_OFFSET 0x0418 /* Interrupt Disable Register */
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#define SAM_FLEXCOM_SPI_IMR_OFFSET 0x041c /* Interrupt Mask Register */
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/* 0x420-0x42c: Reserved */
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#define SAM_FLEXCOM_SPI_CSR0_OFFSET 0x0430 /* Chip Select Register 0 */
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#define SAM_FLEXCOM_SPI_CSR1_OFFSET 0x0434 /* Chip Select Register 1 */
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/* 0x438-0x43C: Reserved */
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#define SAM_FLEXCOM_SPI_FMR_OFFSET 0x0440 /* FIFO Mode register */
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#define SAM_FLEXCOM_SPI_FLR_OFFSET 0x0444 /* FIFO Level Register */
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#define SAM_FLEXCOM_SPI_CMPR_OFFSET 0x0448 /* Comparison register */
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/* 0x044C-0x04E0: Reserved */
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#define SAM_FLEXCOM_SPI_WPMR_OFFSET 0x04e4 /* Write Protection Mode Register */
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#define SAM_FLEXCOM_SPI_WPSR_OFFSET 0x04e8 /* Write Protection Status Register */
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/* 0x04ec-0x5FC: Reserved */
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/* Flexcom SPI Register Addresses *******************************************/
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#ifdef CONFIG_SAMA5_FLEXCOM0_SPI
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#define SAM_FLEXCOM_SPI0_CR (SAM_FLEXCOM0_VBASE+SAM_FLEXCOM_SPI_CR_OFFSET)
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#define SAM_FLEXCOM_SPI0_MR (SAM_FLEXCOM0_VBASE+SAM_FLEXCOM_SPI_MR_OFFSET)
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#define SAM_FLEXCOM_SPI0_RDR (SAM_FLEXCOM0_VBASE+SAM_FLEXCOM_SPI_RDR_OFFSET)
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#define SAM_FLEXCOM_SPI0_TDR (SAM_FLEXCOM0_VBASE+SAM_FLEXCOM_SPI_TDR_OFFSET)
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#define SAM_FLEXCOM_SPI0_SR (SAM_FLEXCOM0_VBASE+SAM_FLEXCOM_SPI_SR_OFFSET)
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#define SAM_FLEXCOM_SPI0_IER (SAM_FLEXCOM0_VBASE+SAM_FLEXCOM_SPI_IER_OFFSET)
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#define SAM_FLEXCOM_SPI0_IDR (SAM_FLEXCOM0_VBASE+SAM_FLEXCOM_SPI_IDR_OFFSET)
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#define SAM_FLEXCOM_SPI0_IMR (SAM_FLEXCOM0_VBASE+SAM_FLEXCOM_SPI_IMR_OFFSET)
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#define SAM_FLEXCOM_SPI0_CSR0 (SAM_FLEXCOM0_VBASE+SAM_FLEXCOM_SPI_CSR0_OFFSET)
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#define SAM_FLEXCOM_SPI0_CSR1 (SAM_FLEXCOM0_VBASE+SAM_FLEXCOM_SPI_CSR1_OFFSET)
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#define SAM_FLEXCOM_SPI0_FMR (SAM_FLEXCOM0_VBASE+SAM_FLEXCOM_SPI_FMR_OFFSET)
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#define SAM_FLEXCOM_SPI0_FLR (SAM_FLEXCOM0_VBASE+SAM_FLEXCOM_SPI_FLR_OFFSET)
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#define SAM_FLEXCOM_SPI0_CMPR (SAM_FLEXCOM0_VBASE+SAM_FLEXCOM_SPI_CMPR_OFFSET)
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#define SAM_FLEXCOM_SPI0_WPMR (SAM_FLEXCOM0_VBASE+SAM_FLEXCOM_SPI_WPMR_OFFSET)
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#define SAM_FLEXCOM_SPI0_WPSR (SAM_FLEXCOM0_VBASE+SAM_FLEXCOM_SPI_WPSR_OFFSET)
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#endif
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#ifdef CONFIG_SAMA5_FLEXCOM1_SPI
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#define SAM_FLEXCOM_SPI1_CR (SAM_FLEXCOM1_VBASE+SAM_FLEXCOM_SPI_CR_OFFSET)
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#define SAM_FLEXCOM_SPI1_MR (SAM_FLEXCOM1_VBASE+SAM_FLEXCOM_SPI_MR_OFFSET)
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#define SAM_FLEXCOM_SPI1_RDR (SAM_FLEXCOM1_VBASE+SAM_FLEXCOM_SPI_RDR_OFFSET)
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#define SAM_FLEXCOM_SPI1_TDR (SAM_FLEXCOM1_VBASE+SAM_FLEXCOM_SPI_TDR_OFFSET)
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#define SAM_FLEXCOM_SPI1_SR (SAM_FLEXCOM1_VBASE+SAM_FLEXCOM_SPI_SR_OFFSET)
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#define SAM_FLEXCOM_SPI1_IER (SAM_FLEXCOM1_VBASE+SAM_FLEXCOM_SPI_IER_OFFSET)
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#define SAM_FLEXCOM_SPI1_IDR (SAM_FLEXCOM1_VBASE+SAM_FLEXCOM_SPI_IDR_OFFSET)
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#define SAM_FLEXCOM_SPI1_IMR (SAM_FLEXCOM1_VBASE+SAM_FLEXCOM_SPI_IMR_OFFSET)
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#define SAM_FLEXCOM_SPI1_CSR0 (SAM_FLEXCOM1_VBASE+SAM_FLEXCOM_SPI_CSR0_OFFSET)
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#define SAM_FLEXCOM_SPI1_CSR1 (SAM_FLEXCOM1_VBASE+SAM_FLEXCOM_SPI_CSR1_OFFSET)
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#define SAM_FLEXCOM_SPI1_FMR (SAM_FLEXCOM1_VBASE+SAM_FLEXCOM_SPI_FMR_OFFSET)
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#define SAM_FLEXCOM_SPI1_FLR (SAM_FLEXCOM1_VBASE+SAM_FLEXCOM_SPI_FLR_OFFSET)
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#define SAM_FLEXCOM_SPI1_CMPR (SAM_FLEXCOM1_VBASE+SAM_FLEXCOM_SPI_CMPR_OFFSET)
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#define SAM_FLEXCOM_SPI1_WPMR (SAM_FLEXCOM1_VBASE+SAM_FLEXCOM_SPI_WPMR_OFFSET)
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#define SAM_FLEXCOM_SPI1_WPSR (SAM_FLEXCOM1_VBASE+SAM_FLEXCOM_SPI_WPSR_OFFSET)
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#endif
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#ifdef CONFIG_SAMA5_FLEXCOM2_SPI
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#define SAM_FLEXCOM_SPI2_CR (SAM_FLEXCOM2_VBASE+SAM_FLEXCOM_SPI_CR_OFFSET)
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#define SAM_FLEXCOM_SPI2_MR (SAM_FLEXCOM2_VBASE+SAM_FLEXCOM_SPI_MR_OFFSET)
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#define SAM_FLEXCOM_SPI2_RDR (SAM_FLEXCOM2_VBASE+SAM_FLEXCOM_SPI_RDR_OFFSET)
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#define SAM_FLEXCOM_SPI2_TDR (SAM_FLEXCOM2_VBASE+SAM_FLEXCOM_SPI_TDR_OFFSET)
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#define SAM_FLEXCOM_SPI2_SR (SAM_FLEXCOM2_VBASE+SAM_FLEXCOM_SPI_SR_OFFSET)
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#define SAM_FLEXCOM_SPI2_IER (SAM_FLEXCOM2_VBASE+SAM_FLEXCOM_SPI_IER_OFFSET)
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#define SAM_FLEXCOM_SPI2_IDR (SAM_FLEXCOM2_VBASE+SAM_FLEXCOM_SPI_IDR_OFFSET)
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#define SAM_FLEXCOM_SPI2_IMR (SAM_FLEXCOM2_VBASE+SAM_FLEXCOM_SPI_IMR_OFFSET)
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#define SAM_FLEXCOM_SPI2_CSR0 (SAM_FLEXCOM2_VBASE+SAM_FLEXCOM_SPI_CSR0_OFFSET)
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#define SAM_FLEXCOM_SPI2_CSR1 (SAM_FLEXCOM2_VBASE+SAM_FLEXCOM_SPI_CSR1_OFFSET)
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#define SAM_FLEXCOM_SPI2_FMR (SAM_FLEXCOM2_VBASE+SAM_FLEXCOM_SPI_FMR_OFFSET)
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#define SAM_FLEXCOM_SPI2_FLR (SAM_FLEXCOM2_VBASE+SAM_FLEXCOM_SPI_FLR_OFFSET)
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#define SAM_FLEXCOM_SPI2_CMPR (SAM_FLEXCOM2_VBASE+SAM_FLEXCOM_SPI_CMPR_OFFSET)
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#define SAM_FLEXCOM_SPI2_WPMR (SAM_FLEXCOM2_VBASE+SAM_FLEXCOM_SPI_WPMR_OFFSET)
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#define SAM_FLEXCOM_SPI2_WPSR (SAM_FLEXCOM2_VBASE+SAM_FLEXCOM_SPI_WPSR_OFFSET)
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#endif
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#ifdef CONFIG_SAMA5_FLEXCOM3_SPI
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#define SAM_FLEXCOM_SPI3_CR (SAM_FLEXCOM3_VBASE+SAM_FLEXCOM_SPI_CR_OFFSET)
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#define SAM_FLEXCOM_SPI3_MR (SAM_FLEXCOM3_VBASE+SAM_FLEXCOM_SPI_MR_OFFSET)
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#define SAM_FLEXCOM_SPI3_RDR (SAM_FLEXCOM3_VBASE+SAM_FLEXCOM_SPI_RDR_OFFSET)
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#define SAM_FLEXCOM_SPI3_TDR (SAM_FLEXCOM3_VBASE+SAM_FLEXCOM_SPI_TDR_OFFSET)
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#define SAM_FLEXCOM_SPI3_SR (SAM_FLEXCOM3_VBASE+SAM_FLEXCOM_SPI_SR_OFFSET)
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#define SAM_FLEXCOM_SPI3_IER (SAM_FLEXCOM3_VBASE+SAM_FLEXCOM_SPI_IER_OFFSET)
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#define SAM_FLEXCOM_SPI3_IDR (SAM_FLEXCOM3_VBASE+SAM_FLEXCOM_SPI_IDR_OFFSET)
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#define SAM_FLEXCOM_SPI3_IMR (SAM_FLEXCOM3_VBASE+SAM_FLEXCOM_SPI_IMR_OFFSET)
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#define SAM_FLEXCOM_SPI3_CSR0 (SAM_FLEXCOM3_VBASE+SAM_FLEXCOM_SPI_CSR0_OFFSET)
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#define SAM_FLEXCOM_SPI3_CSR1 (SAM_FLEXCOM3_VBASE+SAM_FLEXCOM_SPI_CSR1_OFFSET)
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#define SAM_FLEXCOM_SPI3_FMR (SAM_FLEXCOM3_VBASE+SAM_FLEXCOM_SPI_FMR_OFFSET)
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#define SAM_FLEXCOM_SPI3_FLR (SAM_FLEXCOM3_VBASE+SAM_FLEXCOM_SPI_FLR_OFFSET)
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#define SAM_FLEXCOM_SPI3_CMPR (SAM_FLEXCOM3_VBASE+SAM_FLEXCOM_SPI_CMPR_OFFSET)
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#define SAM_FLEXCOM_SPI3_WPMR (SAM_FLEXCOM3_VBASE+SAM_FLEXCOM_SPI_WPMR_OFFSET)
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#define SAM_FLEXCOM_SPI3_WPSR (SAM_FLEXCOM3_VBASE+SAM_FLEXCOM_SPI_WPSR_OFFSET)
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#endif
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#ifdef CONFIG_SAMA5_FLEXCOM4_SPI
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#define SAM_FLEXCOM_SPI4_CR (SAM_FLEXCOM4_VBASE+SAM_FLEXCOM_SPI_CR_OFFSET)
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#define SAM_FLEXCOM_SPI4_MR (SAM_FLEXCOM4_VBASE+SAM_FLEXCOM_SPI_MR_OFFSET)
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#define SAM_FLEXCOM_SPI4_RDR (SAM_FLEXCOM4_VBASE+SAM_FLEXCOM_SPI_RDR_OFFSET)
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#define SAM_FLEXCOM_SPI4_TDR (SAM_FLEXCOM4_VBASE+SAM_FLEXCOM_SPI_TDR_OFFSET)
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#define SAM_FLEXCOM_SPI4_SR (SAM_FLEXCOM4_VBASE+SAM_FLEXCOM_SPI_SR_OFFSET)
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#define SAM_FLEXCOM_SPI4_IER (SAM_FLEXCOM4_VBASE+SAM_FLEXCOM_SPI_IER_OFFSET)
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#define SAM_FLEXCOM_SPI4_IDR (SAM_FLEXCOM4_VBASE+SAM_FLEXCOM_SPI_IDR_OFFSET)
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#define SAM_FLEXCOM_SPI4_IMR (SAM_FLEXCOM4_VBASE+SAM_FLEXCOM_SPI_IMR_OFFSET)
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#define SAM_FLEXCOM_SPI4_CSR0 (SAM_FLEXCOM4_VBASE+SAM_FLEXCOM_SPI_CSR0_OFFSET)
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#define SAM_FLEXCOM_SPI4_CSR1 (SAM_FLEXCOM4_VBASE+SAM_FLEXCOM_SPI_CSR1_OFFSET)
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#define SAM_FLEXCOM_SPI4_FMR (SAM_FLEXCOM4_VBASE+SAM_FLEXCOM_SPI_FMR_OFFSET)
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#define SAM_FLEXCOM_SPI4_FLR (SAM_FLEXCOM4_VBASE+SAM_FLEXCOM_SPI_FLR_OFFSET)
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#define SAM_FLEXCOM_SPI4_CMPR (SAM_FLEXCOM4_VBASE+SAM_FLEXCOM_SPI_CMPR_OFFSET)
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#define SAM_FLEXCOM_SPI4_WPMR (SAM_FLEXCOM4_VBASE+SAM_FLEXCOM_SPI_WPMR_OFFSET)
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#define SAM_FLEXCOM_SPI4_WPSR (SAM_FLEXCOM4_VBASE+SAM_FLEXCOM_SPI_WPSR_OFFSET)
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#endif
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/* Flexcom SPI Register Bit Field Definitions *******************************/
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/* SPI Control Register */
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#define FLEXCOM_SPI_CR_SPIEN (1 << 0) /* Bit 0: SPI Enable */
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#define FLEXCOM_SPI_CR_SPIDIS (1 << 1) /* Bit 1: SPI Disable */
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#define FLEXCOM_SPI_CR_SWRST (1 << 7) /* Bit 7: SPI Software Reset */
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#define FLEXCOM_SPI_CR_REQCLR (1 << 12) /* Bit 12: SPI Request to Clear Comparison Trigger */
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#define FLEXCOM_SPI_CR_TXFCLR (1 << 16) /* Bit 16: SPI Transmit FIFO clear */
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#define FLEXCOM_SPI_CR_RXFCLR (1 << 17) /* Bit 17: SPI Receive FIFO clear */
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#define FLEXCOM_SPI_CR_LASTXFER (1 << 24) /* Bit 24: Last Transfer */
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#define FLEXCOM_SPI_CR_FIFOEN (1 << 30) /* Bit 30: Enable TX and RX FIFOs */
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#define FLEXCOM_SPI_CR_FIFODIS (1 << 31) /* Bit 31: Disable TX and RX FIFOs */
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/* SPI Mode Register */
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#define FLEXCOM_SPI_MR_MSTR (1 << 0) /* Bit 0: Master/Slave Mode */
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#define FLEXCOM_SPI_MR_PS (1 << 1) /* Bit 1: Peripheral Select */
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#define FLEXCOM_SPI_MR_PCSDEC (1 << 2) /* Bit 2: Chip Select Decode */
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#define FLEXCOM_SPI_MR_BSCRCCLK (1 << 3) /* Bit 3: Bit Rate Source Clock */
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#define FLEXCOM_SPI_MR_MODFDIS (1 << 4) /* Bit 4: Mode Fault Detection */
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#define FLEXCOM_SPI_MR_WDRBT (1 << 5) /* Bit 5: Wait Data Read Before Transfer */
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#define FLEXCOM_SPI_MR_LLB (1 << 7) /* Bit 7: Local Loopback Enable */
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#define FLEXCOM_SPI_MR_CMPMODE (1 << 12) /* Bit 12: Comparison Mode */
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#define FLEXCOM_SPI_MR_PCS_SHIFT (16) /* Bits 16-17: Peripheral Chip Select */
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#define FLEXCOM_SPI_MR_PCS_MASK (3 << FLEXCOM_SPI_MR_PCS_SHIFT)
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/* Only 2 chip selects */
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#define FLEXCOM_SPI_MR_PCS0 (0 << FLEXCOM_SPI_MR_PCS_SHIFT)
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/* NPCS[1:0] = 10 */
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#define FLEXCOM_SPI_MR_PCS1 (1 << FLEXCOM_SPI_MR_PCS_SHIFT)
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/* NPCS[1:0] = 01 */
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#define FLEXCOM_SPI_MR_DLYBCS_SHIFT (24) /* Bits 24-31: Delay Between Chip Selects */
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#define FLEXCOM_SPI_MR_DLYBCS_MASK (0xff << FLEXCOM_SPI_MR_DLYBCS_SHIFT)
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/* SPI Receive Data Register */
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#define FLEXCOM_SPI_RDR_RD_SHIFT (0) /* Bits 0-15: Receive Data */
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#define FLEXCOM_SPI_RDR_RD_MASK (0xffff << FLEXCOM_SPI_RDR_RD_SHIFT)
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#define FLEXCOM_SPI_RDR_PCS_SHIFT (16) /* Bits 16-19: Peripheral Chip Select */
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#define FLEXCOM_SPI_RDR_PCS_MASK (3 << FLEXCOM_SPI_RDR_PCS_SHIFT)
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# define FLEXCOM_SPI_RDR_PCS0 (0 << FLEXCOM_SPI_RDR_PCS_SHIFT) /* NPCS[1:0] = 10 */
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# define FLEXCOM_SPI_RDR_PCS1 (1 << FLEXCOM_SPI_RDR_PCS_SHIFT) /* NPCS[1:0] = 01 */
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/* SPI Transmit Data Register */
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#define FLEXCOM_SPI_TDR_TD_SHIFT (0) /* Bits 0-15: Transmit Data */
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#define FLEXCOM_SPI_TDR_TD_MASK (0xffff << FLEXCOM_SPI_TDR_TD_SHIFT)
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#define FLEXCOM_SPI_TDR_PCS_SHIFT (16) /* Bits 16-19: Peripheral Chip Select */
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#define FLEXCOM_SPI_TDR_PCS_MASK (3 << FLEXCOM_SPI_TDR_PCS_SHIFT)
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#define FLEXCOM_SPI_TDR_PCS0 (0 << FLEXCOM_SPI_TDR_PCS_SHIFT) /* NPCS[1:0] = 1110 (w/PCSDEC=1) */
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#define FLEXCOM_SPI_TDR_PCS1 (1 << FLEXCOM_SPI_TDR_PCS_SHIFT) /* NPCS[1:0] = 1101 (w/PCSDEC=1) */
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#define FLEXCOM_SPI_TDR_LASTXFER (1 << 24) /* Bit 24: Last Transfer */
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/* SPI Status Register, SPI Interrupt Enable Register, SPI Interrupt
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* Disable Register, and SPI Interrupt Mask Register (common bit fields)
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*/
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#define FLEXCOM_SPI_INT_RDRF (1 << 0) /* Bit 0: Receive Data Register Full Interrupt */
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#define FLEXCOM_SPI_INT_TDRE (1 << 1) /* Bit 1: Transmit Data Register Empty Interrupt */
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#define FLEXCOM_SPI_INT_MODF (1 << 2) /* Bit 2: Mode Fault Error Interrupt */
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#define FLEXCOM_SPI_INT_OVRES (1 << 3) /* Bit 3: Overrun Error Interrupt */
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#define FLEXCOM_SPI_INT_NSSR (1 << 8) /* Bit 8: NSS Rising Interrupt */
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#define FLEXCOM_SPI_INT_TXEMPTY (1 << 9) /* Bit 9: Transmission Registers Empty Interrupt */
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#define FLEXCOM_SPI_INT_UNDES (1 << 10) /* Bit 10: Underrun Error Status Interrupt (slave) */
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#define FLEXCOM_SPI_INT_CMP (1 << 11) /* Bit 11: Comparison Status */
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#define FLEXCOM_SPI_SR_SPIENS (1 << 16) /* Bit 16: SPI Enable Status (SR only) */
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#define FLEXCOM_SPI_INT_TXFEF (1 << 24) /* Bit 24: TX FIFO empty flag */
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#define FLEXCOM_SPI_INT_TXFFF (1 << 25) /* Bit 25: TX FIFO full flag */
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#define FLEXCOM_SPI_INT_TXFTHF (1 << 26) /* Bit 25: TX FIFO FIFO Threshold flag */
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#define FLEXCOM_SPI_INT_RXFEF (1 << 27) /* Bit 27: RX FIFO empty flag */
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#define FLEXCOM_SPI_INT_RXFFF (1 << 28) /* Bit 28: RX FIFO full flag */
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#define FLEXCOM_SPI_INT_RXFTHF (1 << 29) /* Bit 29: RX FIFO FIFO Threshold flag */
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#define FLEXCOM_SPI_INT_TXFPTEF (1 << 30) /* Bit 30: TX FIFO pointer error flag */
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#define FLEXCOM_SPI_INT_RXFPTEF (1 << 31) /* Bit 31: RX FIFO pointer error flag */
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/* SPI Chip Select Registers 0-3 */
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#define FLEXCOM_SPI_CSR_CPOL (1 << 0) /* Bit 0: Clock Polarity */
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#define FLEXCOM_SPI_CSR_NCPHA (1 << 1) /* Bit 1: Clock Phase */
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#define FLEXCOM_SPI_CSR_CSNAAT (1 << 2) /* Bit 2: Chip Select Not Active After Transfer */
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#define FLEXCOM_SPI_CSR_CSAAT (1 << 3) /* Bit 3: Chip Select Active After Transfer */
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#define FLEXCOM_SPI_CSR_BITS_SHIFT (4) /* Bits 4-7: Bits Per Transfer */
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#define FLEXCOM_SPI_CSR_BITS_MASK (15 << FLEXCOM_SPI_CSR_BITS_SHIFT)
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# define FLEXCOM_SPI_CSR_BITS(n) (((n)-8) << FLEXCOM_SPI_CSR_BITS_SHIFT) /* n, n=8-16 */
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# define FLEXCOM_SPI_CSR_BITS8 (0 << FLEXCOM_SPI_CSR_BITS_SHIFT) /* 8 */
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# define FLEXCOM_SPI_CSR_BITS9 (1 << FLEXCOM_SPI_CSR_BITS_SHIFT) /* 9 */
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# define FLEXCOM_SPI_CSR_BITS10 (2 << FLEXCOM_SPI_CSR_BITS_SHIFT) /* 10 */
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# define FLEXCOM_SPI_CSR_BITS11 (3 << FLEXCOM_SPI_CSR_BITS_SHIFT) /* 11 */
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# define FLEXCOM_SPI_CSR_BITS12 (4 << FLEXCOM_SPI_CSR_BITS_SHIFT) /* 12 */
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# define FLEXCOM_SPI_CSR_BITS13 (5 << FLEXCOM_SPI_CSR_BITS_SHIFT) /* 13 */
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# define FLEXCOM_SPI_CSR_BITS14 (6 << FLEXCOM_SPI_CSR_BITS_SHIFT) /* 14 */
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# define FLEXCOM_SPI_CSR_BITS15 (7 << FLEXCOM_SPI_CSR_BITS_SHIFT) /* 15 */
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# define FLEXCOM_SPI_CSR_BITS16 (8 << FLEXCOM_SPI_CSR_BITS_SHIFT) /* 16 */
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#define FLEXCOM_SPI_CSR_SCBR_SHIFT (8) /* Bits 8-15: Serial Clock Baud Rate */
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#define FLEXCOM_SPI_CSR_SCBR_MASK (0xff << FLEXCOM_SPI_CSR_SCBR_SHIFT)
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# define FLEXCOM_SPI_CSR_SCBR(n) ((uint32_t)(n) << FLEXCOM_SPI_CSR_SCBR_SHIFT)
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#define FLEXCOM_SPI_CSR_DLYBS_SHIFT (16) /* Bits 16-23: Delay Before SPCK */
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#define FLEXCOM_SPI_CSR_DLYBS_MASK (0xff << FLEXCOM_SPI_CSR_DLYBS_SHIFT)
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# define FLEXCOM_SPI_CSR_DLYBS(n) ((uint32_t)(n) << FLEXCOM_SPI_CSR_DLYBS_SHIFT)
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#define FLEXCOM_SPI_CSR_DLYBCT_SHIFT (24) /* Bits 24-31: Delay Between Consecutive Transfers */
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#define FLEXCOM_SPI_CSR_DLYBCT_MASK (0xff << FLEXCOM_SPI_CSR_DLYBCT_SHIFT)
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# define FLEXCOM_SPI_CSR_DLYBCT(n) ((uint32_t)(n) << FLEXCOM_SPI_CSR_DLYBCT_SHIFT)
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/* SPI FIFO Mode Register */
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#define FLEXCOM_SPI_FMR_TXRDYM_SHIFT (1 << 0) /* Bits 0-1: TX Data Register empty mode */
|
||||
#define FLEXCOM_SPI_FMR_TXRDYM_MASK (3 << FLEXCOM_SPI_FMR_TXRDYM_SHIFT)
|
||||
#define FLEXCOM_SPI_FMR_RXRDYM_SHIFT (1 << 4) /* Bits 0-1: RX Data Register full mode */
|
||||
#define FLEXCOM_SPI_FMR_RXRDYM_MASK (3 << FLEXCOM_SPI_FMR_RXRDYM_SHIFT)
|
||||
#define FLEXCOM_SPI_FMR_TXFTHRES_SHIFT (1 << 16) /* Bits 16-21: Transmit FIFO threshold */
|
||||
#define FLEXCOM_SPI_FMR_TXFTHRES_MASK (0x3f << FLEXCOM_SPI_FMR_TXFTHRES_SHIFT)
|
||||
#define FLEXCOM_SPI_FMR_RXFTHRES_SHIFT (1 << 24) /* Bits 24-29: Transmit FIFO threshold */
|
||||
#define FLEXCOM_SPI_FMR_RXFTHRES_MASK (0x3f << FLEXCOM_SPI_FMR_RXFTHRES_SHIFT)
|
||||
|
||||
/* SPI FIFO Level Register */
|
||||
#define FLEXCOM_SPI_FLR_TXFL_SHIFT (1 << 0) /* Bits 0-5: Transmit FIFO Level */
|
||||
#define FLEXCOM_SPI_FLR_TXFL_MASK (0x3f << FLEXCOM_SPI_FLR_TXFL_SHIFT)
|
||||
#define FLEXCOM_SPI_FLR_RXFL_SHIFT (16 << 0) /* Bits 16-21: Transmit FIFO Level */
|
||||
#define FLEXCOM_SPI_FLR_RXFL_MASK (0x3f << FLEXCOM_SPI_FLR_RXFL_SHIFT)
|
||||
|
||||
/* SPI Comparison Register */
|
||||
#define FLEXCOM_SPI_CMPR_VAL1_SHIFT (1 << 0) /* Bits 0-15: First Comparison Value for Received Character */
|
||||
#define FLEXCOM_SPI_CMPR_VAL1_MASK (0xffff << FLEXCOM_SPI_CMPR_VAL1_SHIFT)
|
||||
#define FLEXCOM_SPI_CMPR_VAL2_SHIFT (1 << 0) /* Bits 16-32: Second Comparison Value for Received Character */
|
||||
#define FLEXCOM_SPI_CMPR_VAL2_MASK (0xffff << FLEXCOM_SPI_CMPR_VAL2_SHIFT)
|
||||
|
||||
/* SPI Write Protection Control Register */
|
||||
|
||||
#define FLEXCOM_SPI_WPCR_WPEN (1 << 0) /* Bit 0: SPI Write Protection Enable */
|
||||
#define FLEXCOM_SPI_WPCR_WPKEY_SHIFT (8) /* Bits 8-31: SPI Write Protection Key Password */
|
||||
#define FLEXCOM_SPI_WPCR_WPKEY_MASK (0x00ffffff << FLEXCOM_SPI_WPCR_WPKEY_SHIFT)
|
||||
# define FLEXCOM_SPI_WPCR_WPKEY (0x00535049 << FLEXCOM_SPI_WPCR_WPKEY_SHIFT)
|
||||
|
||||
/* SPI Write Protection Status Register */
|
||||
|
||||
#define FLEXCOM_SPI_WPSR_WPVS (1 << 0) /* Bit 0: SPI Write Protection Violation Status */
|
||||
#define FLEXCOM_SPI_WPSR_WPVSRC_SHIFT (8) /* Bits 8-15: SPI Write Protection Violation Source */
|
||||
#define FLEXCOM_SPI_WPSR_WPVSRC_MASK (0xff << FLEXCOM_SPI_WPSR_WPVSRC_SHIFT)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_FLEXCOM_SPI_H */
|
||||
|
||||
@ -379,4 +379,12 @@
|
||||
# undef SAMA5_HAVE_FLEXCOM_CONSOLE
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SAMA5_FLEXCOM0_SPI) || \
|
||||
defined(CONFIG_SAMA5_FLEXCOM1_SPI) || \
|
||||
defined(CONFIG_SAMA5_FLEXCOM2_SPI) || \
|
||||
defined(CONFIG_SAMA5_FLEXCOM3_SPI) || \
|
||||
defined(CONFIG_SAMA5_FLEXCOM4_SPI)
|
||||
# define SAMA5_HAVE_FLEXCOM_SPI
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_SAMA5_SAM_CONFIG_H */
|
||||
|
||||
2127
arch/arm/src/sama5/sam_flexcom_spi.c
Normal file
2127
arch/arm/src/sama5/sam_flexcom_spi.c
Normal file
File diff suppressed because it is too large
Load Diff
277
arch/arm/src/sama5/sam_flexcom_spi.h
Executable file
277
arch/arm/src/sama5/sam_flexcom_spi.h
Executable file
@ -0,0 +1,277 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/sama5/sam_flexcom_spi.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_SAMA5_SAM_FLEXCOM_SPI_H
|
||||
#define __ARCH_ARM_SRC_SAMA5_SAM_FLEXCOM_SPI_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* The Flexcom SPI "port" number used as an input to sam_flexcom_spibus_
|
||||
* initialize encodes information about the Flexcom SPI controller (0 thru 4)
|
||||
* and the Flexcom SPI chip select (0 or 1)
|
||||
*/
|
||||
|
||||
#define __FLEXCOM_SPI_CS_SHIFT (0) /* Bit 0: Flexcom SPI chip select number */
|
||||
#define __FLEXCOM_SPI_CS_MASK (1 << __FLEXCOM_SPI_CS_SHIFT)
|
||||
# define __FLEXCOM_SPI_CS0 (0 << __FLEXCOM_SPI_CS_SHIFT)
|
||||
# define __FLEXCOM_SPI_CS1 (1 << __FLEXCOM_SPI_CS_SHIFT)
|
||||
#define __FLEXCOM_SPI_SPI_SHIFT (1) /* Bit 1-3: Flexcom number */
|
||||
#define __FLEXCOM_SPI_SPI_MASK (7 << __FLEXCOM_SPI_SPI_SHIFT)
|
||||
# define __FLEXCOM0_SPI (0 << __FLEXCOM_SPI_SPI_SHIFT) /* FLEXCOM0 SPI */
|
||||
# define __FLEXCOM1_SPI (1 << __FLEXCOM_SPI_SPI_SHIFT) /* FLEXCOM1 SPI */
|
||||
# define __FLEXCOM2_SPI (2 << __FLEXCOM_SPI_SPI_SHIFT) /* FLEXCOM2 SPI */
|
||||
# define __FLEXCOM3_SPI (3 << __FLEXCOM_SPI_SPI_SHIFT) /* FLEXCOM3 SPI */
|
||||
# define __FLEXCOM4_SPI (4 << __FLEXCOM_SPI_SPI_SHIFT) /* FLEXCOM4 SPI */
|
||||
|
||||
#define FLEXCOM0_SPI_CS0 (__FLEXCOM0_SPI | __FLEXCOM_SPI_CS0)
|
||||
#define FLEXCOM0_SPI_CS1 (__FLEXCOM0_SPI | __FLEXCOM_SPI_CS1)
|
||||
|
||||
#define FLEXCOM1_SPI_CS0 (__FLEXCOM1_SPI | __FLEXCOM_SPI_CS0)
|
||||
#define FLEXCOM1_SPI_CS1 (__FLEXCOM1_SPI | __FLEXCOM_SPI_CS1)
|
||||
|
||||
#define FLEXCOM2_SPI_CS0 (__FLEXCOM2_SPI | __FLEXCOM_SPI_CS0)
|
||||
#define FLEXCOM2_SPI_CS1 (__FLEXCOM3_SPI | __FLEXCOM_SPI_CS1)
|
||||
|
||||
#define FLEXCOM3_SPI_CS0 (__FLEXCOM3_SPI | __FLEXCOM_SPI_CS0)
|
||||
#define FLEXCOM3_SPI_CS1 (__FLEXCOM3_SPI | __FLEXCOM_SPI_CS1)
|
||||
|
||||
#define FLEXCOM4_SPI_CS0 (__FLEXCOM4_SPI | __FLEXCOM_SPI_CS0)
|
||||
#define FLEXCOM4_SPI_CS1 (__FLEXCOM4_SPI | __FLEXCOM_SPI_CS1)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Inline Functions
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_flex_spibus_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the selected SPI port
|
||||
*
|
||||
* Input Parameters:
|
||||
* cs - Chip select number (identifying the "logical" SPI port)
|
||||
*
|
||||
* Returned Value:
|
||||
* Valid SPI device structure reference on success; a NULL on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
struct spi_dev_s *sam_flex_spibus_initialize(int port);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_flexcom_spi[0|1|2|3|4]select, sam_flexcom_spi[0|1|2|3|4]status,
|
||||
* and sam_flexcom_spi[0|1|2|3|4]cmddata
|
||||
*
|
||||
* Description:
|
||||
* These external functions must be provided by board-specific logic. They
|
||||
* include:
|
||||
*
|
||||
* o sam_flexcom_spi[0|1|2|3|4]select is a functions to manage the
|
||||
* board-specific chip selects
|
||||
* o sam_flexcom_spi[0|1|2|3|4]status and sam_flexcom_spi[0|1|2|3|4]cmddata
|
||||
* implementations of the status and cmddata methods of the SPI interface
|
||||
* defined by struct spi_ops_ (see include/nuttx/spi/spi.h).
|
||||
* All other methods including sam_flex_spibus_initialize()) are provided
|
||||
* by common SAM2/3/4 logic.
|
||||
*
|
||||
* To use this common SPI logic on your board:
|
||||
*
|
||||
* 1. Provide logic in sam_boardinitialize() to configure FLEXCOM SPI
|
||||
* chip select pins.
|
||||
* 2. Provide sam_flexcom_spi[0|1|2|3|4]select() and
|
||||
* sam_flexcom_spi[0|1|2|3|4]status() functions in your board-specific
|
||||
* logic. These functions will perform chip selection and status
|
||||
* operations using PIOs in the way your board is configured.
|
||||
* 2. If CONFIG_FLEXCOMx_SPI_CMDDATA is defined in the NuttX configuration,
|
||||
* provide sam_flexcom_spi[0|1|2|3|4]cmddata() functions in your
|
||||
* board-specific logic. This function will perform cmd/data selection
|
||||
* operations using PIOs in the way your board is configured.
|
||||
* 3. Add a call to sam_flex_spibus_initialize() in your low level
|
||||
* application initialization logic
|
||||
* 4. The handle returned by sam_flex_spibus_initialize() may then be used
|
||||
* to bind the FLEXCOM SPI driver to higher level logic (e.g., calling
|
||||
* mmcsd_spislotinitialize(), for example, will bind the SPI driver to
|
||||
* the SPI MMC/SD driver).
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_flexcom_spi[0|1|2|3|4]select
|
||||
*
|
||||
* Description:
|
||||
* PIO chip select pins may be programmed by the board specific logic in
|
||||
* one of two different ways. First, the pins may be programmed as SPI
|
||||
* peripherals. In that case, the pins are completely controlled by the
|
||||
* SPI driver. This method still needs to be provided, but it may be only
|
||||
* a stub.
|
||||
*
|
||||
* An alternative way to program the PIO chip select pins is as a normal
|
||||
* PIO output. In that case, the automatic control of the CS pins is
|
||||
* bypassed and this function must provide control of the chip select.
|
||||
* NOTE: In this case, the PIO output pin does *not* have to be the
|
||||
* same as the NPCS pin normal associated with the chip select number.
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - SPI device info
|
||||
* devid - Identifies the (logical) device
|
||||
* selected - TRUE:Select the device, FALSE:De-select the device
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_SAMA5_FLEXCOM0_SPI
|
||||
void sam_flexcom0_spiselect(uint32_t devid, bool selected);
|
||||
#endif
|
||||
#ifdef CONFIG_SAMA5_FLEXCOM1_SPI
|
||||
void sam_flexcom1_spiselect(uint32_t devid, bool selected);
|
||||
#endif
|
||||
#ifdef CONFIG_SAMA5_FLEXCOM2_SPI
|
||||
void sam_flexcom2_spiselect(uint32_t devid, bool selected);
|
||||
#endif
|
||||
#ifdef CONFIG_SAMA5_FLEXCOM3_SPI
|
||||
void sam_flexcom3_spiselect(uint32_t devid, bool selected);
|
||||
#endif
|
||||
#ifdef CONFIG_SAMA5_FLEXCOM4_SPI
|
||||
void sam_flexcom4_spiselect(uint32_t devid, bool selected);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_flexcom_spi[0|1|2|3|4]status
|
||||
*
|
||||
* Description:
|
||||
* Return status information associated with the SPI device.
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - SPI device info
|
||||
* devid - Identifies the (logical) device
|
||||
*
|
||||
* Returned Value:
|
||||
* Bit-encoded SPI status (see include/nuttx/spi/spi.h.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_SAMA5_FLEXCOM0_SPI
|
||||
uint8_t sam_flexcom0_spistatus(struct spi_dev_s *dev, uint32_t devid);
|
||||
#endif
|
||||
#ifdef CONFIG_SAMA5_FLEXCOM1_SPI
|
||||
uint8_t sam_flexcom1_spistatus(struct spi_dev_s *dev, uint32_t devid);
|
||||
#endif
|
||||
#ifdef CONFIG_SAMA5_FLEXCOM2_SPI
|
||||
uint8_t sam_flexcom2_spistatus(struct spi_dev_s *dev, uint32_t devid);
|
||||
#endif
|
||||
#ifdef CONFIG_SAMA5_FLEXCOM3_SPI
|
||||
uint8_t sam_flexcom3_spistatus(struct spi_dev_s *dev, uint32_t devid);
|
||||
#endif
|
||||
#ifdef CONFIG_SAMA5_FLEXCOM4_SPI
|
||||
uint8_t sam_flexcom4_spistatus(struct spi_dev_s *dev, uint32_t devid);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_spi[0|1|2|3|4]cmddata
|
||||
*
|
||||
* Description:
|
||||
* Some SPI devices require an additional control to determine if the SPI
|
||||
* data being sent is a command or is data. If CONFIG_SPI_CMDDATA then
|
||||
* this function will be called to different be command and data transfers.
|
||||
*
|
||||
* This is often needed, for example, by LCD drivers. Some LCD hardware
|
||||
* may be configured to use 9-bit data transfers with the 9th bit
|
||||
* indicating command or data. That same hardware may be configurable,
|
||||
* instead, to use 8-bit data but to require an additional, board-
|
||||
* specific PIO control to distinguish command and data. This function
|
||||
* would be needed in that latter case.
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - SPI device info
|
||||
* devid - Identifies the (logical) device
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero on success; a negated errno on failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_FLEXCOM_SPI_CMDDATA
|
||||
#ifdef CONFIG_SAMA5_FLEXCOM0_SPI
|
||||
int sam_flexcom0_spicmddata(struct spi_dev_s *dev, uint32_t devid,
|
||||
bool cmd);
|
||||
#endif
|
||||
#ifdef CONFIG_SAMA5_FLEXCOM1_SPI
|
||||
int sam_flexcom1_spicmddata(struct spi_dev_s *dev, uint32_t devid,
|
||||
bool cmd);
|
||||
#endif
|
||||
#ifdef CONFIG_SAMA5_FLEXCOM2_SPI
|
||||
int sam_flexcom2_spicmddata(struct spi_dev_s *dev, uint32_t devid,
|
||||
bool cmd);
|
||||
#endif
|
||||
#ifdef CONFIG_SAMA5_FLEXCOM3_SPI
|
||||
int sam_flexcom3_spicmddata(struct spi_dev_s *dev, uint32_t devid,
|
||||
bool cmd);
|
||||
#endif
|
||||
#ifdef CONFIG_SAMA5_FLEXCOM4_SPI
|
||||
int sam_flexcom4_spicmddata(struct spi_dev_s *dev, uint32_t devid,
|
||||
bool cmd);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_SAMA5_SAM_FLEXCOM_SPI_H */
|
||||
Loading…
Reference in New Issue
Block a user