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SAML21 DMA: BASEADDR and WRBADDR can only be written while the DMAC is disabled

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This commit is contained in:
Gregory Nutt 2015-06-14 11:46:44 -06:00
parent a13a691bff
commit e6df02fc17
1 changed files with 9 additions and 15 deletions
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24
arch/arm/src/samdl/sam_dmac.c
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@ -618,11 +618,7 @@ static int sam_single(struct sam_dmach_s *dmach)
{ {
struct dma_desc_s *head = &g_base_desc[dmach->dc_chan]; struct dma_desc_s *head = &g_base_desc[dmach->dc_chan];
/* Clear any pending interrupts from any previous DMAC transfer. /* Clear any pending interrupts from any previous DMAC transfer. */
*
* REVISIT: If DMAC interrupts are disabled at the NVIKC, then reading the
* EBCISR register could cause a loss of interrupts!
*/
#warning Missing logic #warning Missing logic
/* Set up the DMA */ /* Set up the DMA */
@ -651,11 +647,7 @@ static int sam_multiple(struct sam_dmach_s *dmach)
{ {
struct dma_desc_s *head = &g_base_desc[dmach->dc_chan]; struct dma_desc_s *head = &g_base_desc[dmach->dc_chan];
/* Clear any pending interrupts from any previous DMAC transfer. /* Clear any pending interrupts from any previous DMAC transfer. */
*
* REVISIT: If DMAC interrupts are disabled at the NVIKC, then reading the
* EBCISR register could cause a loss of interrupts!
*/
#warning Missing logic #warning Missing logic
/* Set up the initial DMA */ /* Set up the initial DMA */
@ -729,15 +721,17 @@ void weak_function up_dmainitialize(void)
(void)irq_attach(SAM_IRQ_DMAC, sam_dmainterrupt); (void)irq_attach(SAM_IRQ_DMAC, sam_dmainterrupt);
/* Enable the DMA controller */ /* Set the LPRAM DMA descriptor table addresses. These can only be
* written when the DMAC is disabled.
putreg16(DMAC_CTRL_DMAENABLE, SAM_DMAC_CTRL); */
/* Set the LPRAM DMA descriptor table addresses */
putreg32((uint32_t)g_base_desc, SAM_DMAC_BASEADDR); putreg32((uint32_t)g_base_desc, SAM_DMAC_BASEADDR);
putreg32((uint32_t)g_writeback_desc, SAM_DMAC_WRBADDR); putreg32((uint32_t)g_writeback_desc, SAM_DMAC_WRBADDR);
/* Enable the DMA controller */
putreg16(DMAC_CTRL_DMAENABLE, SAM_DMAC_CTRL);
/* Enable the IRQ at the NVIC (still disabled at the DMA controller) */ /* Enable the IRQ at the NVIC (still disabled at the DMA controller) */
up_enable_irq(SAM_IRQ_DMAC); up_enable_irq(SAM_IRQ_DMAC);