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LPC1788 PLL configuration from Rommel Marcelo

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5654 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2013-02-16 12:46:09 +00:00
parent 104692928d
commit e6f3604333
5 changed files with 29 additions and 21 deletions
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6
arch/arm/include/irq.h
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@ -57,9 +57,11 @@
*/
#if defined(CONFIG_ARCH_CORTEXM3) || defined(CONFIG_ARCH_CORTEXM4)
# include <arch/armv7-m/irq.h>
# include <arch/armv7-m/irq.h>
#elif defined(CONFIG_ARCH_CORTEXM0)
# include <arch/armv6-m/irq.h>
#else
# include <arch/arm/irq.h>
# include <arch/arm/irq.h>
#endif
/****************************************************************************

6
arch/arm/include/syscall.h
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@ -47,9 +47,11 @@
/* Include ARM architecture-specific syscall macros */
#if defined(CONFIG_ARCH_CORTEXM3) || defined(CONFIG_ARCH_CORTEXM4)
# include <arch/armv7-m/syscall.h>
# include <arch/armv7-m/syscall.h>
#elif defined(CONFIG_ARCH_CORTEXM0)
# include <arch/armv6-m/syscall.h>
#else
# include <arch/arm/syscall.h>
# include <arch/arm/syscall.h>
#endif
/****************************************************************************

2
arch/arm/include/types.h
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@ -89,7 +89,7 @@ typedef unsigned int _uintptr_t;
*/
#ifdef __thumb2__
#ifdef CONFIG_ARMV7M_USEBASEPRI
#if defined(CONFIG_ARMV7M_USEBASEPRI) || defined(CONFIG_ARCH_ARMV6M)
typedef unsigned char irqstate_t;
#else
typedef unsigned short irqstate_t;

4
arch/arm/src/Makefile
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@ -42,9 +42,13 @@ else
ifeq ($(CONFIG_ARCH_CORTEXM4),y) # Cortex-M4 is ARMv7E-M
ARCH_SUBDIR = armv7-m
else
ifeq ($(CONFIG_ARCH_CORTEXM0),y) # Cortex-M0 is ARMv6-M
ARCH_SUBDIR = armv6-m
else
ARCH_SUBDIR = arm
endif
endif
endif
ifeq ($(CONFIG_WINDOWS_NATIVE),y)
ARCH_SRCDIR = $(TOPDIR)\arch\$(CONFIG_ARCH)\src

32
arch/arm/src/lpc17xx/chip/lpc178x_syscon.h
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@ -220,13 +220,13 @@
/* Bits 0-11: Reserved */
#define SYSCON_FLASHCFG_TIM_SHIFT (12) /* Bits 12-15: FLASHTIM Flash access time */
#define SYSCON_FLASHCFG_TIM_MASK (15 << SYSCON_FLASHCFG_TIM_SHIFT)
# define SYSCON_FLASHCFG_TIM_1 (0 << SYSCON_FLASHCFG_TIM_SHIFT) /* 1 CPU clock <= 20 MHz CPU clock */
# define SYSCON_FLASHCFG_TIM_2 (1 << SYSCON_FLASHCFG_TIM_SHIFT) /* 2 CPU clock <= 40 MHz CPU clock */
# define SYSCON_FLASHCFG_TIM_3 (2 << SYSCON_FLASHCFG_TIM_SHIFT) /* 3 CPU clock <= 60 MHz CPU clock */
# define SYSCON_FLASHCFG_TIM_4 (3 << SYSCON_FLASHCFG_TIM_SHIFT) /* 4 CPU clock <= 80 MHz CPU clock */
# define SYSCON_FLASHCFG_TIM_5 (4 << SYSCON_FLASHCFG_TIM_SHIFT) /* 5 CPU clock <= 100 MHz CPU clock
# define SYSCON_FLASHCFG_TIM_0 (0) /* 1 CPU clock <= 20 MHz CPU clock */
# define SYSCON_FLASHCFG_TIM_1 (1 << SYSCON_FLASHCFG_TIM_SHIFT) /* 2 CPU clock <= 40 MHz CPU clock */
# define SYSCON_FLASHCFG_TIM_2 (2 << SYSCON_FLASHCFG_TIM_SHIFT) /* 3 CPU clock <= 60 MHz CPU clock */
# define SYSCON_FLASHCFG_TIM_3 (3 << SYSCON_FLASHCFG_TIM_SHIFT) /* 4 CPU clock <= 80 MHz CPU clock */
# define SYSCON_FLASHCFG_TIM_4 (4 << SYSCON_FLASHCFG_TIM_SHIFT) /* 5 CPU clock <= 100 MHz CPU clock
* (Up to 120 Mhz for LPC1788x) */
# define SYSCON_FLASHCFG_TIM_6 (5 << SYSCON_FLASHCFG_TIM_SHIFT) /* "safe" setting for any conditions */
# define SYSCON_FLASHCFG_TIM_5 (5 << SYSCON_FLASHCFG_TIM_SHIFT) /* "safe" setting for any conditions */
/* Bits 16-31: Reserved */
/* Memory Mapping Control register (MEMMAP - 0x400F C040) */
@ -289,16 +289,16 @@
/* Bits 9-31: Reserved */
/* USB Clock Configuration register */
#define SYSCON_USBCLKCFG_USBDIV_SHIFT (0) /* Bits 0-4: PLL0/1 divide value USB clock */
#define SYSCON_USBCLKCFG_USBDIV_MASK (0x1f << SYSCON_USBCLKCFG_USBDIV_SHIFT)
# define SYSCON_USBCLKCFG_USBDIV_DIV1 (1 << SYSCON_USBCLKCFG_USBDIV_SHIFT) /* PLL0/1 output must be 48MHz */
# define SYSCON_USBCLKCFG_USBDIV_DIV2 (2 << SYSCON_USBCLKCFG_USBDIV_SHIFT) /* PLL0/1 output must be 96MHz */
# define SYSCON_USBCLKCFG_USBDIV_DIV3 (3 << SYSCON_USBCLKCFG_USBDIV_SHIFT) /* PLL0/1 output must be 144MHz */
#define SYSCON_USBCLKSEL_USBDIV_SHIFT (0) /* Bits 0-4: PLL0/1 divide value USB clock */
#define SYSCON_USBCLKSEL_USBDIV_MASK (0x1f << SYSCON_USBCLKSEL_USBDIV_SHIFT)
# define SYSCON_USBCLKSEL_USBDIV_DIV1 (1 << SYSCON_USBCLKSEL_USBDIV_SHIFT) /* PLL0/1 output must be 48MHz */
# define SYSCON_USBCLKSEL_USBDIV_DIV2 (2 << SYSCON_USBCLKSEL_USBDIV_SHIFT) /* PLL0/1 output must be 96MHz */
# define SYSCON_USBCLKSEL_USBDIV_DIV3 (3 << SYSCON_USBCLKSEL_USBDIV_SHIFT) /* PLL0/1 output must be 144MHz */
/* Bits 5-7: Reserved */
#define SYSCON_USBCLKCFG_USBSEL_SHIFT (8) /* Bits 8-9: Input clock to USBDIV */
#define SYSCON_USBCLKCFG_USBSEL_MASK (3 << SYSCON_USBCLKCFG_USBSEL_SHIFT)
#define SYSCON_USBCLKCFG_USBSEL_MAINPLL (1 << SYSCON_USBCLKCFG_USBSEL_SHIFT) /* 01: PLL0 is used as input clock to USBDIV */
#define SYSCON_USBCLKCFG_USBSEL_ALTPLL (2 << SYSCON_USBCLKCFG_USBSEL_SHIFT) /* 10: PLL1 is used as input clock to USBDIV */
#define SYSCON_USBCLKSEL_USBSEL_SHIFT (8) /* Bits 8-9: Input clock to USBDIV */
#define SYSCON_USBCLKSEL_USBSEL_MASK (3 << SYSCON_USBCLKSEL_USBSEL_SHIFT)
#define SYSCON_USBCLKSEL_USBSEL_PLL0 (1 << SYSCON_USBCLKSEL_USBSEL_SHIFT) /* 01: PLL0 is used as input clock to USBDIV */
#define SYSCON_USBCLKSEL_USBSEL_PLL1 (2 << SYSCON_USBCLKSEL_USBSEL_SHIFT) /* 10: PLL1 is used as input clock to USBDIV */
/* 11: unused */
/* Bits 10-31: Reserved */
/* CAN0/1 Sleep Clear Register */
@ -383,7 +383,7 @@
#define SYSCON_PCONP_PCCAN1 (1 << 13) /* Bit 13: CAN Controller 1 power/clock control */
#define SYSCON_PCONP_PCCAN2 (1 << 14) /* Bit 14: CAN Controller 2 power/clock control */
#define SYSCON_PCONP_PCGPIO (1 << 15) /* Bit 15: GPIOs power/clock enable */
#define SYSCON_PCONP_PCRIT (1 << 16) /* Bit 16: Repetitive Interrupt Timer power/clock control */
#define SYSCON_PCONP_PCSPIFI (1 << 16) /* Bit 16: SPI Flash Interface power/clock control */
#define SYSCON_PCONP_PCMCPWM (1 << 17) /* Bit 17: Motor Control PWM */
#define SYSCON_PCONP_PCQEI (1 << 18) /* Bit 18: Quadrature Encoder power/clock control */
#define SYSCON_PCONP_PCI2C1 (1 << 19) /* Bit 19: I2C1 power/clock control */