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Spark configuration updates from David Sidrane

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This commit is contained in:
Gregory Nutt 2013-10-16 07:55:04 -06:00
parent e555cfaa5b
commit e7428e9cbc
9 changed files with 994 additions and 251 deletions
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40
configs/spark/Kconfig
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@ -5,4 +5,44 @@
if ARCH_BOARD_SPARK
config SPARK_FLASH
bool "MTD driver for onboard 2M FLASH"
default y
select MTD
select MTD_SST25
select FS_FAT
select STM32_SPI2
select MTD_BYTE_WRITE
---help---
Configures an MTD device for use with the onboard flash
config SPARK_FLASH_SPI
int "Flash SPI bus number"
default 2
depends on SPARK_FLASH
---help---
Selects the SPI bus number identying that SPI interface that
connects the Flash to the MCU.
config SPARK_FLASH_MINOR
int "Minor number for the FLASH /dev/fat entry"
default 0
depends on SPARK_FLASH
---help---
Sets the minor number for the FLASH MTD /dev entry
config SPARK_FLASH_PART
bool "Enable partition support on FLASH"
default n
depends on SPARK_FLASH
---help---
Enables creation of partitions on the FLASH
config SPARK_FLASH_PART_LIST
string "Flash partition size list"
default "512,1536"
depends on SPARK_FLASH_PART
---help---
Comma separated list of partition sizes in KB
endif

497
configs/spark/README.txt
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@ -1,26 +1,297 @@
README
======
This README discusses issues unique to NuttX configurations for the Spark Core board from Spark Devices (http://www.sparkdevices.com). This board features the STM32103CBT6 MCU from STMicro.
This README discusses issues unique to NuttX configurations for the Spark Core board from Spark Devices (http://www.spark.io). This board features the STM32103CBT6 MCU from STMicro.
Microprocessor: 32-bit ARM Cortex M3 at 72MHz STM32F103CBT6
Memory: 120 KB Flash and 20 KB SRAM, 2M serial Flash
I/O Pins Out: 37, 17 On the Connector
Network: TI CC3000 Wifi Module
ADCs: 9 (at 12-bit resolution)
Peripherals: 4 timers, 2 I2Cs, 2 SPI ports, 3 USARTs, 2 led's one Blue and one RGB.
Other: Sleep, stop, and standby modes; serial wire debug and JTAG interfaces
During the development of the SparkCore, the hardware was in limited supply
As a work around DAvid Sidrane <david_s5@nscdg.com> created a SparkCore Big board
(http://nscdg.com/spark/sparkBB.png) that will interface with a maple mini
(http://leaflabs.com/docs/hardware/maple-mini.html), and a CC3000BOOST
(https://estore.ti.com/CC3000BOOST-CC3000-BoosterPack-P4258.aspx)
It breaks out the Tx, Rx to connect to a FTDI TTL-232RG-VREG3V3-WE for the console and
wires in the spark LEDs and serial flash to the same I/O as the sparkcore. It has a Jlink
compatible Jtag connector on it.
Contents
========
- Development Environment
- DFU
- GNU Toolchain Options
- IDEs
- NuttX EABI "buildroot" Toolchain
- NuttX OABI "buildroot" Toolchain
- NXFLAT Toolchain
- Hardware
- Core Pin out
- LEDs
- Buttons
- USARTS and Serial Consoles
- DFU and JTAG
- Spark -specific Configuration Options
- Configurations
Development Environment
=======================
Either Linux (recommended), Mac or Cygwin on Windows can be used for the development environment.
Either Linux or Cygwin on Windows can be used for the development environment.
The source has been built only using the GNU toolchain (see below). Other
toolchains will likely cause problems. Testing was performed using the Cygwin
environment because the Raisonance R-Link emulatator and some RIDE7 development tools
were used and those tools works only under Windows.
toolchains will likely cause problems.
DFU
===
GNU Toolchain Options
=====================
Toolchain Configurations
------------------------
The NuttX make system has been modified to support the following different
toolchain options.
1. The CodeSourcery GNU toolchain,
2. The Atollic Toolchain,
3. The devkitARM GNU toolchain,
4. Raisonance GNU toolchain, or
5. The NuttX buildroot Toolchain (see below).
All testing has been conducted using the CodeSourcery toolchain for Linux. To use
the Atollic, devkitARM, Raisonance GNU, or NuttX buildroot toolchain, you simply need to
add one of the following configuration options to your .config (or defconfig)
file:
CONFIG_STM32_CODESOURCERYW=n : CodeSourcery under Windows
CONFIG_STM32_CODESOURCERYL=y : CodeSourcery under Linux
CONFIG_STM32_ATOLLIC_LITE=n : The free, "Lite" version of Atollic toolchain under Windows
CONFIG_STM32_ATOLLIC_PRO=n : The paid, "Pro" version of Atollic toolchain under Windows
CONFIG_STM32_DEVKITARM=n : devkitARM under Windows
CONFIG_STM32_RAISONANCEny : Raisonance RIDE7 under Windows
CONFIG_STM32_BUILDROOT=n : NuttX buildroot under Linux or Cygwin (default)
If you change the default toolchain, then you may also have to modify the PATH in
the setenv.h file if your make cannot find the tools.
NOTE: the CodeSourcery (for Windows), Atollic, devkitARM, and Raisonance toolchains are
Windows native toolchains. The CodeSourcey (for Linux) and NuttX buildroot
toolchains are Cygwin and/or Linux native toolchains. There are several limitations
to using a Windows based toolchain in a Cygwin environment. The three biggest are:
1. The Windows toolchain cannot follow Cygwin paths. Path conversions are
performed automatically in the Cygwin makefiles using the 'cygpath' utility
but you might easily find some new path problems. If so, check out 'cygpath -w'
2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links
are used in Nuttx (e.g., include/arch). The make system works around these
problems for the Windows tools by copying directories instead of linking them.
But this can also cause some confusion for you: For example, you may edit
a file in a "linked" directory and find that your changes had no effect.
That is because you are building the copy of the file in the "fake" symbolic
directory. If you use a Windows toolchain, you should get in the habit of
making like this:
make clean_context all
An alias in your .bashrc file might make that less painful.
3. Dependencies are not made when using Windows versions of the GCC. This is
because the dependencies are generated using Windows pathes which do not
work with the Cygwin make.
MKDEP = $(TOPDIR)/tools/mknulldeps.sh
The CodeSourcery Toolchain (2009q1)
-----------------------------------
The CodeSourcery toolchain (2009q1) does not work with default optimization
level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with
-Os.
The Atollic "Pro" and "Lite" Toolchain
--------------------------------------
One problem that I had with the Atollic toolchains is that the provide a gcc.exe
and g++.exe in the same bin/ file as their ARM binaries. If the Atollic bin/ path
appears in your PATH variable before /usr/bin, then you will get the wrong gcc
when you try to build host executables. This will cause to strange, uninterpretable
errors build some host binaries in tools/ when you first make.
Also, the Atollic toolchains are the only toolchains that have built-in support for
the FPU in these configurations. If you plan to use the Cortex-M4 FPU, you will
need to use the Atollic toolchain for now. See the FPU section below for more
information.
The Atollic "Lite" Toolchain
----------------------------
The free, "Lite" version of the Atollic toolchain does not support C++ nor
does it support ar, nm, objdump, or objdcopy. If you use the Atollic "Lite"
toolchain, you will have to set:
CONFIG_HAVE_CXX=n
In order to compile successfully. Otherwise, you will get errors like:
"C++ Compiler only available in TrueSTUDIO Professional"
The make may then fail in some of the post link processing because of some of
the other missing tools. The Make.defs file replaces the ar and nm with
the default system x86 tool versions and these seem to work okay. Disable all
of the following to avoid using objcopy:
CONFIG_RRLOAD_BINARY=n
CONFIG_INTELHEX_BINARY=n
CONFIG_MOTOROLA_SREC=n
CONFIG_RAW_BINARY=n
devkitARM
---------
The devkitARM toolchain includes a version of MSYS make. Make sure that the
the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM
path or will get the wrong version of make.
IDEs
====
NuttX is built using command-line make. It can be used with an IDE, but some
effort will be required to create the project.
Makefile Build
--------------
Under Eclipse, it is pretty easy to set up an "empty makefile project" and
simply use the NuttX makefile to build the system. That is almost for free
under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty
makefile project in order to work with Windows (Google for "Eclipse Cygwin" -
there is a lot of help on the internet).
Using Sourcery CodeBench from http://www.mentor.com/embedded-software/sourcery-tools/sourcery-codebench/overview
1) Download and install the latest version (as of this writting it was sourceryg++-2013.05-64-arm-none-eabi)
Import the project from git.
File->import->Git-URI, then import a Exiting code as a Makefile progject from the working directory the
git clone was done to.
Select the Sourcery CodeBench for ARM EABI. N.B. You must do one command line build,
before the make will work in CodeBench.
Native Build
------------
Here are a few tips before you start that effort:
1) Select the toolchain that you will be using in your .config file
2) Start the NuttX build at least one time from the Cygwin command line
before trying to create your project. This is necessary to create
certain auto-generated files and directories that will be needed.
3) Set up include pathes: You will need include/, arch/arm/src/stm32,
arch/arm/src/common, arch/arm/src/armv7-m, and sched/.
4) All assembly files need to have the definition option -D __ASSEMBLY__
on the command line.
Startup files will probably cause you some headaches. The NuttX startup file
is arch/arm/src/stm32/stm32_vectors.S. With RIDE, I have to build NuttX
one time from the Cygwin command line in order to obtain the pre-built
startup object needed by RIDE.
NuttX EABI "buildroot" Toolchain
================================
A GNU GCC-based toolchain is assumed. The files */setenv.sh should
be modified to point to the correct path to the Cortex-M3 GCC toolchain (if
different from the default in your PATH variable).
If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX
SourceForge download site (https://sourceforge.net/projects/nuttx/files/buildroot/).
This GNU toolchain builds and executes in the Linux or Cygwin environment.
1. You must have already configured Nuttx in <some-dir>/nuttx.
cd tools
./configure.sh stm32_tiny/<sub-dir>
2. Download the latest buildroot package into <some-dir>
3. unpack the buildroot tarball. The resulting directory may
have versioning information on it like buildroot-x.y.z. If so,
rename <some-dir>/buildroot-x.y.z to <some-dir>/buildroot.
4. cd <some-dir>/buildroot
5. cp configs/cortexm3-eabi-defconfig-4.6.3 .config
6. make oldconfig
7. make
8. Edit setenv.h, if necessary, so that the PATH variable includes
the path to the newly built binaries.
See the file configs/README.txt in the buildroot source tree. That has more
details PLUS some special instructions that you will need to follow if you are
building a Cortex-M3 toolchain for Cygwin under Windows.
NOTE: Unfortunately, the 4.6.3 EABI toolchain is not compatible with the
the NXFLAT tools. See the top-level TODO file (under "Binary loaders") for
more information about this problem. If you plan to use NXFLAT, please do not
use the GCC 4.6.3 EABI toochain; instead use the GCC 4.3.3 OABI toolchain.
See instructions below.
NuttX OABI "buildroot" Toolchain
================================
The older, OABI buildroot toolchain is also available. To use the OABI
toolchain:
1. When building the buildroot toolchain, either (1) modify the cortexm3-eabi-defconfig-4.6.3
configuration to use EABI (using 'make menuconfig'), or (2) use an exising OABI
configuration such as cortexm3-defconfig-4.3.3
2. Modify the Make.defs file to use the OABI conventions:
+CROSSDEV = arm-nuttx-elf-
+ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft
+NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections
-CROSSDEV = arm-nuttx-eabi-
-ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft
-NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
NXFLAT Toolchain
================
If you are *not* using the NuttX buildroot toolchain and you want to use
the NXFLAT tools, then you will still have to build a portion of the buildroot
tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can
be downloaded from the NuttX SourceForge download site
(https://sourceforge.net/projects/nuttx/files/).
This GNU toolchain builds and executes in the Linux or Cygwin environment.
1. You must have already configured Nuttx in <some-dir>/nuttx.
cd tools
./configure.sh lpcxpresso-lpc1768/<sub-dir>
2. Download the latest buildroot package into <some-dir>
3. unpack the buildroot tarball. The resulting directory may
have versioning information on it like buildroot-x.y.z. If so,
rename <some-dir>/buildroot-x.y.z to <some-dir>/buildroot.
4. cd <some-dir>/buildroot
5. cp configs/cortexm3-defconfig-nxflat .config
6. make oldconfig
7. make
8. Edit setenv.h, if necessary, so that the PATH variable includes
the path to the newly builtNXFLAT binaries.
DFU and JTAG
============
Enbling Support for the DFU Bootloader
--------------------------------------
The linker files in these projects can be configured to indicate that you
will be loading code using STMicro built-in USB Device Firmware Upgrade (DFU)
loader or via some JTAG emulator. You can specify the DFU bootloader by
@ -35,7 +306,7 @@ DFU
of FLASH (0x08000000) but will be offset to 0x08005000. This offset is needed
to make space for the DFU loader and 0x08005000 is where the DFU loader expects
to find new applications at boot time. If you need to change that origin for some
other bootloader, you will need to edit the file(s) ld.script.dfu for each
other bootloader, you will need to edit the file(s) ld.script.dfu for the
configuration.
For Linux or Mac:
@ -61,23 +332,211 @@ DFU
The DFU SE PC-based software is available from the STMicro website,
http://www.st.com. General usage instructions:
1. Connect the Spark board to your computer using a USB
1. Convert the NuttX Intel Hex file (nuttx.hex) into a special DFU
file (nuttx.dfu)... see below for details.
2. Connect the M3 Wildfire board to your computer using a USB
cable.
2. Start the DFU loader on the Spark board. You do this by
resetting the board while holding the "Key" button. Windows should
3. Start the DFU loader on the M3 Wildfire board. You do this by
resetting the board while holding the "Key" button. Windows should
recognize that the DFU loader has been installed.
3. Run the DFU SE program to load nuttx.bin into FLASH.
3. Run the DFU SE program to load nuttx.dfu into FLASH.
What if the DFU loader is not in FLASH? The loader code is available
What if the DFU loader is not in FLASH? The loader code is available
inside of the Demo dirctory of the USBLib ZIP file that can be downloaded
from the STMicro Website. You can build it using RIDE (or other toolchains);
from the STMicro Website. You can build it using RIDE (or other toolchains);
you will need a JTAG emulator to burn it into FLASH the first time.
In order to use STMicro's built-in DFU loader, you will have to get
the NuttX binary into a special format with a .dfu extension. The
the NuttX binary into a special format with a .dfu extension. The
DFU SE PC_based software installation includes a file "DFU File Manager"
conversion program that a file in Intel Hex format to the special DFU
format. When you successfully build NuttX, you will find a file called
nutt.hex in the top-level directory. That is the file that you should
provide to the DFU File Manager. You will end up with a file called
format. When you successfully build NuttX, you will find a file called
nutt.hex in the top-level directory. That is the file that you should
provide to the DFU File Manager. You will end up with a file called
nuttx.dfu that you can use with the STMicro DFU SE program.
Enabling JTAG
-------------
If you are not using the DFU, then you will probably also need to enable
JTAG support. By default, all JTAG support is disabled but there NuttX
configuration options to enable JTAG in various different ways.
These configurations effect the setting of the SWJ_CFG[2:0] bits in the AFIO
MAPR register. These bits are used to configure the SWJ and trace alternate function I/Os.
The SWJ (SerialWire JTAG) supports JTAG or SWD access to the Cortex debug port.
The default state in this port is for all JTAG support to be disable.
CONFIG_STM32_JTAG_FULL_ENABLE - sets SWJ_CFG[2:0] to 000 which enables full
SWJ (JTAG-DP + SW-DP)
CONFIG_STM32_JTAG_NOJNTRST_ENABLE - sets SWJ_CFG[2:0] to 001 which enable
full SWJ (JTAG-DP + SW-DP) but without JNTRST.
CONFIG_STM32_JTAG_SW_ENABLE - sets SWJ_CFG[2:0] to 010 which would set JTAG-DP
disabled and SW-DP enabled
The default setting (none of the above defined) is SWJ_CFG[2:0] set to 100
which disable JTAG-DP and SW-DP.
Hardware
=======================
The Spark comprises a STM32F103CB 72 Mhz, 128 Flash, 20K Ram, with 37 IO Pins, and
a TI CC3000 Wifi Module. It has a 2MB serial flash, onboad regulation and 2 led's
one Blue and one RGB.
During the development of the SparkCore, the hardware was in limited supply
As a work around david_s5 created a SparkCore Big board (http://nscdg.com/spark/sparkBB.png)
that will interface with a maple mini (http://leaflabs.com/docs/hardware/maple-mini.html),
and a CC3000BOOST (https://estore.ti.com/CC3000BOOST-CC3000-BoosterPack-P4258.aspx)
It breaks out the Tx, Rx to connect to a FTDI TTL-232RG-VREG3V3-WE for the console and
wires in the spark LEDs and serial flash to the same I/O as the sparkcore. It has a Jlink
compatible Jtag connector on it.
Core Pin out
^^^^^^^^^^^^^^^^
There are 24 pis on the Spark Core module.
Spark Spark Function STM32F103CBT6
Name Pin # Pin #
-------- ------ ------------------------------------------------ ---------------
RAW JP1-1 Input Power N/A
GND JP1-2 GND
TX JP1-3 PA[02] USART2_TX/ADC12_IN2/TIM2_CH3 12
RX JP1-4 PA[03] USART2_RX/ADC12_IN3/TIM2_CH4 13
A7 JP1-5 PB[01] ADC12_IN9/TIM3_CH4 19
A6 JP1-6 PB[00] ADC12_IN8/TIM3_CH3 18
A5 JP1-7 PA[07] SPI1_MOSI/ADC12_IN7/TIM3_CH2 17
A4 JP1-8 PA[06] SPI1_MISO/ADC12_IN6/TIM3_CH1 16
A3 JP1-9 PA[05] SPI1_SCK/ADC12_IN5 15
A2 JP1-10 PA[04] SPI1_NSS/USART2_CK/ADC12_IN4 14
A1 JP1-11 PA[01] USART2_RTS/ADC12_IN1/TIM2_CH2 11
A0 JP1-12 PA[00] WKUP/USART2_CTS/ADC12_IN0/TIM2_CH1_ETR 10
+3V3 JP2-1 V3.3 Out of Core NA
RST JP2-2 NRST 7
VDDA JP2-3 ADC Voltage 9
GND JP2-4 GND
D7 JP2-5 PA[13] JTMS/SWDIO 34 Common with Blue LED LED_USR
D6 JP2-6 PA[14] JTCK/SWCLK 37
D5 JP2-7 PA[15] JTDI 38
D4 JP2-8 PB[03] JTDO 39
D3 JP2-9 PB[04] NJTRST 40
D2 JP2-10 PB[05] I2C1_SMBA 41
D1 JP2-11 PB[06] I2C1_SCL/TIM4_CH1 42
D0 JP2-12 PB[07] I2C1_SDA/TIM4_CH2 43
Core Internal IO
^^^^^^^^^^^^^^^^^
Spark Function STM32F103CBT6
Name Pin #
-------- ------------------------------------------------ ---------------
BTN PB[02] BOOT1 20
LED1,D7 PA[13] JTMS/SWDIO 34
LED2 PA[08] USART1_CK/TIM1_CH1/MCO 29
LED3 PA[09] USART1_TX/TIM1_CH2 30
LED4 PA[10] USART1_RX/TIM1_CH3 31
MEM_CS PB[09] TIM4_CH4 46 SST25VF016B Chip Select
SPI_CLK PB[13] SPI2_SCK/USART3_CTS/TIM1_CH1N 26
SPI_MISO PB[14] SPI2_MISO/USART3_RTS/TIM1_CH2N 27
SPI_MOSI PB[15] SPI2_MOSI/TIM1_CH3N 28
USB_DISC PB[10] I2C2_SCL/USART3_TX 21
WIFI_CS PB[12] SPI2_NSS/I2C2_SMBA/USART3_CK/TIM1_BKIN 25 CC3000 Chip Select
WIFI_EN PB[08] TIM4_CH3 45 CC3000 Module enable
WIFI_INT PB[11] I2C2_SDA/USART3_RX 22 CC3000 Host interface SPI interrupt
Buttons and LEDs
^^^^^^^^^^^^^^^^
Buttons
-------
The Spark has two mechanical buttons. One button is the RESET button
connected to the STM32F103CB's reset line via /RST and the other is a
generic user configurable button labeled BTN and connected to GPIO
PB2/BOOT1. Since on the Spark, BOOT0 is tied to GND it is a moot point
that BTN signal is connected to the BOOT1 signal. When a button is
pressed it will drive the I/O line to GND.
LEDs
----
There are 4 user-controllable LEDs in two packages on board the Spark board:
Sigal Location Color GPIO Active
------- ------------ ----------- ----- -----------
LED1 LED_USR Blue LED PA13 High Common With D7
LED2 LED_RGB Red LED PA8 Low
LED3 LED_RGB Blue LED PA9 Low
LED4 LED_RGB Green LED PA10 Low
LED1 is connected to ground and can be illuminated by driving the PA13
output high, it shares the Sparks D7 output. The LED2,LED3 and LED4
are pulled high and can be illuminated by driving the corresponding GPIO output
to low.
The RGB LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
defined. In that case, the usage by the board port is defined in
include/board.h and src/up_leds.c. The LEDs are used to encode OS-related
events as follows:
SYMBOL Meaning LED2 LED3 LED4
red blue green Color
------------------- ----------------------- ------- ------- ------ ---------
LED_STARTED NuttX has been started ON OFF OFF Red
LED_HEAPALLOCATE Heap has been allocated OFF ON OFF Blue
LED_IRQSENABLED Interrupts enabled ON OFF ON Orange
LED_STACKCREATED Idle stack created OFF OFF ON Green
LED_INIRQ In an interrupt** ON N/C N/C Red Glow
LED_SIGNAL In a signal handler*** N/C ON N/C Blue Glow
LED_ASSERTION An assertion failed ON ON ON White
LED_PANIC The system has crashed ON N/C N/C Red Flashing
LED_IDLE STM32 is is sleep mode (Optional, not used)
* If LED2, LED3, LED4 are statically on, then NuttX probably failed to boot
and these LEDs will give you some indication of where the failure was
** The normal state is LED4 ON and LED2 faintly glowing. This faint glow
is because of timer interupts that result in the LED being illuminated
on a small proportion of the time.
*** LED3 may also flicker normally if signals are processed.
Serial Consoles
^^^^^^^^^^^^^^^
USART2
-----
If you have a 3.3 V TTL to RS-232 convertor then this is the most convenient
serial console to use. UART2 is the default in all of these
configurations.
USART2 RX PA3 JP1 pin 4
USART2 TX PA2 JP1 pin 3
GND JP1 pin 2
V3.3 JP2 pin 1
Virtual COM Port
----------------
Yet another option is to use UART0 and the USB virtual COM port. This
option may be more convenient for long term development, but was
painful to use during board bring-up.
Spark -specific Configuration Options
==============
WIP
Configurations
==============
WIP
1) SPI2 is enabled and support is included for the FAT file system
on the 16Mbit (2M) SST25 device on the spark core.
CONFIG_STM32_SPI2=y
CONFIG_MTD_SST25=y
CONFIG_SST25_SECTOR512=y
CONFIG_DISABLE_MOUNTPOINT=n
CONFIG_FS_FAT=y
CONFIG_NSH_ARCHINIT=y
When the system boots, you should have the FAT file system mounted
at /mnt/sst25 that will ba exported as MSD on the USB on insertion
of the USB connector

135
configs/spark/include/board.h
View File

@ -145,16 +145,63 @@
#endif
/* LED definitions ******************************************************************/
/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any
* way. The following definitions are used to access individual LEDs.
*/
/* LED index values for use with stm32_setled() */
#define BOARD_LED1 0 /* Tied to LED_USR */
#define BOARD_LED2 1 /* Tied to LED_RGB RED */
#define BOARD_LED3 2 /* Tied to LED_RGB BLUE */
#define BOARD_LED4 3 /* Tied to LED_RGB GREEN */
#define BOARD_NLEDS 4
#define BOARD_USR_LED_BLUE BOARD_LED1
#define BOARD_RGB_LED_RED BOARD_LED2
#define BOARD_RGB_LED_GREEN BOARD_LED4
#define BOARD_RGB_LED_BLUE BOARD_LED3
/* LED bits for use with stm32_setleds() */
#define BOARD_USR_LED_BIT (1 << BOARD_USR_LED_BLUE)
#define BOARD_RED_LED_BIT (1 << BOARD_RGB_LED_RED)
#define BOARD_BLUE_LED_BIT (1 << BOARD_RGB_LED_BLUE)
#define BOARD_GREEN_LED_BIT (1 << BOARD_RGB_LED_GREEN)
#define LED_ACTIVE_LOW (BOARD_RED_LED_BIT|BOARD_BLUE_LED_BIT|BOARD_GREEN_LED_BIT)
/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on board the
* spark. The following definitions describe how NuttX controls the LEDs:
*/
/* LED1 LED2 LED3 LED4 */
/* blue red blue green Color */
#define LED_STARTED 0 /* ------ ------ ------ ------ --------- */
#define LED_HEAPALLOCATE 1 /* OFF ON OFF OFF Red */
#define LED_IRQSENABLED 2 /* OFF OFF ON OFF Blue */
#define LED_STACKCREATED 3 /* OFF ON OFF ON Orange */
#define LED_INIRQ 4 /* N/C OFF OFF ON Green */
#define LED_SIGNAL 5 /* N/C ON N/C N/C Red Glow */
#define LED_ASSERTION 6 /* N/C N/C ON N/C Blue Glow */
#define LED_PANIC 7 /* N/C ON ON ON White */
#define LED_NUM_CODES 8
/* Button definitions ***************************************************************/
/* The Spark supports two buttons; only one button is controllable by software:
*
* BTN: user and wake-up button connected to the I/O PB2/BOOT1 of the STM32F103CB.
* N.B. Since BOOT0 is tied to GND it is a moot point that BTN signal is connected
* to the BOOT1 signal.
* RESET: This pushbutton connected to NRST is used to RESET the STM32F103CB.
*/
#define BUTTON_USER 0
#define NUM_BUTTONS 1
#define BUTTON_USER_BIT (1 << BUTTON_USER)
#define BUTTON_ACTIVE_LOW (BUTTON_USER_BIT)
/* The board has only one controllable LED */
#define LED_STARTED 0 /* No LEDs */
#define LED_HEAPALLOCATE 1 /* LED1 on */
#define LED_IRQSENABLED 2 /* LED2 on */
#define LED_STACKCREATED 3 /* LED1 on */
#define LED_INIRQ 4 /* LED1 off */
#define LED_SIGNAL 5 /* LED2 on */
#define LED_ASSERTION 6 /* LED1 + LED2 */
#define LED_PANIC 7 /* LED1 / LED2 blinking */
/************************************************************************************
* Public Data
@ -165,7 +212,8 @@
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C" {
extern "C"
{
#else
#define EXTERN extern
#endif
@ -173,6 +221,54 @@ extern "C" {
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
/************************************************************************************
* Button support.
*
* Description:
* up_buttoninit() must be called to initialize button resources. After
* that, up_buttons() may be called to collect the current state of all
* buttons or up_irqbutton() may be called to register button interrupt
* handlers.
*
* After up_buttoninit() has been called, up_buttons() may be called to
* collect the state of all buttons. up_buttons() returns an 8-bit bit set
* with each bit associated with a button. See the BUTTON_*_BIT and JOYSTICK_*_BIT
* definitions in board.h for the meaning of each bit.
*
* up_irqbutton() may be called to register an interrupt handler that will
* be called when a button is depressed or released. The ID value is a
* button enumeration value that uniquely identifies a button resource. See the
* BUTTON_* and JOYSTICK_* definitions in board.h for the meaning of enumeration
* value. The previous interrupt handler address is returned (so that it may
* restored, if so desired).
*
************************************************************************************/
#ifdef CONFIG_ARCH_BUTTONS
void up_buttoninit(void);
uint8_t up_buttons(void);
#ifdef CONFIG_ARCH_IRQBUTTONS
xcpt_t up_irqbutton(int id, xcpt_t irqhandler);
#endif
#endif
/************************************************************************************
* Name: up_ledinit, up_setled, and up_setleds
*
* Description:
* If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board LEDs. If
* CONFIG_ARCH_LEDS is not defined, then the following interfacesare available to
* control the LEDs from user applications.
*
************************************************************************************/
#ifndef CONFIG_ARCH_LEDS
#undef up_ledinit // Remove macro definition to reuse name
void up_ledinit(void);
void up_setled(int led, bool ledon);
void up_setleds(uint8_t ledset, uint8_t led_states_set);
#endif
/************************************************************************************
* Name: stm32_boardinitialize
*
@ -185,6 +281,25 @@ extern "C" {
void stm32_boardinitialize(void);
/************************************************************************************
* Name: nsh_archinitialize
*
* Description:
* Perform architecture specific initialization for NSH.
*
* CONFIG_NSH_ARCHINIT=y :
* Called from the NSH library
*
* CONFIG_BOARD_INITIALIZE=y, CONFIG_NSH_LIBRARY=y, &&
* CONFIG_NSH_ARCHINIT=n:
* Called from board_initialize().
*
************************************************************************************/
#ifdef CONFIG_NSH_LIBRARY
int nsh_archinitialize(void);
#endif
#undef EXTERN
#if defined(__cplusplus)
}

170
configs/spark/nsh/defconfig
View File

@ -100,8 +100,8 @@ CONFIG_ARCH_HAVE_MPU=y
#
# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set
# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set
# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set
CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y
CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y
# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL is not set
# CONFIG_SERIAL_TERMIOS is not set
#
@ -199,17 +199,17 @@ CONFIG_STM32_DFU=y
# CONFIG_STM32_ADC3 is not set
# CONFIG_STM32_BKP is not set
# CONFIG_STM32_CAN1 is not set
# CONFIG_STM32_CRC is not set
CONFIG_STM32_CRC=y
# CONFIG_STM32_DMA1 is not set
# CONFIG_STM32_DMA2 is not set
# CONFIG_STM32_DAC1 is not set
# CONFIG_STM32_DAC2 is not set
CONFIG_STM32_I2C1=y
CONFIG_STM32_I2C2=y
# CONFIG_STM32_I2C1 is not set
# CONFIG_STM32_I2C2 is not set
# CONFIG_STM32_PWR is not set
# CONFIG_STM32_SDIO is not set
# CONFIG_STM32_SPI1 is not set
# CONFIG_STM32_SPI2 is not set
CONFIG_STM32_SPI2=y
# CONFIG_STM32_TIM1 is not set
# CONFIG_STM32_TIM2 is not set
# CONFIG_STM32_TIM3 is not set
@ -218,23 +218,23 @@ CONFIG_STM32_I2C2=y
# CONFIG_STM32_TIM6 is not set
# CONFIG_STM32_TIM7 is not set
# CONFIG_STM32_TIM8 is not set
CONFIG_STM32_USART1=y
# CONFIG_STM32_USART2 is not set
# CONFIG_STM32_USART1 is not set
CONFIG_STM32_USART2=y
# CONFIG_STM32_USART3 is not set
# CONFIG_STM32_UART4 is not set
# CONFIG_STM32_UART5 is not set
CONFIG_STM32_USB=y
# CONFIG_STM32_IWDG is not set
# CONFIG_STM32_WWDG is not set
CONFIG_STM32_I2C=y
# CONFIG_STM32_I2C is not set
#
# Alternate Pin Mapping
#
# CONFIG_STM32_I2C1_REMAP is not set
# CONFIG_STM32_USART1_REMAP is not set
CONFIG_STM32_JTAG_DISABLE=y
# CONFIG_STM32_JTAG_FULL_ENABLE is not set
# CONFIG_STM32_JTAG_DISABLE is not set
CONFIG_STM32_JTAG_FULL_ENABLE=y
# CONFIG_STM32_JTAG_NOJNTRST_ENABLE is not set
# CONFIG_STM32_JTAG_SW_ENABLE is not set
# CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG is not set
@ -253,9 +253,9 @@ CONFIG_STM32_USART=y
# I2C Configuration
#
# CONFIG_STM32_I2C_DYNTIMEO is not set
CONFIG_STM32_I2CTIMEOSEC=1
CONFIG_STM32_I2CTIMEOMS=500
CONFIG_STM32_I2CTIMEOTICKS=500
# CONFIG_STM32_I2CTIMEOSEC is not set
# CONFIG_STM32_I2CTIMEOMS is not set
# CONFIG_STM32_I2CTIMEOTICKS is not set
# CONFIG_STM32_I2C_DUTY16_9 is not set
#
@ -317,16 +317,26 @@ CONFIG_ARCH_BOARD="spark"
#
CONFIG_ARCH_HAVE_LEDS=y
CONFIG_ARCH_LEDS=y
CONFIG_NSH_MMCSDMINOR=0
CONFIG_ARCH_HAVE_BUTTONS=y
CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_HAVE_IRQBUTTONS=y
CONFIG_ARCH_IRQBUTTONS=y
#
# Board-Specific Options
#
CONFIG_SPARK_FLASH=y
CONFIG_SPARK_FLASH_SPI=2
CONFIG_SPARK_FLASH_MINOR=0
CONFIG_SPARK_FLASH_PART=y
CONFIG_SPARK_FLASH_PART_LIST="256,768"
CONFIG_SPARK_FLASH_MOUNT_POINT="/mnt/p%d"
#
# RTOS Features
#
# CONFIG_BOARD_INITIALIZE is not set
CONFIG_BOARD_INITIALIZE=y
CONFIG_MSEC_PER_TICK=10
CONFIG_RR_INTERVAL=200
# CONFIG_SCHED_INSTRUMENTATION is not set
@ -390,24 +400,40 @@ CONFIG_DEV_NULL=y
# CONFIG_RAMDISK is not set
# CONFIG_CAN is not set
# CONFIG_PWM is not set
CONFIG_I2C=y
# CONFIG_I2C is not set
# CONFIG_I2C_SLAVE is not set
CONFIG_I2C_TRANSFER=y
# CONFIG_I2C_TRANSFER is not set
# CONFIG_I2C_WRITEREAD is not set
# CONFIG_I2C_POLLED is not set
# CONFIG_I2C_TRACE is not set
CONFIG_ARCH_HAVE_I2CRESET=y
# CONFIG_ARCH_HAVE_I2CRESET is not set
# CONFIG_I2C_RESET is not set
# CONFIG_SPI is not set
CONFIG_SPI=y
# CONFIG_RTC is not set
# CONFIG_WATCHDOG is not set
# CONFIG_ANALOG is not set
CONFIG_ANALOG=y
# CONFIG_AUDIO_DEVICES is not set
# CONFIG_BCH is not set
# CONFIG_INPUT is not set
# CONFIG_LCD is not set
# CONFIG_MMCSD is not set
# CONFIG_MTD is not set
#
# MTD Configuration
#
CONFIG_MTD=y
CONFIG_MTD_PARTITION=y
CONFIG_MTD_BYTE_WRITE=y
#
# MTD Device Drivers
#
CONFIG_MTD_SST25=y
CONFIG_SST25_SPIMODE=1
CONFIG_SST25_SPIFREQUENCY=20000000
CONFIG_SST25_SECTOR512=n
# CONFIG_PIPES is not set
# CONFIG_PM is not set
# CONFIG_POWER is not set
@ -415,26 +441,27 @@ CONFIG_ARCH_HAVE_I2CRESET=y
CONFIG_SERIAL=y
# CONFIG_DEV_LOWCONSOLE is not set
# CONFIG_16550_UART is not set
CONFIG_ARCH_HAVE_USART1=y
CONFIG_ARCH_HAVE_USART2=y
#
# USART Configuration
#
CONFIG_USART1_ISUART=y
CONFIG_USART2_ISUART=y
CONFIG_MCU_SERIAL=y
CONFIG_STANDARD_SERIAL=y
CONFIG_USART1_SERIAL_CONSOLE=y
CONFIG_USART2_SERIAL_CONSOLE=y
# CONFIG_NO_SERIAL_CONSOLE is not set
#
# USART1 Configuration
#
CONFIG_USART1_RXBUFSIZE=256
CONFIG_USART1_TXBUFSIZE=256
CONFIG_USART1_BAUD=115200
CONFIG_USART1_BITS=8
CONFIG_USART1_PARITY=0
CONFIG_USART1_2STOP=0
CONFIG_USART2_RXBUFSIZE=256
CONFIG_USART2_TXBUFSIZE=256
CONFIG_USART2_BAUD=115200
CONFIG_USART2_BITS=8
CONFIG_USART2_PARITY=0
CONFIG_USART2_2STOP=0
# CONFIG_USART1_IFLOWCONTROL is not set
# CONFIG_USART1_OFLOWCONTROL is not set
# CONFIG_SERIAL_IFLOWCONTROL is not set
@ -457,12 +484,64 @@ CONFIG_USBDEV_TRACE_NRECORDS=32
#
# USB Device Class Driver Options
#
# CONFIG_USBDEV_COMPOSITE is not set
CONFIG_USBDEV_COMPOSITE=y
CONFIG_COMPOSITE_IAD=y
CONFIG_COMPOSITE_EP0MAXPACKET=64
CONFIG_COMPOSITE_VENDORID=0x03eb
CONFIG_COMPOSITE_VENDORSTR="NuttX"
CONFIG_COMPOSITE_PRODUCTID=0x0000
CONFIG_COMPOSITE_PRODUCTSTR="Composite device"
CONFIG_COMPOSITE_SERIALSTR="001"
CONFIG_COMPOSITE_CONFIGSTR="NuttX COMPOSITE config"
CONFIG_COMPOSITE_VERSIONNO=0x1010
# CONFIG_PL2303 is not set
# CONFIG_CDCACM is not set
# CONFIG_USBMSC is not set
CONFIG_CDCACM=y
CONFIG_CDCACM_CONSOLE=n
CONFIG_CDCACM_COMPOSITE=y
CONFIG_CDCACM_IFNOBASE=0
CONFIG_CDCACM_STRBASE=0
CONFIG_CDCACM_EP0MAXPACKET=64
CONFIG_CDCACM_EPINTIN=1
CONFIG_CDCACM_EPINTIN_FSSIZE=64
CONFIG_CDCACM_EPINTIN_HSSIZE=64
CONFIG_CDCACM_EPBULKOUT=3
CONFIG_CDCACM_EPBULKOUT_FSSIZE=64
CONFIG_CDCACM_EPBULKOUT_HSSIZE=512
CONFIG_CDCACM_EPBULKIN=2
CONFIG_CDCACM_EPBULKIN_FSSIZE=64
CONFIG_CDCACM_EPBULKIN_HSSIZE=512
CONFIG_CDCACM_NWRREQS=4
CONFIG_CDCACM_NRDREQS=4
CONFIG_CDCACM_BULKIN_REQLEN=768
CONFIG_CDCACM_RXBUFSIZE=256
CONFIG_CDCACM_TXBUFSIZE=256
CONFIG_CDCACM_VENDORID=0x0525
CONFIG_CDCACM_PRODUCTID=0xa4a7
CONFIG_CDCACM_VENDORSTR="NuttX"
CONFIG_CDCACM_PRODUCTSTR="CDC/ACM Serial"
CONFIG_USBMSC=y
CONFIG_USBMSC_COMPOSITE=y
CONFIG_USBMSC_IFNOBASE=2
CONFIG_USBMSC_STRBASE=2
CONFIG_USBMSC_EP0MAXPACKET=64
CONFIG_USBMSC_EPBULKOUT=2
CONFIG_USBMSC_EPBULKIN=3
CONFIG_USBMSC_NWRREQS=4
CONFIG_USBMSC_NRDREQS=4
CONFIG_USBMSC_BULKINREQLEN=512
CONFIG_USBMSC_BULKOUTREQLEN=512
CONFIG_USBMSC_VENDORID=0x584e
CONFIG_USBMSC_VENDORSTR="NuttX"
CONFIG_USBMSC_PRODUCTID=0x5342
CONFIG_USBMSC_PRODUCTSTR="Mass Storage"
CONFIG_USBMSC_VERSIONNO=0x399
# CONFIG_USBMSC_REMOVABLE is not set
# CONFIG_USBHOST is not set
# CONFIG_WIRELESS is not set
CONFIG_WIRELESS=y
# CONFIG_WL_CC1101 is not set
CONFIG_WL_CC3000=y
# CONFIG_WL_CC3000_DUMMY is not set
# CONFIG_WL_NRF24L01 is not set
#
# System Logging Device Options
@ -487,7 +566,12 @@ CONFIG_USBDEV_TRACE_NRECORDS=32
#
# CONFIG_DISABLE_MOUNTPOINT is not set
# CONFIG_FS_RAMMAP is not set
# CONFIG_FS_FAT is not set
CONFIG_FS_FAT=y
CONFIG_FAT_LCNAMES=y
CONFIG_FAT_LFN=y
CONFIG_FAT_MAXFNAME=32
CONFIG_FS_FATTIME=y
# CONFIG_FS_NXFFS is not set
# CONFIG_FS_ROMFS is not set
# CONFIG_FS_SMARTFS is not set
@ -764,13 +848,13 @@ CONFIG_NSH_CONSOLE=y
#
# I2C tool
#
CONFIG_SYSTEM_I2CTOOL=y
CONFIG_I2CTOOL_MINBUS=1
CONFIG_I2CTOOL_MAXBUS=2
CONFIG_I2CTOOL_MINADDR=0x0
CONFIG_I2CTOOL_MAXADDR=0xf0
CONFIG_I2CTOOL_MAXREGADDR=0xff
CONFIG_I2CTOOL_DEFFREQ=100000
# CONFIG_SYSTEM_I2CTOOL is not set
# CONFIG_I2CTOOL_MINBUS is not set
# CONFIG_I2CTOOL_MAXBUS is not set
# CONFIG_I2CTOOL_MINADDR is not set
# CONFIG_I2CTOOL_MAXADDR is not set
# CONFIG_I2CTOOL_MAXREGADDR is not set
# CONFIG_I2CTOOL_DEFFREQ is not set
#
# FLASH Program Installation

28
configs/spark/src/Makefile
View File

@ -41,22 +41,40 @@ CFLAGS += -I$(TOPDIR)/sched
ASRCS =
AOBJS = $(ASRCS:.S=$(OBJEXT))
CSRCS = up_boot.c up_leds.c up_usbdev.c
CSRCS = up_boot.c up_spi.c
ifeq ($(CONFIG_NX_LCDDRIVER),y)
ifeq ($(CONFIG_HAVE_CXX),y)
CSRCS += up_cxxinitialize.c
endif
ifeq ($(CONFIG_ARCH_LEDS),y)
CSRCS += up_autoleds.c
else
CSRCS += up_userleds.c
endif
ifeq ($(CONFIG_ARCH_BUTTONS),y)
CSRCS += up_buttons.c
endif
ifeq ($(CONFIG_NSH_ARCHINIT),y)
CSRCS += up_nsh.c
endif
ifeq ($(CONFIG_INPUT),y)
ifeq ($(CONFIG_USBDEV),y)
CSRCS += up_usbdev.c
endif
ifeq ($(CONFIG_USBMSC),y)
ifeq ($(CONFIG_USBDEV_COMPOSITE),y)
CSRCS += up_composite.c
endif
ifeq ($(CONFIG_WL_CC3000),y)
CSRCS += up_wireless.c
endif
ifeq ($(CONFIG_WATCHDOG),y)
CSRCS += up_watchdog.c
CSRCS += up_watchdog.c
endif
COBJS = $(CSRCS:.c=$(OBJEXT))

177
configs/spark/src/spark.h
View File

@ -4,6 +4,7 @@
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Laurent Latil <laurent@latil.nom.fr>
* Librae <librae8226@gmail.com>
* David_s5 <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -34,8 +35,8 @@
*
************************************************************************************/
#ifndef __CONFIGS_SPARK_SRC_SPARK_INTERNAL_H
#define __CONFIGS_SPARK_SRC_SPARK_INTERNAL_H
#ifndef __CONFIGS_SPARK_SRC_SPARK_H
#define __CONFIGS_SPARK_SRC_SPARK_H
/************************************************************************************
* Included Files
@ -48,6 +49,106 @@
/************************************************************************************
* Definitions
************************************************************************************/
/* During the development of the SparkCore, the hardware was in limited supply
* As a work around david_s5 created a SparkCore Big board (http://nscdg.com/spark/sparkBB.png)
* that will interface with a maple mini (http://leaflabs.com/docs/hardware/maple-mini.html),
* and a CC3000BOOST (https://estore.ti.com/CC3000BOOST-CC3000-BoosterPack-P4258.aspx)
*
* It breaks out the Tx, Rx to connect to a FTDI TTL-232RG-VREG3V3-WE for the console and
* wires in the spark LEDs and serial flash to the same I/O as the sparkcore. It has a Jlink
* compatible Jtag connector on it.
*
*
* Board GPIO Usage:
*
* GPIO Function MPU Core Core Maple Maple
* Pin # Name Pin # Name Pin #
* ----- -------------------------------- --------------------------------------------------------
* PA[00] WKUP/USART2_CTS/ADC12_IN0/TIM2_CH1_ETR 10 A0 JP1-12 J1-8
* PA[01] USART2_RTS/ADC12_IN1/TIM2_CH2 11 A1 JP1-11 J1-9
* PA[02] USART2_TX/ADC12_IN2/TIM2_CH3 12 TX JP1-3 J1-10
* PA[03] USART2_RX/ADC12_IN3/TIM2_CH4 13 RX JP1-4 J1-11
* PA[04] SPI1_NSS/USART2_CK/ADC12_IN4 14 A2 JP1-10 J1-12
* PA[05] SPI1_SCK/ADC12_IN5 15 A3 JP1-9 J1-13
* PA[06] SPI1_MISO/ADC12_IN6/TIM3_CH1 16 A4 JP1-8 J1-14
* PA[07] SPI1_MOSI/ADC12_IN7/TIM3_CH2 17 A5 JP1-7 J1-15
* PA[08] USART1_CK/TIM1_CH1/MCO 29 LED2 J2-5
* PA[09] USART1_TX/TIM1_CH2 30 LED3 J2-6
* PA[10] USART1_RX/TIM1_CH3 31 LED4 J2-7
* PA[11] USART1_CTS/CAN_RX/TIM1_CH4/USBDM 32 USBM USBDM J2-8
* PA[12] USART1_RTS/CAN_TX/TIM1_ETR/USBDP 33 USBP USBDP J2-9
* PA[13] JTMS/SWDIO 34 D7,LED1 JP2-5 J2-10
* PA[14] JTCK/SWCLK 37 D6 JP2-6 J2-11
* PA[15] JTDI 38 D5 JP2-7 J2-12
*
* PB[00] ADC12_IN8/TIM3_CH3 18 A6 JP1-6 J1-16
* PB[01] ADC12_IN9/TIM3_CH4 19 A7 JP1-5 R1-LED
* PB[02] BOOT1 20 BTN BTN J1-17
* PB[03] JTDO 39 D4 JP2-8 J2-13
* PB[04] NJTRST 40 D3 JP2-9 J2-14
* PB[05] I2C1_SMBA 41 D2 JP2-10 J2-15
* PB[06] I2C1_SCL/TIM4_CH1 42 D1 JP2-11 J2-16
* PB[07] I2C1_SDA/TIM4_CH2 43 D0 JP2-12 J2-17
* PB[08] TIM4_CH3 45 WIFI_EN BOOT0 J2-18
* PB[09] TIM4_CH4 46 MEM_CS DISC
* PB[10] I2C2_SCL/USART3_TX 21 USB_DISC J1-18
* PB[11] I2C2_SDA/USART3_RX 22 WIFI_INT J1-19
* PB[12] SPI2_NSS/I2C2_SMBA/USART3_CK/TIM1_BKIN 25 WIFI_CS J2-1
* PB[13] SPI2_SCK/USART3_CTS/TIM1_CH1N 26 SPI_CLK J2-2
* PB[14] SPI2_MISO/USART3_RTS/TIM1_CH2N 27 SPI_MISO J2-3
* PB[15] SPI2_MOSI/TIM1_CH3N 28 SPI_MOSI J2-4
*
* PC[13] TAMPER-RTC 2 N.C. J1-4
* PC[14] OSC32_IN 3 OSC32_IN Y1 N.C.
* PC[15] OSC32_OUT 4 OSC32_OUT Y1 N.C.
*
* PD[00] OSC_IN 5 OSC_IN Y2 8MHZ OSC 8MHZ OSC
* PD[01] OSC_OUT 6 OSC_OUT Y2 8MHZ OSC 8MHZ OSC
*
* Spark Core pin Mapping
*
* GPIO ADC Timer I2C UART SPI JTAG Other 5V? STM Pin# Core HW Core SW
* PA0 CH0 2_CH1_ETR 2_CTS 10 A0 10
* PA1 CH1 2_CH2 2_RTS 11 A1 11
* PA2 CH2 2_CH3 2_TX 12 TX 19
* PA3 CH3 2_CH4 2_RX 13 RX 18
* PA4 CH4 2_CK 1_NSS 14 A2 12
* PA5 CH5 1_SCK 15 A3 13
* PA6 CH6 3_CH1 1_MISO 16 A4 14
* PA7 CH7 3_CH2 1_MOSI 17 A5 15
* PA8 1_CH1 1_CK MCO Yes 29 LED2
* PA9 1_CH2 1_TX Yes 30 LED3
* PA10 1_CH3 1_RX Yes 31 LED4
* PA11 1_CH4 1_CTS USB- Yes 32 USBM
* PA12 1_ETR 1_RTS USB+ Yes 33 USBP
* PA13 JTMS Yes 34 D7 7
* PA14 JTCK Yes 37 D6 6
* PA15 JTDI Yes 38 D5 5
*
* PB0 CH8 3_CH3 18 A6 16
* PB1 CH9 3_CH4 19 A7 17
* PB2 BOOT1 Yes 20 BTN
* PB3 JTDO Yes 39 D4 4
* PB4 NJTRST Yes 40 D3 3
* PB5 1_SMBA 41 D2 2
* PB6 4_CH1 1_SCL Yes 42 D1 1
* PB7 4_CH2 1_SDA Yes 43 D0 0
* PB8 4_CH3 Yes 45 WIFI_EN
* PB9 4_CH4 Yes 46 MEM_CS
* PB10 2_SCL 3_TX Yes 21 USB_DISC
* PB11 2_SDA 3_RX Yes 22 WIFI_INT
* PB12 1_BKIN 2_SMBA 3_CK 2_NSS Yes 25 WIFI_CS
* PB13 3_CTS 2_SCK Yes 26 SPI_SCK
* PB14 3_RTS 2_MISO Yes 27 SPI_MISO
* PB15 2_MOSI Yes 28 SPI_MOSI
*
* PC13 2
* PC14 RTC Oscillator 3 OSC32IN
* PC15 RTC Oscillator 4 OSC32OUT
*
* PD0 Oscillator <= 5 OSC
* PD1 Oscillator => 6 OSC
*/
/* How many SPI modules does this chip support? The LM3S6918 supports 2 SPI
* modules (others may support more -- in such case, the following must be
@ -61,12 +162,62 @@
# undef CONFIG_STM32_SPI2
#endif
/* GPIOs **************************************************************/
/* LEDs *****************************************************************************/
/*
* GPIO Function MPU Core Core Maple Maple
* Pin # Name Pin # Name Pin #
* ----- -------------------------------- --------------------------------------------------------
*
* PA[08] USART1_CK/TIM1_CH1/MCO 29 LED2 J2-5
* PA[09] USART1_TX/TIM1_CH2 30 LED3 J2-6
* PA[10] USART1_RX/TIM1_CH3 31 LED4 J2-7
* PA[13] JTMS/SWDIO 34 D7,LED1 JP2-5 J2-10
*/
#define GPIO_LED (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN1)
#define GPIO_USB_PULLUP (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN9)
#define GPIO_LED1 (GPIO_PORTA | GPIO_PIN13 | GPIO_OUTPUT_CLEAR | GPIO_OUTPUT | GPIO_CNF_OUTPP | GPIO_MODE_50MHz)
#define GPIO_LED_USR GPIO_LED1
#define GPIO_LED2 (GPIO_PORTA | GPIO_PIN8 | GPIO_OUTPUT_SET | GPIO_OUTPUT | GPIO_CNF_OUTPP | GPIO_MODE_50MHz)
#define GPIO_LED3 (GPIO_PORTA | GPIO_PIN9 | GPIO_OUTPUT_SET | GPIO_OUTPUT | GPIO_CNF_OUTPP | GPIO_MODE_50MHz)
#define GPIO_LED4 (GPIO_PORTA | GPIO_PIN10 | GPIO_OUTPUT_SET | GPIO_OUTPUT | GPIO_CNF_OUTPP | GPIO_MODE_50MHz)
#define GPIO_USB_PULLUP (GPIO_OUTPUT | GPIO_CNF_OUTPP | GPIO_MODE_50MHz | GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN9)
/* BUTTON ***************************************************************************/
/*
* GPIO Function MPU Core Core Maple Maple
* Pin # Name Pin # Name Pin #
* ----- -------------------------------- --------------------------------------------------------
* PB[02] BOOT1 20 BTN BTN J1-17
*/
#define IRQBUTTON BUTTON_USER
#define GPIO_BTN (GPIO_PORTB | GPIO_PIN2 | GPIO_INPUT | GPIO_CNF_INPULLUP | GPIO_EXTI)
/* MEMORYs **************************************************************************/
/*
* GPIO Function MPU Core Core Maple Maple
* Pin # Name Pin # Name Pin #
* ----- -------------------------------- --------------------------------------------------------
* PB[09] TIM4_CH4 46 MEM_CS DISC
*/
#define GPIO_MEM_CS (GPIO_PORTB | GPIO_PIN9 | GPIO_OUTPUT_SET | GPIO_OUTPUT | GPIO_CNF_OUTPP | GPIO_MODE_50MHz)
/* CCS3000 **************************************************************************/
/*
* GPIO Function MPU Core Core Maple Maple
* Pin # Name Pin # Name Pin #
* ----- -------------------------------- --------------------------------------------------------
* PB[08] TIM4_CH3 45 WIFI_EN BOOT0 J2-18
* PB[11] I2C2_SDA/USART3_RX 22 WIFI_INT J1-19
* PB[12] SPI2_NSS/I2C2_SMBA/USART3_CK/TIM1_BKIN 25 WIFI_CS J2-1
*/
#define GPIO_WIFI_EN (GPIO_PORTB | GPIO_PIN8 | GPIO_OUTPUT_SET | GPIO_OUTPUT | GPIO_CNF_OUTPP | GPIO_MODE_50MHz)
#define GPIO_WIFI_CS (GPIO_PORTB | GPIO_PIN12 | GPIO_OUTPUT_SET | GPIO_OUTPUT | GPIO_CNF_OUTPP | GPIO_MODE_50MHz)
#define GPIO_WIFI_INT (GPIO_PORTB | GPIO_PIN11 | GPIO_INPUT | GPIO_CNF_INPULLUP | GPIO_EXTI)
/************************************************************************************
* Public Types
@ -102,15 +253,5 @@ void stm32_spiinitialize(void);
void stm32_usbinitialize(void);
/************************************************************************************
* Name: up_wlinitialize
*
* Description:
* Called to configure wireless module (nRF24L01).
*
************************************************************************************/
void up_wlinitialize(void);
#endif /* __ASSEMBLY__ */
#endif /* __CONFIGS_SPARK_SRC_SPARK_INTERNAL_H */
#endif /* __CONFIGS_SPARK_SRC_SPARK_H */

44
configs/spark/src/up_boot.c
View File

@ -77,14 +77,19 @@ void stm32_boardinitialize(void)
up_ledinit();
#endif
/* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak function
#ifdef CONFIG_ARCH_HAVE_BUTTONS
up_buttoninit();
#endif
/* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the weak function
* stm32_spiinitialize() has been brought into the link.
*/
#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2)
stm32_spiinitialize();
#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3)
stm32_spiinitialize();
#endif
/* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not
* disabled, and 3) the weak function stm32_usbinitialize() has been brought
* into the build.
@ -93,4 +98,37 @@ void stm32_boardinitialize(void)
#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB)
stm32_usbinitialize();
#endif
}
/****************************************************************************
* Name: board_initialize
*
* Description:
* If CONFIG_BOARD_INITIALIZE is selected, then an additional
* initialization call will be performed in the boot-up sequence to a
* function called board_initialize(). board_initialize() will be
* called immediately after up_intiialize() is called and just before the
* initial application is started. This additional initialization phase
* may be used, for example, to initialize board-specific device drivers.
*
****************************************************************************/
#ifdef CONFIG_BOARD_INITIALIZE
void board_initialize(void)
{
/* Perform NSH initialization here instead of from the NSH. This
* alternative NSH initialization is necessary when NSH is ran in user-space
* but the initialization function must run in kernel space.
*/
#if defined(CONFIG_NSH_LIBRARY) && !defined(CONFIG_NSH_ARCHINIT)
nsh_archinitialize();
wireless_archinitialize();
#endif
}
#endif

152
configs/spark/src/up_leds.c
View File

@ -1,152 +0,0 @@
/****************************************************************************
* configs/spark/src/up_leds.c
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Librae <librae8226@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include <debug.h>
#include <arch/board/board.h>
#include "chip.h"
#include "up_arch.h"
#include "up_internal.h"
#include "stm32.h"
#include "spark.h"
/****************************************************************************
* Definitions
****************************************************************************/
/* CONFIG_DEBUG_LEDS enables debug output from this file (needs CONFIG_DEBUG
* with CONFIG_DEBUG_VERBOSE too)
*/
#ifdef CONFIG_DEBUG_LEDS
# define leddbg lldbg
# define ledvdbg llvdbg
#else
# define leddbg(x...)
# define ledvdbg(x...)
#endif
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
static inline void set_led(bool v)
{
ledvdbg("Turn LED %s\n", v? "on":"off");
stm32_gpiowrite(GPIO_LED, v);
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_ledinit
****************************************************************************/
#ifdef CONFIG_ARCH_LEDS
void up_ledinit(void)
{
/* Configure LED GPIO for output */
stm32_configgpio(GPIO_LED);
}
/****************************************************************************
* Name: up_ledon
****************************************************************************/
void up_ledon(int led)
{
ledvdbg("up_ledon(%d)\n", led);
switch (led)
{
case LED_STARTED:
case LED_HEAPALLOCATE:
/* As the board provides only one soft controllable LED, we simply turn
* it on when the board boots
*/
set_led(true);
break;
case LED_PANIC:
/* For panic state, the LED is blinking */
set_led(true);
break;
default:
break;
}
}
/****************************************************************************
* Name: up_ledoff
****************************************************************************/
void up_ledoff(int led)
{
ledvdbg("up_ledoff(%d)\n", led);
switch (led)
{
case LED_STARTED:
case LED_PANIC:
/* For panic state, the LED is blinking */
set_led(false);
break;
default:
break;
}
}
#endif /* CONFIG_ARCH_LEDS */

2
configs/spark/src/up_watchdog.c
View File

@ -119,7 +119,7 @@
int up_wdginitialize(void)
{
/* Initialize tha register the watchdog timer device */
/* Initialize and register the watchdog timer device */
#if defined(CONFIG_STM32_WWDG)
stm32_wwdginitialize(CONFIG_STM32_WDG_DEVPATH);