rch/arm/armv7-a/l2cc_pl310.h: Move arch/arm/sama5/chip/sam_l2cc.h to arch/arm/armv7-a/l2cc_pl310.h. Adjust the two corresponding Kconfig files as well.
This commit is contained in:
Gregory Nutt
parent
2ec0ab3b5e
commit
e74f37445b
@ -5,6 +5,21 @@
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comment "ARMv7-A Configuration Options"
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config ARMV7A_HAVE_L2CC_PL310
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bool
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default n
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config ARMV7A_L2CC_PL310
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bool "ARMv7-A L2CC P310 Support"
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default n
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depends on ARMV7A_HAVE_L2CC_PL310
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---help---
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Enable the 2 Cache Controller (L2CC) is based on the L2CC-PL310 ARM
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multi-way cache macrocell, version r3p2. The addition of an on-chip
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secondary cache, also referred to as a Level 2 or L2 cache, is a
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method of improving the system performance when significant memory
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traffic is generated by the processor.
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choice
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prompt "Toolchain Selection"
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default ARMV7A_TOOLCHAIN_GNU_EABIW if HOST_WINDOWS
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@ -1,5 +1,5 @@
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/************************************************************************************
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* arch/arm/src/sama5/chip/sam_l2cc.h
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* arch/arm/src/armv7-a/chip/l2cc_pl310.h
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*
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* Copyright (C) 2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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@ -33,94 +33,99 @@
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_L2CC_H
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#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_L2CC_H
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#ifndef __ARCH_ARM_SRC_ARMV7_A_L2CC_PL310_H
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#define __ARCH_ARM_SRC_ARMV7_A_L2CC_PL310_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip/sam_memorymap.h"
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/* The base address of the L2CC implementation must be provided in the chip.h
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* header file as L2CC_VBASE.
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*/
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#include "chip/chip.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* L2CC Register Offsets ************************************************************/
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#define SAM_L2CC_IDR_OFFSET 0x0000 /* Cache ID Register */
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#define SAM_L2CC_TYPR_OFFSET 0x0004 /* Cache Type Register */
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#define SAM_L2CC_CR_OFFSET 0x0100 /* Control Register */
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#define SAM_L2CC_ACR_OFFSET 0x0104 /* Auxiliary Control Register */
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#define SAM_L2CC_TRCR_OFFSET 0x0108 /* Tag RAM Control Register */
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#define SAM_L2CC_DRCR_OFFSET 0x010c /* Data RAM Control Register */
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#define L2CC_IDR_OFFSET 0x0000 /* Cache ID Register */
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#define L2CC_TYPR_OFFSET 0x0004 /* Cache Type Register */
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#define L2CC_CR_OFFSET 0x0100 /* Control Register */
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#define L2CC_ACR_OFFSET 0x0104 /* Auxiliary Control Register */
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#define L2CC_TRCR_OFFSET 0x0108 /* Tag RAM Control Register */
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#define L2CC_DRCR_OFFSET 0x010c /* Data RAM Control Register */
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/* 0x0110-0x01fc Reserved */
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#define SAM_L2CC_ECR_OFFSET 0x0200 /* Event Counter Control Register */
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#define SAM_L2CC_ECFGR1_OFFSET 0x0204 /* Event Counter 1 Configuration Register */
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#define SAM_L2CC_ECFGR0_OFFSET 0x0208 /* Event Counter 0 Configuration Register */
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#define SAM_L2CC_EVR1_OFFSET 0x020c /* Event Counter 1 Value Register */
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#define SAM_L2CC_EVR0_OFFSET 0x0210 /* Event Counter 0 Value Register */
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#define SAM_L2CC_IMR_OFFSET 0x0214 /* Interrupt Mask Register */
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#define SAM_L2CC_MISR_OFFSET 0x0218 /* Masked Interrupt Status Register */
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#define SAM_L2CC_RISR_OFFSET 0x021c /* Raw Interrupt Status Register */
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#define SAM_L2CC_ICR_OFFSET 0x0220 /* Interrupt Clear Register */
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#define L2CC_ECR_OFFSET 0x0200 /* Event Counter Control Register */
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#define L2CC_ECFGR1_OFFSET 0x0204 /* Event Counter 1 Configuration Register */
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#define L2CC_ECFGR0_OFFSET 0x0208 /* Event Counter 0 Configuration Register */
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#define L2CC_EVR1_OFFSET 0x020c /* Event Counter 1 Value Register */
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#define L2CC_EVR0_OFFSET 0x0210 /* Event Counter 0 Value Register */
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#define L2CC_IMR_OFFSET 0x0214 /* Interrupt Mask Register */
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#define L2CC_MISR_OFFSET 0x0218 /* Masked Interrupt Status Register */
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#define L2CC_RISR_OFFSET 0x021c /* Raw Interrupt Status Register */
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#define L2CC_ICR_OFFSET 0x0220 /* Interrupt Clear Register */
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/* 0x0224-0x072c Reserved */
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#define SAM_L2CC_CSR_OFFSET 0x0730 /* Cache Synchronization Register */
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#define L2CC_CSR_OFFSET 0x0730 /* Cache Synchronization Register */
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/* 0x0734-0x076c Reserved */
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#define SAM_L2CC_IPALR_OFFSET 0x0770 /* Invalidate Physical Address Line Register */
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#define L2CC_IPALR_OFFSET 0x0770 /* Invalidate Physical Address Line Register */
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/* 0x0774-0x0778 Reserved */
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#define SAM_L2CC_IWR_OFFSET 0x077c /* Invalidate Way Register */
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#define L2CC_IWR_OFFSET 0x077c /* Invalidate Way Register */
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/* 0x0780-0x07af Reserved */
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#define SAM_L2CC_CPALR_OFFSET 0x07b0 /* Clean Physical Address Line Register */
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#define L2CC_CPALR_OFFSET 0x07b0 /* Clean Physical Address Line Register */
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/* 0x07b4 Reserved */
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#define SAM_L2CC_CIR_OFFSET 0x07b8 /* Clean Index Register */
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#define SAM_L2CC_CWR_OFFSET 0x07bc /* Clean Way Register */
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#define L2CC_CIR_OFFSET 0x07b8 /* Clean Index Register */
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#define L2CC_CWR_OFFSET 0x07bc /* Clean Way Register */
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/* 0x07c0-0x07ec Reserved */
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#define SAM_L2CC_CIPALR_OFFSET 0x07f0 /* Clean Invalidate Physical Address Line Register */
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#define L2CC_CIPALR_OFFSET 0x07f0 /* Clean Invalidate Physical Address Line Register */
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/* 0x07f4 Reserved */
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#define SAM_L2CC_CIIR_OFFSET 0x07f8 /* Clean Invalidate Index Register */
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#define SAM_L2CC_CIWR_OFFSET 0x07fc /* Clean Invalidate Way Register */
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#define L2CC_CIIR_OFFSET 0x07f8 /* Clean Invalidate Index Register */
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#define L2CC_CIWR_OFFSET 0x07fc /* Clean Invalidate Way Register */
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/* 0x0800-0x08fc Reserved */
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#define SAM_L2CC_DLKR_OFFSET 0x0900 /* Data Lockdown Register */
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#define SAM_L2CC_ILKR_OFFSET 0x0904 /* Instruction Lockdown Register */
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#define L2CC_DLKR_OFFSET 0x0900 /* Data Lockdown Register */
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#define L2CC_ILKR_OFFSET 0x0904 /* Instruction Lockdown Register */
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/* 0x0908-0x0f3c Reserved */
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#define SAM_L2CC_DCR_OFFSET 0x0f40 /* Debug Control Register */
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#define L2CC_DCR_OFFSET 0x0f40 /* Debug Control Register */
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/* 0x0f44-0x0f5c Reserved */
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#define SAM_L2CC_PCR_OFFSET 0x0f60 /* Prefetch Control Register */
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#define L2CC_PCR_OFFSET 0x0f60 /* Prefetch Control Register */
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/* 0x0f64-0x0f7c Reserved */
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#define SAM_L2CC_POWCR_OFFSET 0x0f80 /* Power Control Register */
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#define L2CC_POWCR_OFFSET 0x0f80 /* Power Control Register */
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/* L2CC Register Addresses **********************************************************/
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#define SAM_L2CC_IDR (SAM_L2CC_VSECTION+SAM_L2CC_IDR_OFFSET)
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#define SAM_L2CC_TYPR (SAM_L2CC_VSECTION+SAM_L2CC_TYPR_OFFSET)
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#define SAM_L2CC_CR (SAM_L2CC_VSECTION+SAM_L2CC_CR_OFFSET)
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#define SAM_L2CC_ACR (SAM_L2CC_VSECTION+SAM_L2CC_ACR_OFFSET)
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#define SAM_L2CC_TRCR (SAM_L2CC_VSECTION+SAM_L2CC_TRCR_OFFSET)
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#define SAM_L2CC_DRCR (SAM_L2CC_VSECTION+SAM_L2CC_DRCR_OFFSET)
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#define SAM_L2CC_ECR (SAM_L2CC_VSECTION+SAM_L2CC_ECR_OFFSET)
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#define SAM_L2CC_ECFGR1 (SAM_L2CC_VSECTION+SAM_L2CC_ECFGR1_OFFSET)
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#define SAM_L2CC_ECFGR0 (SAM_L2CC_VSECTION+SAM_L2CC_ECFGR0_OFFSET)
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#define SAM_L2CC_EVR1 (SAM_L2CC_VSECTION+SAM_L2CC_EVR1_OFFSET)
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#define SAM_L2CC_EVR0 (SAM_L2CC_VSECTION+SAM_L2CC_EVR0_OFFSET)
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#define SAM_L2CC_IMR (SAM_L2CC_VSECTION+SAM_L2CC_IMR_OFFSET)
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#define SAM_L2CC_MISR (SAM_L2CC_VSECTION+SAM_L2CC_MISR_OFFSET)
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#define SAM_L2CC_RISR (SAM_L2CC_VSECTION+SAM_L2CC_RISR_OFFSET)
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#define SAM_L2CC_ICR (SAM_L2CC_VSECTION+SAM_L2CC_ICR_OFFSET)
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#define SAM_L2CC_CSR (SAM_L2CC_VSECTION+SAM_L2CC_CSR_OFFSET)
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#define SAM_L2CC_IPALR (SAM_L2CC_VSECTION+SAM_L2CC_IPALR_OFFSET)
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#define SAM_L2CC_IWR (SAM_L2CC_VSECTION+SAM_L2CC_IWR_OFFSET)
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#define SAM_L2CC_CPALR (SAM_L2CC_VSECTION+SAM_L2CC_CPALR_OFFSET)
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#define SAM_L2CC_CIR (SAM_L2CC_VSECTION+SAM_L2CC_CIR_OFFSET)
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#define SAM_L2CC_CWR (SAM_L2CC_VSECTION+SAM_L2CC_CWR_OFFSET)
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#define SAM_L2CC_CIPALR (SAM_L2CC_VSECTION+SAM_L2CC_CIPALR_OFFSET)
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#define SAM_L2CC_CIIR (SAM_L2CC_VSECTION+SAM_L2CC_CIIR_OFFSET)
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#define SAM_L2CC_CIWR (SAM_L2CC_VSECTION+SAM_L2CC_CIWR_OFFSET)
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#define SAM_L2CC_DLKR (SAM_L2CC_VSECTION+SAM_L2CC_DLKR_OFFSET)
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#define SAM_L2CC_ILKR (SAM_L2CC_VSECTION+SAM_L2CC_ILKR_OFFSET)
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#define SAM_L2CC_DCR (SAM_L2CC_VSECTION+SAM_L2CC_DCR_OFFSET)
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#define SAM_L2CC_PCR (SAM_L2CC_VSECTION+SAM_L2CC_PCR_OFFSET)
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#define SAM_L2CC_POWCR (SAM_L2CC_VSECTION+SAM_L2CC_POWCR_OFFSET)
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#define L2CC_IDR (L2CC_VBASE+L2CC_IDR_OFFSET)
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#define L2CC_TYPR (L2CC_VBASE+L2CC_TYPR_OFFSET)
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#define L2CC_CR (L2CC_VBASE+L2CC_CR_OFFSET)
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#define L2CC_ACR (L2CC_VBASE+L2CC_ACR_OFFSET)
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#define L2CC_TRCR (L2CC_VBASE+L2CC_TRCR_OFFSET)
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#define L2CC_DRCR (L2CC_VBASE+L2CC_DRCR_OFFSET)
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#define L2CC_ECR (L2CC_VBASE+L2CC_ECR_OFFSET)
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#define L2CC_ECFGR1 (L2CC_VBASE+L2CC_ECFGR1_OFFSET)
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#define L2CC_ECFGR0 (L2CC_VBASE+L2CC_ECFGR0_OFFSET)
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#define L2CC_EVR1 (L2CC_VBASE+L2CC_EVR1_OFFSET)
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#define L2CC_EVR0 (L2CC_VBASE+L2CC_EVR0_OFFSET)
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#define L2CC_IMR (L2CC_VBASE+L2CC_IMR_OFFSET)
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#define L2CC_MISR (L2CC_VBASE+L2CC_MISR_OFFSET)
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#define L2CC_RISR (L2CC_VBASE+L2CC_RISR_OFFSET)
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#define L2CC_ICR (L2CC_VBASE+L2CC_ICR_OFFSET)
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#define L2CC_CSR (L2CC_VBASE+L2CC_CSR_OFFSET)
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#define L2CC_IPALR (L2CC_VBASE+L2CC_IPALR_OFFSET)
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#define L2CC_IWR (L2CC_VBASE+L2CC_IWR_OFFSET)
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#define L2CC_CPALR (L2CC_VBASE+L2CC_CPALR_OFFSET)
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#define L2CC_CIR (L2CC_VBASE+L2CC_CIR_OFFSET)
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#define L2CC_CWR (L2CC_VBASE+L2CC_CWR_OFFSET)
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#define L2CC_CIPALR (L2CC_VBASE+L2CC_CIPALR_OFFSET)
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#define L2CC_CIIR (L2CC_VBASE+L2CC_CIIR_OFFSET)
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#define L2CC_CIWR (L2CC_VBASE+L2CC_CIWR_OFFSET)
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#define L2CC_DLKR (L2CC_VBASE+L2CC_DLKR_OFFSET)
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#define L2CC_ILKR (L2CC_VBASE+L2CC_ILKR_OFFSET)
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#define L2CC_DCR (L2CC_VBASE+L2CC_DCR_OFFSET)
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#define L2CC_PCR (L2CC_VBASE+L2CC_PCR_OFFSET)
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#define L2CC_POWCR (L2CC_VBASE+L2CC_POWCR_OFFSET)
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/* L2CC Register Bit Definitions ****************************************************/
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@ -406,4 +411,4 @@
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#define L2CC_POWCR_STBYEN (1 << 0) /* Bit 0: Standby Mode Enable */
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#define L2CC_POWCR_DCKGATEN (1 << 1) /* Bit 1: Dynamic Clock Gating Enable */
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#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_L2CC_H */
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#endif /* __ARCH_ARM_SRC_ARMV7_A_L2CC_PL310_H */
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@ -49,10 +49,6 @@ config SAMA5_HAVE_XDMA
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bool
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default n
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config SAMA5_HAVE_L2CC
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bool
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default n
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config SAMA5_HAVE_LCDC
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bool
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default n
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@ -123,6 +119,8 @@ config ARCH_CHIP_SAMA5D3
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config ARCH_CHIP_SAMA5D4
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bool
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default n
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select ARMV7A_HAVE_L2CC_PL310
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select ARCH_NAND_HWECC
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select SAMA5_HAVE_AESB
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select SAMA5_HAVE_EMACB
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select SAMA5_HAVE_EMAC1
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@ -132,7 +130,6 @@ config ARCH_CHIP_SAMA5D4
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select SAMA5_HAVE_UART1
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select SAMA5_HAVE_USART4
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select SAMA5_HAVE_XDMA
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select SAMA5_HAVE_L2CC
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select SAMA5_HAVE_SAIC
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select SAMA5_HAVE_SBM
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select SAMA5_HAVE_SFC
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@ -141,7 +138,6 @@ config ARCH_CHIP_SAMA5D4
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select SAMA5_HAVE_TC2
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select SAMA5_HAVE_TRUSTZONE
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select SAMA5_HAVE_TWI3
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select ARCH_NAND_HWECC
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choice
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prompt "Atmel AT91SAMA5 Chip Selection"
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@ -242,11 +238,6 @@ config SAMA5_DBGU
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bool "Debug Unit (DBGU)"
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default n
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config SAMA5_L2CC
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bool "L2 Cache Controller (L2CC)"
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default n
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depends on SAMA5_HAVE_L2CC
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config SAMA5_PIT
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bool "Periodic Interval Timer (PIT)"
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default n
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@ -1,7 +1,7 @@
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/************************************************************************************
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* arch/arm/src/sama5/chip.h
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -45,5 +45,15 @@
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#include "chip/sam_memorymap.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* arch/arm/src/armv7-a/l2cc_pl310.h includes this file and expects it to provide the
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* address of the L2CC-PL310 implementation.
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*/
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#define L2CC_VBASE SAM_L2CC_VSECTION
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#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_H */
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