From e74f37445b9e3169b2f1890937ad18d8bdd205e2 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 25 Jul 2014 17:25:17 -0600 Subject: [PATCH] rch/arm/armv7-a/l2cc_pl310.h: Move arch/arm/sama5/chip/sam_l2cc.h to arch/arm/armv7-a/l2cc_pl310.h. Adjust the two corresponding Kconfig files as well. --- arch/arm/src/armv7-a/Kconfig | 15 ++ .../chip/sam_l2cc.h => armv7-a/l2cc_pl310.h} | 131 +++++++++--------- arch/arm/src/sama5/Kconfig | 13 +- arch/arm/src/sama5/chip.h | 12 +- 4 files changed, 96 insertions(+), 75 deletions(-) rename arch/arm/src/{sama5/chip/sam_l2cc.h => armv7-a/l2cc_pl310.h} (83%) diff --git a/arch/arm/src/armv7-a/Kconfig b/arch/arm/src/armv7-a/Kconfig index ba56052f4b..1c0ba2493c 100644 --- a/arch/arm/src/armv7-a/Kconfig +++ b/arch/arm/src/armv7-a/Kconfig @@ -5,6 +5,21 @@ comment "ARMv7-A Configuration Options" +config ARMV7A_HAVE_L2CC_PL310 + bool + default n + +config ARMV7A_L2CC_PL310 + bool "ARMv7-A L2CC P310 Support" + default n + depends on ARMV7A_HAVE_L2CC_PL310 + ---help--- + Enable the 2 Cache Controller (L2CC) is based on the L2CC-PL310 ARM + multi-way cache macrocell, version r3p2. The addition of an on-chip + secondary cache, also referred to as a Level 2 or L2 cache, is a + method of improving the system performance when significant memory + traffic is generated by the processor. + choice prompt "Toolchain Selection" default ARMV7A_TOOLCHAIN_GNU_EABIW if HOST_WINDOWS diff --git a/arch/arm/src/sama5/chip/sam_l2cc.h b/arch/arm/src/armv7-a/l2cc_pl310.h similarity index 83% rename from arch/arm/src/sama5/chip/sam_l2cc.h rename to arch/arm/src/armv7-a/l2cc_pl310.h index b42c33a34f..d22f561188 100644 --- a/arch/arm/src/sama5/chip/sam_l2cc.h +++ b/arch/arm/src/armv7-a/l2cc_pl310.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/sama5/chip/sam_l2cc.h + * arch/arm/src/armv7-a/chip/l2cc_pl310.h * * Copyright (C) 2014 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,94 +33,99 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_L2CC_H -#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_L2CC_H +#ifndef __ARCH_ARM_SRC_ARMV7_A_L2CC_PL310_H +#define __ARCH_ARM_SRC_ARMV7_A_L2CC_PL310_H /************************************************************************************ * Included Files ************************************************************************************/ #include -#include "chip/sam_memorymap.h" + +/* The base address of the L2CC implementation must be provided in the chip.h + * header file as L2CC_VBASE. + */ + +#include "chip/chip.h" /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ /* L2CC Register Offsets ************************************************************/ -#define SAM_L2CC_IDR_OFFSET 0x0000 /* Cache ID Register */ -#define SAM_L2CC_TYPR_OFFSET 0x0004 /* Cache Type Register */ -#define SAM_L2CC_CR_OFFSET 0x0100 /* Control Register */ -#define SAM_L2CC_ACR_OFFSET 0x0104 /* Auxiliary Control Register */ -#define SAM_L2CC_TRCR_OFFSET 0x0108 /* Tag RAM Control Register */ -#define SAM_L2CC_DRCR_OFFSET 0x010c /* Data RAM Control Register */ +#define L2CC_IDR_OFFSET 0x0000 /* Cache ID Register */ +#define L2CC_TYPR_OFFSET 0x0004 /* Cache Type Register */ +#define L2CC_CR_OFFSET 0x0100 /* Control Register */ +#define L2CC_ACR_OFFSET 0x0104 /* Auxiliary Control Register */ +#define L2CC_TRCR_OFFSET 0x0108 /* Tag RAM Control Register */ +#define L2CC_DRCR_OFFSET 0x010c /* Data RAM Control Register */ /* 0x0110-0x01fc Reserved */ -#define SAM_L2CC_ECR_OFFSET 0x0200 /* Event Counter Control Register */ -#define SAM_L2CC_ECFGR1_OFFSET 0x0204 /* Event Counter 1 Configuration Register */ -#define SAM_L2CC_ECFGR0_OFFSET 0x0208 /* Event Counter 0 Configuration Register */ -#define SAM_L2CC_EVR1_OFFSET 0x020c /* Event Counter 1 Value Register */ -#define SAM_L2CC_EVR0_OFFSET 0x0210 /* Event Counter 0 Value Register */ -#define SAM_L2CC_IMR_OFFSET 0x0214 /* Interrupt Mask Register */ -#define SAM_L2CC_MISR_OFFSET 0x0218 /* Masked Interrupt Status Register */ -#define SAM_L2CC_RISR_OFFSET 0x021c /* Raw Interrupt Status Register */ -#define SAM_L2CC_ICR_OFFSET 0x0220 /* Interrupt Clear Register */ +#define L2CC_ECR_OFFSET 0x0200 /* Event Counter Control Register */ +#define L2CC_ECFGR1_OFFSET 0x0204 /* Event Counter 1 Configuration Register */ +#define L2CC_ECFGR0_OFFSET 0x0208 /* Event Counter 0 Configuration Register */ +#define L2CC_EVR1_OFFSET 0x020c /* Event Counter 1 Value Register */ +#define L2CC_EVR0_OFFSET 0x0210 /* Event Counter 0 Value Register */ +#define L2CC_IMR_OFFSET 0x0214 /* Interrupt Mask Register */ +#define L2CC_MISR_OFFSET 0x0218 /* Masked Interrupt Status Register */ +#define L2CC_RISR_OFFSET 0x021c /* Raw Interrupt Status Register */ +#define L2CC_ICR_OFFSET 0x0220 /* Interrupt Clear Register */ /* 0x0224-0x072c Reserved */ -#define SAM_L2CC_CSR_OFFSET 0x0730 /* Cache Synchronization Register */ +#define L2CC_CSR_OFFSET 0x0730 /* Cache Synchronization Register */ /* 0x0734-0x076c Reserved */ -#define SAM_L2CC_IPALR_OFFSET 0x0770 /* Invalidate Physical Address Line Register */ +#define L2CC_IPALR_OFFSET 0x0770 /* Invalidate Physical Address Line Register */ /* 0x0774-0x0778 Reserved */ -#define SAM_L2CC_IWR_OFFSET 0x077c /* Invalidate Way Register */ +#define L2CC_IWR_OFFSET 0x077c /* Invalidate Way Register */ /* 0x0780-0x07af Reserved */ -#define SAM_L2CC_CPALR_OFFSET 0x07b0 /* Clean Physical Address Line Register */ +#define L2CC_CPALR_OFFSET 0x07b0 /* Clean Physical Address Line Register */ /* 0x07b4 Reserved */ -#define SAM_L2CC_CIR_OFFSET 0x07b8 /* Clean Index Register */ -#define SAM_L2CC_CWR_OFFSET 0x07bc /* Clean Way Register */ +#define L2CC_CIR_OFFSET 0x07b8 /* Clean Index Register */ +#define L2CC_CWR_OFFSET 0x07bc /* Clean Way Register */ /* 0x07c0-0x07ec Reserved */ -#define SAM_L2CC_CIPALR_OFFSET 0x07f0 /* Clean Invalidate Physical Address Line Register */ +#define L2CC_CIPALR_OFFSET 0x07f0 /* Clean Invalidate Physical Address Line Register */ /* 0x07f4 Reserved */ -#define SAM_L2CC_CIIR_OFFSET 0x07f8 /* Clean Invalidate Index Register */ -#define SAM_L2CC_CIWR_OFFSET 0x07fc /* Clean Invalidate Way Register */ +#define L2CC_CIIR_OFFSET 0x07f8 /* Clean Invalidate Index Register */ +#define L2CC_CIWR_OFFSET 0x07fc /* Clean Invalidate Way Register */ /* 0x0800-0x08fc Reserved */ -#define SAM_L2CC_DLKR_OFFSET 0x0900 /* Data Lockdown Register */ -#define SAM_L2CC_ILKR_OFFSET 0x0904 /* Instruction Lockdown Register */ +#define L2CC_DLKR_OFFSET 0x0900 /* Data Lockdown Register */ +#define L2CC_ILKR_OFFSET 0x0904 /* Instruction Lockdown Register */ /* 0x0908-0x0f3c Reserved */ -#define SAM_L2CC_DCR_OFFSET 0x0f40 /* Debug Control Register */ +#define L2CC_DCR_OFFSET 0x0f40 /* Debug Control Register */ /* 0x0f44-0x0f5c Reserved */ -#define SAM_L2CC_PCR_OFFSET 0x0f60 /* Prefetch Control Register */ +#define L2CC_PCR_OFFSET 0x0f60 /* Prefetch Control Register */ /* 0x0f64-0x0f7c Reserved */ -#define SAM_L2CC_POWCR_OFFSET 0x0f80 /* Power Control Register */ +#define L2CC_POWCR_OFFSET 0x0f80 /* Power Control Register */ /* L2CC Register Addresses **********************************************************/ -#define SAM_L2CC_IDR (SAM_L2CC_VSECTION+SAM_L2CC_IDR_OFFSET) -#define SAM_L2CC_TYPR (SAM_L2CC_VSECTION+SAM_L2CC_TYPR_OFFSET) -#define SAM_L2CC_CR (SAM_L2CC_VSECTION+SAM_L2CC_CR_OFFSET) -#define SAM_L2CC_ACR (SAM_L2CC_VSECTION+SAM_L2CC_ACR_OFFSET) -#define SAM_L2CC_TRCR (SAM_L2CC_VSECTION+SAM_L2CC_TRCR_OFFSET) -#define SAM_L2CC_DRCR (SAM_L2CC_VSECTION+SAM_L2CC_DRCR_OFFSET) -#define SAM_L2CC_ECR (SAM_L2CC_VSECTION+SAM_L2CC_ECR_OFFSET) -#define SAM_L2CC_ECFGR1 (SAM_L2CC_VSECTION+SAM_L2CC_ECFGR1_OFFSET) -#define SAM_L2CC_ECFGR0 (SAM_L2CC_VSECTION+SAM_L2CC_ECFGR0_OFFSET) -#define SAM_L2CC_EVR1 (SAM_L2CC_VSECTION+SAM_L2CC_EVR1_OFFSET) -#define SAM_L2CC_EVR0 (SAM_L2CC_VSECTION+SAM_L2CC_EVR0_OFFSET) -#define SAM_L2CC_IMR (SAM_L2CC_VSECTION+SAM_L2CC_IMR_OFFSET) -#define SAM_L2CC_MISR (SAM_L2CC_VSECTION+SAM_L2CC_MISR_OFFSET) -#define SAM_L2CC_RISR (SAM_L2CC_VSECTION+SAM_L2CC_RISR_OFFSET) -#define SAM_L2CC_ICR (SAM_L2CC_VSECTION+SAM_L2CC_ICR_OFFSET) -#define SAM_L2CC_CSR (SAM_L2CC_VSECTION+SAM_L2CC_CSR_OFFSET) -#define SAM_L2CC_IPALR (SAM_L2CC_VSECTION+SAM_L2CC_IPALR_OFFSET) -#define SAM_L2CC_IWR (SAM_L2CC_VSECTION+SAM_L2CC_IWR_OFFSET) -#define SAM_L2CC_CPALR (SAM_L2CC_VSECTION+SAM_L2CC_CPALR_OFFSET) -#define SAM_L2CC_CIR (SAM_L2CC_VSECTION+SAM_L2CC_CIR_OFFSET) -#define SAM_L2CC_CWR (SAM_L2CC_VSECTION+SAM_L2CC_CWR_OFFSET) -#define SAM_L2CC_CIPALR (SAM_L2CC_VSECTION+SAM_L2CC_CIPALR_OFFSET) -#define SAM_L2CC_CIIR (SAM_L2CC_VSECTION+SAM_L2CC_CIIR_OFFSET) -#define SAM_L2CC_CIWR (SAM_L2CC_VSECTION+SAM_L2CC_CIWR_OFFSET) -#define SAM_L2CC_DLKR (SAM_L2CC_VSECTION+SAM_L2CC_DLKR_OFFSET) -#define SAM_L2CC_ILKR (SAM_L2CC_VSECTION+SAM_L2CC_ILKR_OFFSET) -#define SAM_L2CC_DCR (SAM_L2CC_VSECTION+SAM_L2CC_DCR_OFFSET) -#define SAM_L2CC_PCR (SAM_L2CC_VSECTION+SAM_L2CC_PCR_OFFSET) -#define SAM_L2CC_POWCR (SAM_L2CC_VSECTION+SAM_L2CC_POWCR_OFFSET) +#define L2CC_IDR (L2CC_VBASE+L2CC_IDR_OFFSET) +#define L2CC_TYPR (L2CC_VBASE+L2CC_TYPR_OFFSET) +#define L2CC_CR (L2CC_VBASE+L2CC_CR_OFFSET) +#define L2CC_ACR (L2CC_VBASE+L2CC_ACR_OFFSET) +#define L2CC_TRCR (L2CC_VBASE+L2CC_TRCR_OFFSET) +#define L2CC_DRCR (L2CC_VBASE+L2CC_DRCR_OFFSET) +#define L2CC_ECR (L2CC_VBASE+L2CC_ECR_OFFSET) +#define L2CC_ECFGR1 (L2CC_VBASE+L2CC_ECFGR1_OFFSET) +#define L2CC_ECFGR0 (L2CC_VBASE+L2CC_ECFGR0_OFFSET) +#define L2CC_EVR1 (L2CC_VBASE+L2CC_EVR1_OFFSET) +#define L2CC_EVR0 (L2CC_VBASE+L2CC_EVR0_OFFSET) +#define L2CC_IMR (L2CC_VBASE+L2CC_IMR_OFFSET) +#define L2CC_MISR (L2CC_VBASE+L2CC_MISR_OFFSET) +#define L2CC_RISR (L2CC_VBASE+L2CC_RISR_OFFSET) +#define L2CC_ICR (L2CC_VBASE+L2CC_ICR_OFFSET) +#define L2CC_CSR (L2CC_VBASE+L2CC_CSR_OFFSET) +#define L2CC_IPALR (L2CC_VBASE+L2CC_IPALR_OFFSET) +#define L2CC_IWR (L2CC_VBASE+L2CC_IWR_OFFSET) +#define L2CC_CPALR (L2CC_VBASE+L2CC_CPALR_OFFSET) +#define L2CC_CIR (L2CC_VBASE+L2CC_CIR_OFFSET) +#define L2CC_CWR (L2CC_VBASE+L2CC_CWR_OFFSET) +#define L2CC_CIPALR (L2CC_VBASE+L2CC_CIPALR_OFFSET) +#define L2CC_CIIR (L2CC_VBASE+L2CC_CIIR_OFFSET) +#define L2CC_CIWR (L2CC_VBASE+L2CC_CIWR_OFFSET) +#define L2CC_DLKR (L2CC_VBASE+L2CC_DLKR_OFFSET) +#define L2CC_ILKR (L2CC_VBASE+L2CC_ILKR_OFFSET) +#define L2CC_DCR (L2CC_VBASE+L2CC_DCR_OFFSET) +#define L2CC_PCR (L2CC_VBASE+L2CC_PCR_OFFSET) +#define L2CC_POWCR (L2CC_VBASE+L2CC_POWCR_OFFSET) /* L2CC Register Bit Definitions ****************************************************/ @@ -406,4 +411,4 @@ #define L2CC_POWCR_STBYEN (1 << 0) /* Bit 0: Standby Mode Enable */ #define L2CC_POWCR_DCKGATEN (1 << 1) /* Bit 1: Dynamic Clock Gating Enable */ -#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_L2CC_H */ +#endif /* __ARCH_ARM_SRC_ARMV7_A_L2CC_PL310_H */ diff --git a/arch/arm/src/sama5/Kconfig b/arch/arm/src/sama5/Kconfig index 3643a64a0c..d582171a09 100644 --- a/arch/arm/src/sama5/Kconfig +++ b/arch/arm/src/sama5/Kconfig @@ -49,10 +49,6 @@ config SAMA5_HAVE_XDMA bool default n -config SAMA5_HAVE_L2CC - bool - default n - config SAMA5_HAVE_LCDC bool default n @@ -123,6 +119,8 @@ config ARCH_CHIP_SAMA5D3 config ARCH_CHIP_SAMA5D4 bool default n + select ARMV7A_HAVE_L2CC_PL310 + select ARCH_NAND_HWECC select SAMA5_HAVE_AESB select SAMA5_HAVE_EMACB select SAMA5_HAVE_EMAC1 @@ -132,7 +130,6 @@ config ARCH_CHIP_SAMA5D4 select SAMA5_HAVE_UART1 select SAMA5_HAVE_USART4 select SAMA5_HAVE_XDMA - select SAMA5_HAVE_L2CC select SAMA5_HAVE_SAIC select SAMA5_HAVE_SBM select SAMA5_HAVE_SFC @@ -141,7 +138,6 @@ config ARCH_CHIP_SAMA5D4 select SAMA5_HAVE_TC2 select SAMA5_HAVE_TRUSTZONE select SAMA5_HAVE_TWI3 - select ARCH_NAND_HWECC choice prompt "Atmel AT91SAMA5 Chip Selection" @@ -242,11 +238,6 @@ config SAMA5_DBGU bool "Debug Unit (DBGU)" default n -config SAMA5_L2CC - bool "L2 Cache Controller (L2CC)" - default n - depends on SAMA5_HAVE_L2CC - config SAMA5_PIT bool "Periodic Interval Timer (PIT)" default n diff --git a/arch/arm/src/sama5/chip.h b/arch/arm/src/sama5/chip.h index 88b268c004..924e05558a 100644 --- a/arch/arm/src/sama5/chip.h +++ b/arch/arm/src/sama5/chip.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/sama5/chip.h * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2013-2014 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -45,5 +45,15 @@ #include "chip/sam_memorymap.h" +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* arch/arm/src/armv7-a/l2cc_pl310.h includes this file and expects it to provide the + * address of the L2CC-PL310 implementation. + */ + +#define L2CC_VBASE SAM_L2CC_VSECTION + #endif /* __ARCH_ARM_SRC_SAMA5_CHIP_H */