From e76b7d99faba650c1df3b29ffa73d00cea8bba91 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 1 May 2015 07:31:56 -0600 Subject: [PATCH] Added missing EXTI definitions for the STM32 F3; Correct an error the port D base address in the STM32 F3 and F37 memory maps. From Greg Meiste. --- arch/arm/src/stm32/chip/stm32_exti.h | 7 +++++++ arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h | 4 ++-- arch/arm/src/stm32/chip/stm32f37xxx_memorymap.h | 4 ++-- 3 files changed, 11 insertions(+), 4 deletions(-) diff --git a/arch/arm/src/stm32/chip/stm32_exti.h b/arch/arm/src/stm32/chip/stm32_exti.h index 50191ecdcc..ad636417ec 100644 --- a/arch/arm/src/stm32/chip/stm32_exti.h +++ b/arch/arm/src/stm32/chip/stm32_exti.h @@ -137,6 +137,13 @@ # define EXTI_RTC_TAMPER (1 << 21) /* EXTI line 21 is connected to the RTC Tamper and TimeStamp events */ # define EXTI_RTC_TIMESTAMP (1 << 21) /* EXTI line 21 is connected to the RTC Tamper and TimeStamp events */ # define EXTI_RTC_WAKEUP (1 << 22) /* EXTI line 22 is connected to the RTC Wakeup event */ +#elif defined(CONFIG_STM32_STM32F30XX) +# define EXTI_PVD_LINE (1 << 16) /* EXTI line 16 is connected to the PVD output */ +# define EXTI_RTC_ALARM (1 << 17) /* EXTI line 17 is connected to the RTC Alarm event */ +# define EXTI_OTGFS_WAKEUP (1 << 18) /* EXTI line 18 is connected to the USB OTG FS Wakeup event */ +# define EXTI_RTC_TAMPER (1 << 19) /* EXTI line 19 is connected to the RTC Tamper and TimeStamp events */ +# define EXTI_RTC_TIMESTAMP (1 << 19) /* EXTI line 19 is connected to the RTC Tamper and TimeStamp events */ +# define EXTI_RTC_WAKEUP (1 << 20) /* EXTI line 20 is connected to the RTC Wakeup event */ #endif /* Interrupt mask register */ diff --git a/arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h b/arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h index c8cb8f03e9..51cca40eef 100644 --- a/arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h +++ b/arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h @@ -139,7 +139,7 @@ #define STM32_GPIOA_BASE 0x48000000 /* 0x48000000-0x480003ff: GPIO Port A */ #define STM32_GPIOB_BASE 0x48000400 /* 0x48000400-0x480007ff: GPIO Port B */ #define STM32_GPIOC_BASE 0x48000800 /* 0x48000800-0x48000bff: GPIO Port C */ -#define STM32_GPIOD_BASE 0X40000C00 /* 0x48000c00-0x48000fff: GPIO Port D */ +#define STM32_GPIOD_BASE 0X48000C00 /* 0x48000c00-0x48000fff: GPIO Port D */ #define STM32_GPIOE_BASE 0x48001000 /* 0x48001000-0x480013ff: GPIO Port E */ #define STM32_GPIOF_BASE 0x48001400 /* 0x48001400-0x480017ff: GPIO Port F */ @@ -153,7 +153,7 @@ #define STM32_ADC34_BASE 0x50000700 /* 0x50000700-0x50000708: ADC34 Common */ /* Cortex-M4 Base Addresses *********************************************************/ -/* Other registers -- see armv7-m/nvic.h for standard Cortex-M3 registers in this +/* Other registers -- see armv7-m/nvic.h for standard Cortex-M4 registers in this * address range */ diff --git a/arch/arm/src/stm32/chip/stm32f37xxx_memorymap.h b/arch/arm/src/stm32/chip/stm32f37xxx_memorymap.h index cf01966f2d..a9116019bf 100644 --- a/arch/arm/src/stm32/chip/stm32f37xxx_memorymap.h +++ b/arch/arm/src/stm32/chip/stm32f37xxx_memorymap.h @@ -142,12 +142,12 @@ #define STM32_GPIOA_BASE 0x48000000 /* 0x48000000-0x480003ff: GPIO Port A */ #define STM32_GPIOB_BASE 0x48000400 /* 0x48000400-0x480007ff: GPIO Port B */ #define STM32_GPIOC_BASE 0x48000800 /* 0x48000800-0x48000bff: GPIO Port C */ -#define STM32_GPIOD_BASE 0X40000C00 /* 0x48000c00-0x48000fff: GPIO Port D */ +#define STM32_GPIOD_BASE 0X48000C00 /* 0x48000c00-0x48000fff: GPIO Port D */ #define STM32_GPIOE_BASE 0x48001000 /* 0x48001000-0x480013ff: GPIO Port E */ #define STM32_GPIOF_BASE 0x48001400 /* 0x48001400-0x480017ff: GPIO Port F */ /* Cortex-M4 Base Addresses *********************************************************/ -/* Other registers -- see armv7-m/nvic.h for standard Cortex-M3 registers in this +/* Other registers -- see armv7-m/nvic.h for standard Cortex-M4 registers in this * address range */