diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h index 6691fa5642..dfb71287ed 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h @@ -504,20 +504,20 @@ # define RCC_D1CCIPR_FMCSEL_PLL2 (2 << RCC_D1CCIPR_FMCSEL_SHIFT) /* 10: */ # define RCC_D1CCIPR_FMCSEL_PER (3 << RCC_D1CCIPR_FMCSEL_SHIFT) /* 11: */ /* Bits 2-3: Reserved */ -#define RCC_D1CCIPR_QSPISEL_SHIFT (0) /* Bits 4-5: */ +#define RCC_D1CCIPR_QSPISEL_SHIFT (4) /* Bits 4-5: */ #define RCC_D1CCIPR_QSPISEL_MASK (3 << RCC_D1CCIPR_QSPISEL_SHIFT) # define RCC_D1CCIPR_QSPISEL_HCLK (0 << RCC_D1CCIPR_QSPISEL_SHIFT) /* 00: */ # define RCC_D1CCIPR_QSPISEL_PLL1 (1 << RCC_D1CCIPR_QSPISEL_SHIFT) /* 01: */ # define RCC_D1CCIPR_QSPISEL_PLL2 (2 << RCC_D1CCIPR_QSPISEL_SHIFT) /* 10: */ # define RCC_D1CCIPR_QSPISEL_PER (3 << RCC_D1CCIPR_QSPISEL_SHIFT) /* 11: */ /* Bits 6-15: Reserved */ -#define RCC_D1CCIPR_SDMMC_SHIFT (16) /* Bit 15: */ +#define RCC_D1CCIPR_SDMMC_SHIFT (16) /* Bit 16: */ #define RCC_D1CCIPR_SDMMC_MASK (1 << RCC_D1CCIPR_SDMMC_SHIFT) # define RCC_D1CCIPR_SDMMC_PLL1 (0 << RCC_D1CCIPR_SDMMC_SHIFT) /* 0: */ # define RCC_D1CCIPR_SDMMC_PLL2 (1 << RCC_D1CCIPR_SDMMC_SHIFT) /* 1: */ /* Bits 17-27: Reserved */ /* Bits 17-27: Reserved */ -#define RCC_D1CCIPR_CKPERSEL_SHIFT (0) /* Bits 28-29: */ +#define RCC_D1CCIPR_CKPERSEL_SHIFT (28) /* Bits 28-29: */ #define RCC_D1CCIPR_CKPERSEL_MASK (3 << RCC_D1CCIPR_CKPERSEL_SHIFT) # define RCC_D1CCIPR_CKPERSEL_HSI (0 << RCC_D1CCIPR_CKPERSEL_SHIFT) /* 00: */ # define RCC_D1CCIPR_CKPERSEL_CSI (1 << RCC_D1CCIPR_CKPERSEL_SHIFT) /* 01: */ @@ -583,28 +583,23 @@ # define RCC_D2CCIP1R_SWPSEL_PCLK (0 << RCC_D2CCIP1R_SWPSEL_SHIFT) /* 0 */ # define RCC_D2CCIP1R_SWPSEL_HSI (1 << RCC_D2CCIP1R_SWPSEL_SHIFT) /* 1 */ -/* Bit definitions for RCC_D2CCIP2R reigster */ +/* Bit definitions for RCC_D2CCIP2R register */ #define RCC_D2CCIP2R_USART234578SEL_SHIFT (0) /* Bits 0-2 */ # define RCC_D2CCIP2R_USART234578SEL_MASK (7 << RCC_D2CCIP2R_USART234578SEL_SHIFT) #define RCC_D2CCIP2R_USART16SEL_SHIFT (3) /* Bits 3-5 */ # define RCC_D2CCIP2R_USART16SEL_MASK (7 << RCC_D2CCIP2R_USART16SEL_SHIFT) -#define RCC_D2CCIP2R_RNGSEL_SHIFT (3) /* Bits 8-9 */ + /* Bits 6-7: Reserved */ +#define RCC_D2CCIP2R_RNGSEL_SHIFT (8) /* Bits 8-9 */ # define RCC_D2CCIP2R_RNGSEL_MASK (3 << RCC_D2CCIP2R_RNGSEL_SHIFT) + /* Bits 10-11: Reserved */ #define RCC_D2CCIP2R_I2C123SEL_SHIFT (12) /* Bits 12-13 */ #define RCC_D2CCIP2R_I2C123SEL_MASK (3 << RCC_D2CCIP2R_I2C123SEL_SHIFT) # define RCC_D2CCIP2R_I2C123SEL_PCLK1 (0 << RCC_D2CCIP2R_I2C123SEL_SHIFT) /* 00 */ # define RCC_D2CCIP2R_I2C123SEL_PLL3 (1 << RCC_D2CCIP2R_I2C123SEL_SHIFT) /* 01 */ # define RCC_D2CCIP2R_I2C123SEL_HSI (2 << RCC_D2CCIP2R_I2C123SEL_SHIFT) /* 10 */ # define RCC_D2CCIP2R_I2C123SEL_CSI (3 << RCC_D2CCIP2R_I2C123SEL_SHIFT) /* 11 */ - -#define RCC_D2CCIP2R_I2C4SEL_SHIFT (8) /* Bits 8-9 */ -#define RCC_D2CCIP2R_I2C4SEL_MASK (3 << RCC_D2CCIP2R_I2C4SEL_SHIFT) -# define RCC_D2CCIP2R_I2C4SEL_PCLK1 (0 << RCC_D2CCIP2R_I2C4SEL_SHIFT) /* 00 */ -# define RCC_D2CCIP2R_I2C4SEL_PLL3 (1 << RCC_D2CCIP2R_I2C4SEL_SHIFT) /* 01 */ -# define RCC_D2CCIP2R_I2C4SEL_HSI (2 << RCC_D2CCIP2R_I2C4SEL_SHIFT) /* 10 */ -# define RCC_D2CCIP2R_I2C4SEL_CSI (3 << RCC_D2CCIP2R_I2C4SEL_SHIFT) /* 11 */ - + /* Bits 14-19: Reserved */ #define RCC_D2CCIP2R_USBSEL_SHIFT (20) /* Bits 20-21 */ # define RCC_D2CCIP2R_USBSEL_MASK (3 << RCC_D2CCIP2R_USBSEL_SHIFT) # define RCC_D2CCIP2R_USBSEL_DISABLE (0 << RCC_D2CCIP2R_USBSEL_SHIFT) @@ -613,10 +608,12 @@ # define RCC_D2CCIP2R_USBSEL_HSI48 (3 << RCC_D2CCIP2R_USBSEL_SHIFT) #define RCC_D2CCIP2R_CECSEL_SHIFT (22) /* Bits 22-23 */ # define RCC_D2CCIP2R_CECSEL_MASK (3 << RCC_D2CCIP2R_CECSEL_SHIFT) + /* Bits 24-27: Reserved */ #define RCC_D2CCIP2R_LPTIM1SEL_SHIFT (28) /* Bits 28-30 */ # define RCC_D2CCIP2R_LPTIM1SEL_MASK (3 << RCC_D2CCIP2R_LPTIM1SEL_SHIFT) + /* Bit 31: Reserved */ -/* TODO: Bit definitions for RCC_D3CCIPR reigster */ +/* Bit definitions for RCC_D3CCIPR register */ #define RCC_D3CCIPR_LPUART1SEL_SHIFT (0) /* Bits 0-2: LPUART1 kernel clock source selection */ #define RCC_D3CCIPR_LPUART1SEL_MASK (7 << RCC_D3CCIPR_LPUART1SEL_SHIFT) diff --git a/arch/arm/src/stm32h7/stm32_adc.c b/arch/arm/src/stm32h7/stm32_adc.c index c79742ad18..81982cc528 100644 --- a/arch/arm/src/stm32h7/stm32_adc.c +++ b/arch/arm/src/stm32h7/stm32_adc.c @@ -138,7 +138,7 @@ (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP19_SHIFT)) /* The channels not in this range are internal channels for reading - * Vbat ADC3:17, VSence (temperature) ADC3:18 and Vrefint ADC3:19 + * Vbat ADC3:17, VSense (temperature) ADC3:18 and Vrefint ADC3:19 * * N.B. DAC channels on ADC2 are not supported */ @@ -1505,11 +1505,11 @@ static bool adc_internal(FAR struct stm32_dev_s * priv, uint32_t *adc_ccr) switch (priv->chanlist[i]) { case 17: - *adc_ccr |= ADC_CCR_VSENSEEN; + *adc_ccr |= ADC_CCR_VBATEN; break; case 18: - *adc_ccr |= ADC_CCR_VBATEN; + *adc_ccr |= ADC_CCR_VSENSEEN; break; case 19: diff --git a/arch/arm/src/stm32h7/stm32_serial.c b/arch/arm/src/stm32h7/stm32_serial.c index cce3664368..fe59bdd226 100644 --- a/arch/arm/src/stm32h7/stm32_serial.c +++ b/arch/arm/src/stm32h7/stm32_serial.c @@ -672,7 +672,7 @@ static struct up_dev_s g_uart8priv = }, .irq = STM32_IRQ_UART8, - .rxftcfg = CONFIG_USRT8_RXFIFO_THRES, + .rxftcfg = CONFIG_UART8_RXFIFO_THRES, .parity = CONFIG_UART8_PARITY, .bits = CONFIG_UART8_BITS, .stopbits2 = CONFIG_UART8_2STOP, diff --git a/arch/arm/src/stm32h7/stm32_spi.c b/arch/arm/src/stm32h7/stm32_spi.c index eb776b28ed..ebf7a2e16b 100644 --- a/arch/arm/src/stm32h7/stm32_spi.c +++ b/arch/arm/src/stm32h7/stm32_spi.c @@ -167,7 +167,7 @@ #endif /* SPI45 */ #if defined(CONFIG_STM32H7_SPI6) -# if STM32_RCC_D3CCIP1R_SPI6SRC == RCC_D3CCIP1R_SPI6SEL_PCLK4 +# if STM32_RCC_D3CCIPR_SPI6SRC == RCC_D3CCIPR_SPI6SEL_PCLK4 # define SPI6_KERNEL_CLOCK_FREQ STM32_PCLK4_FREQUENCY # else # error Not supported yet diff --git a/configs/nucleo-h743zi/include/board.h b/configs/nucleo-h743zi/include/board.h index a126aa6394..90f43242d4 100644 --- a/configs/nucleo-h743zi/include/board.h +++ b/configs/nucleo-h743zi/include/board.h @@ -234,7 +234,7 @@ /* I2C4 clock source - HSI */ -#define STM32_RCC_D2CCIP3R_I2C4SRC RCC_D2CCIP3R_I2C4SEL_HSI +#define STM32_RCC_D3CCIPR_I2C4SRC RCC_D3CCIPR_I2C4SEL_HSI /* SPI123 clock source - PLL1Q */ @@ -246,7 +246,7 @@ /* SPI6 clock source - APB (PCLK4) */ -#define STM32_RCC_D3CCIP1R_SPI6SRC RCC_D3CCIP1R_SPI6SEL_PCLK4 +#define STM32_RCC_D3CCIPR_SPI6SRC RCC_D3CCIPR_SPI6SEL_PCLK4 /* USB 1 and 2 clock source - HSI48 */