EFM32: Add LFA and LFB clock support
This commit is contained in:
Gregory Nutt
parent
6cf07c2a0e
commit
e7fe3882a6
@ -71,6 +71,18 @@
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# error HFPERCLK divisor not yet supported
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#endif
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#ifdef BOARD_LFACLK_ULFRCO
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# define BOARD_LFA_ULFCO_ENABLE true
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#else
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# define BOARD_LFA_ULFCO_ENABLE false
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#endif
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#ifdef BOARD_LFBCLK_ULFRCO
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# define BOARD_LFB_ULFCO_ENABLE true
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#else
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# define BOARD_LFB_ULFCO_ENABLE false
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#endif
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/****************************************************************************
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* Public Data
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****************************************************************************/
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@ -140,7 +152,7 @@ static inline void efm32_statuswait(uint32_t bitset)
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*
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****************************************************************************/
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static inline void efm32_enable_lfrco(void)
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static void efm32_enable_lfrco(void)
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{
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/* Enable the LFRCO */
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@ -148,8 +160,7 @@ static inline void efm32_enable_lfrco(void)
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efm32_statuswait(CMU_STATUS_LFRCORDY);
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}
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static inline void efm32_enable_lfxo(void)
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static void efm32_enable_lfxo(void)
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{
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/* Enable the LFXO */
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@ -165,7 +176,7 @@ static inline void efm32_enable_hfrco(void)
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efm32_statuswait(CMU_STATUS_HFRCORDY);
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}
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static inline void efm32_enable_hfxo(void)
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static void efm32_enable_hfxo(void)
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{
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/* Enable the HFXO */
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@ -181,6 +192,58 @@ static inline void efm32_enable_auxhfrco(void)
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efm32_statuswait(CMU_STATUS_AUXHFRCORDY);
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}
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/****************************************************************************
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* Name: efm32_enable_leclocking
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*
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* Description:
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* Enable HFCORE clocking to the LE
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*
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****************************************************************************/
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static void efm32_enable_leclocking(void)
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{
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uint32_t regval;
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regval = getreg32(EFM32_CMU_HFCORECLKEN0);
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regval |= CMU_HFCORECLKEN0_LE;
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putreg32(regval, EFM32_CMU_HFCORECLKEN0);
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}
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/****************************************************************************
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* Name: efm32_enable_leclocking
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*
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* Description:
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* If the core frequency is higher than CMU_MAX_FREQ_HFLE on
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* Giant/Leopard/Wonder, enable HFLE and DIV4.
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*
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****************************************************************************/
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#ifdef CMU_CTRL_HFLE
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static void efm32_enable_hfle(uint32_t frequency)
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{
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uint32_t regval;
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/* Check if the core frequency is higher than CMU_MAX_FREQ_HFLE */
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if (frequency > CMU_MAX_FREQ_HFLE)
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{
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/* Enable HFLE */
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regval = getreg32(EFM32_CMU_CTRL);
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regval |= CMU_CTRL_HFLE;
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putreg32(regval, EFM32_CMU_CTRL);
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/* Enable DIV4 factor for peripheral clock */
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regval = getreg32(EFM32_CMU_HFCORECLKDIV);
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regval |= CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4;
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putreg32(regval, EFM32_CMU_HFCORECLKDIV);
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}
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}
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#else
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# define efm32_enable_hfle(f)
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#endif
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/****************************************************************************
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* Name: efm32_maxwaitstates
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*
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@ -326,7 +389,7 @@ static void efm32_setwaitstates(uint32_t hfcoreclk)
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*
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****************************************************************************/
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static inline void efm32_hfclk_config(uint32_t hfclksel, uint32_t hfclkdiv)
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static inline uint32_t efm32_hfclk_config(uint32_t hfclksel, uint32_t hfclkdiv)
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{
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uint32_t frequency;
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#ifdef CMU_CTRL_HFLE
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@ -427,6 +490,7 @@ static inline void efm32_hfclk_config(uint32_t hfclksel, uint32_t hfclkdiv)
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/* Now select the optimal number of FLASH wait states */
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efm32_setwaitstates(frequency);
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return frequency;
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}
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/****************************************************************************
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@ -458,9 +522,11 @@ static inline void efm32_hfclk_config(uint32_t hfclksel, uint32_t hfclkdiv)
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*
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****************************************************************************/
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static inline void efm32_hfcoreclk_config(uint32_t hfcoreclkdiv)
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static inline uint32_t efm32_hfcoreclk_config(uint32_t hfcoreclkdiv,
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uint32_t hfclk)
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{
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/* REVISIT: Divider not currently used */
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return hfclk;
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}
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/****************************************************************************
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@ -479,9 +545,11 @@ static inline void efm32_hfcoreclk_config(uint32_t hfcoreclkdiv)
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*
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****************************************************************************/
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static inline void efm32_hfperclk_config(uint32_t hfperclkdiv)
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static inline uint32_t efm32_hfperclk_config(uint32_t hfperclkdiv,
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uint32_t hfclk)
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{
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/* REVISIT: Divider not currently used */
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return hfclk;
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}
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/****************************************************************************
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@ -509,9 +577,77 @@ static inline void efm32_hfperclk_config(uint32_t hfperclkdiv)
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*
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****************************************************************************/
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static inline void efm32_lfaclk_config(uint32_t lfaclksel)
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static inline uint32_t efm32_lfaclk_config(uint32_t lfaclksel, bool ulfrco,
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uint32_t hfcoreclk)
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{
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/* REVISIT: Not yet implemented */
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uint32_t lfaclk;
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uint32_t regval;
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/* ULFRCO is a special case */
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if (ulfrco)
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{
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/* ULFRCO is always enabled */
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lfaclksel = _CMU_LFCLKSEL_LFA_DISABLED;
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lfaclk = BOARD_ULFRCO_FREQUNCY;
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}
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else
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{
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/* Enable the oscillator source */
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switch (lfaclksel)
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{
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default:
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case _CMU_LFCLKSEL_LFA_DISABLED:
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{
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lfaclk = 0;
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}
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break;
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case CMU_LFCLKSEL_LFA_LFRCO:
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{
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efm32_enable_lfrco();
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}
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break;
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case _CMU_LFCLKSEL_LFA_LFXO:
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{
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efm32_enable_lfxo();
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lfaclk = BOARD_LFXO_FREQUENCY;
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}
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break;
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case _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2:
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{
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/* Enable core clocking to the LE */
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efm32_enable_leclocking();
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/* Enable HFLE, if appropriate */
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efm32_enable_hfle(hfcoreclk);
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/* And, finally, enable the HFXO */
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efm32_enable_hfxo();
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lfaclk = hfcoreclk >> 1;
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}
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break;
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}
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}
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/* Enable the LFA clock in the LFCLKSEL register */
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regval = getreg32(EFM32_CMU_LFCLKSEL);
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regval &= ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK);
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regval |= (lfaclksel << _CMU_LFCLKSEL_LFA_SHIFT);
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#ifdef CMU_LFCLKSEL_LFAE_ULFRCO
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regval |= ((uint32_t)ulfrco << _CMU_LFCLKSEL_LFAE_SHIFT);
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#endif
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putreg32(regval, EFM32_CMU_LFCLKSEL);
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return lfaclk;
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}
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/****************************************************************************
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@ -535,9 +671,77 @@ static inline void efm32_lfaclk_config(uint32_t lfaclksel)
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*
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****************************************************************************/
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static inline void efm32_lfbclk_config(uint32_t lfbclksel)
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static inline uint32_t efm32_lfbclk_config(uint32_t lfbclksel, bool ulfrco,
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uint32_t hfcoreclk)
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{
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/* REVISIT: Not yet implemented */
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uint32_t lfbclk;
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uint32_t regval;
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/* ULFRCO is a special case */
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if (ulfrco)
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{
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/* ULFRCO is always enabled */
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lfbclksel = _CMU_LFCLKSEL_LFB_DISABLED;
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lfbclk = BOARD_ULFRCO_FREQUNCY;
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}
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else
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{
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/* Enable the oscillator source */
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switch (lfbclksel)
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{
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default:
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case _CMU_LFCLKSEL_LFB_DISABLED:
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{
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lfbclk = 0;
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}
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break;
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case CMU_LFCLKSEL_LFB_LFRCO:
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{
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efm32_enable_lfrco();
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}
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break;
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case _CMU_LFCLKSEL_LFB_LFXO:
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{
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efm32_enable_lfxo();
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lfbclk = BOARD_LFXO_FREQUENCY;
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}
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break;
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case _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2:
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{
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/* Enable core clocking to the LE */
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efm32_enable_leclocking();
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/* Enable HFLE, if appropriate */
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efm32_enable_hfle(hfcoreclk);
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/* And, finally, enable the HFXO */
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efm32_enable_hfxo();
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lfbclk = hfcoreclk >> 1;
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}
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break;
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}
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}
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/* Enable the LFB clock in the LFCLKSEL register */
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regval = getreg32(EFM32_CMU_LFCLKSEL);
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regval &= ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK);
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regval |= (lfbclksel << _CMU_LFCLKSEL_LFB_SHIFT);
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#ifdef CMU_LFCLKSEL_LFBE_ULFRCO
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regval |= ((uint32_t)ulfrco << _CMU_LFCLKSEL_LFBE_SHIFT);
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#endif
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putreg32(regval, EFM32_CMU_LFCLKSEL);
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return lfbclk;
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}
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/****************************************************************************
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@ -634,17 +838,28 @@ static inline void efm32_gpioclock(void)
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void efm32_clockconfig(void)
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{
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uint32_t hfclk;
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uint32_t hfcoreclk;
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uint32_t hfperclk;
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uint32_t lfaclk;
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uint32_t lfbclk;
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/* Enable clocks and set dividers as determined by the board.h header file */
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efm32_hfclk_config(BOARD_HFCLKSEL, BOARD_HFCLKDIV);
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efm32_hfcoreclk_config(BOARD_HFCORECLKDIV);
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efm32_hfperclk_config(BOARD_HFPERCLKDIV);
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efm32_lfaclk_config(BOARD_LFACLKSEL);
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efm32_lfbclk_config(BOARD_LFBCLKSEL);
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hfclk = efm32_hfclk_config(BOARD_HFCLKSEL, BOARD_HFCLKDIV);
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hfcoreclk = efm32_hfcoreclk_config(BOARD_HFCORECLKDIV, hfclk);
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hfperclk = efm32_hfperclk_config(BOARD_HFPERCLKDIV, hfclk);
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lfaclk = efm32_lfaclk_config(BOARD_LFACLKSEL, BOARD_LFA_ULFCO_ENABLE, hfcoreclk);
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lfbclk = efm32_lfbclk_config(BOARD_LFBCLKSEL, BOARD_LFB_ULFCO_ENABLE, hfcoreclk);
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efm32_pcntclk_config();
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efm32_wdogclk_config();
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efm32_auxclk_config();
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UNUSED(hfperclk);
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UNUSED(lfaclk);
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UNUSED(lfbclk);
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/* Enable clocking of the GPIO ports */
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efm32_gpioclock();
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