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arch/risc-v: Remove dupped irq code from k210

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Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
This commit is contained in:
Huang Qi 2022-01-20 22:09:24 +08:00 committed by Xiang Xiao
parent 7738bb98fc
commit e81439a367
5 changed files with 24 additions and 49 deletions
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31
arch/risc-v/include/k210/irq.h
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@ -33,39 +33,14 @@
/* Map RISC-V exception code to NuttX IRQ */
/* IRQ 0-15 : (exception:interrupt=0) */
#define K210_IRQ_IAMISALIGNED (0) /* Instruction Address Misaligned */
#define K210_IRQ_IAFAULT (1) /* Instruction Address Fault */
#define K210_IRQ_IINSTRUCTION (2) /* Illegal Instruction */
#define K210_IRQ_BPOINT (3) /* Break Point */
#define K210_IRQ_LAMISALIGNED (4) /* Load Address Misaligned */
#define K210_IRQ_LAFAULT (5) /* Load Access Fault */
#define K210_IRQ_SAMISALIGNED (6) /* Store/AMO Address Misaligned */
#define K210_IRQ_SAFAULT (7) /* Store/AMO Access Fault */
#define K210_IRQ_ECALLU (8) /* Environment Call from U-mode */
/* 9-10: Reserved */
#define K210_IRQ_ECALLM (11) /* Environment Call from M-mode */
/* 12-15: Reserved */
/* IRQ 16- : (async event:interrupt=1) */
#define K210_IRQ_ASYNC (16)
#define K210_IRQ_MSOFT (K210_IRQ_ASYNC + 3) /* Machine Software Int */
#define K210_IRQ_MTIMER (K210_IRQ_ASYNC + 7) /* Machine Timer Int */
#define K210_IRQ_MEXT (K210_IRQ_ASYNC + 11) /* Machine External Int */
/* Machine Global External Interrupt */
#ifdef CONFIG_K210_WITH_QEMU
#define K210_IRQ_UART0 (K210_IRQ_MEXT + 4)
#define K210_IRQ_UART0 (RISCV_IRQ_MEXT + 4)
#else
#define K210_IRQ_UART0 (K210_IRQ_MEXT + 33)
#define K210_IRQ_UART0 (RISCV_IRQ_MEXT + 33)
#endif
/* Total number of IRQs */
#define NR_IRQS (K210_IRQ_UART0 + 1)
#define NR_IRQS (K210_IRQ_UART0 + 1)
#endif /* __ARCH_RISCV_INCLUDE_K210_IRQ_H */

2
arch/risc-v/src/k210/k210_cpustart.c
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@ -103,7 +103,7 @@ void k210_cpu_boot(int cpu)
/* Enable machine software interrupt for IPI to boot */
up_enable_irq(K210_IRQ_MSOFT);
up_enable_irq(RISCV_IRQ_MSOFT);
/* Wait interrupt */

24
arch/risc-v/src/k210/k210_irq.c
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@ -102,10 +102,10 @@ void up_irqinitialize(void)
/* Attach the ecall interrupt handler */
irq_attach(K210_IRQ_ECALLM, riscv_swint, NULL);
irq_attach(RISCV_IRQ_ECALLM, riscv_swint, NULL);
#ifdef CONFIG_BUILD_PROTECTED
irq_attach(K210_IRQ_ECALLU, riscv_swint, NULL);
irq_attach(RISCV_IRQ_ECALLU, riscv_swint, NULL);
#endif
#ifdef CONFIG_SMP
@ -115,8 +115,8 @@ void up_irqinitialize(void)
/* Setup MSOFT for CPU0 with pause handler */
irq_attach(K210_IRQ_MSOFT, riscv_pause_handler, NULL);
up_enable_irq(K210_IRQ_MSOFT);
irq_attach(RISCV_IRQ_MSOFT, riscv_pause_handler, NULL);
up_enable_irq(RISCV_IRQ_MSOFT);
#endif
#ifndef CONFIG_SUPPRESS_INTERRUPTS
@ -140,21 +140,21 @@ void up_disable_irq(int irq)
int extirq;
uint64_t oldstat;
if (irq == K210_IRQ_MSOFT)
if (irq == RISCV_IRQ_MSOFT)
{
/* Read mstatus & clear machine software interrupt enable in mie */
asm volatile ("csrrc %0, mie, %1": "=r" (oldstat) : "r"(MIE_MSIE));
}
else if (irq == K210_IRQ_MTIMER)
else if (irq == RISCV_IRQ_MTIMER)
{
/* Read mstatus & clear machine timer interrupt enable in mie */
asm volatile ("csrrc %0, mie, %1": "=r" (oldstat) : "r"(MIE_MTIE));
}
else if (irq > K210_IRQ_MEXT)
else if (irq > RISCV_IRQ_MEXT)
{
extirq = irq - K210_IRQ_MEXT;
extirq = irq - RISCV_IRQ_MEXT;
/* Clear enable bit for the irq */
@ -183,21 +183,21 @@ void up_enable_irq(int irq)
int extirq;
uint64_t oldstat;
if (irq == K210_IRQ_MSOFT)
if (irq == RISCV_IRQ_MSOFT)
{
/* Read mstatus & set machine software interrupt enable in mie */
asm volatile ("csrrs %0, mie, %1": "=r" (oldstat) : "r"(MIE_MSIE));
}
else if (irq == K210_IRQ_MTIMER)
else if (irq == RISCV_IRQ_MTIMER)
{
/* Read mstatus & set machine timer interrupt enable in mie */
asm volatile ("csrrs %0, mie, %1": "=r" (oldstat) : "r"(MIE_MTIE));
}
else if (irq > K210_IRQ_MEXT)
else if (irq > RISCV_IRQ_MEXT)
{
extirq = irq - K210_IRQ_MEXT;
extirq = irq - RISCV_IRQ_MEXT;
/* Set enable bit for the irq */

12
arch/risc-v/src/k210/k210_irq_dispatch.c
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@ -58,14 +58,14 @@ void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
/* Check if fault happened */
if (vector < K210_IRQ_ECALLU)
if (vector < RISCV_IRQ_ECALLU)
{
up_fault((int)irq, regs);
}
/* Firstly, check if the irq is machine external interrupt */
if (K210_IRQ_MEXT == irq)
if (RISCV_IRQ_MEXT == irq)
{
uint32_t val = getreg32(K210_PLIC_CLAIM);
@ -76,7 +76,7 @@ void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
/* NOTE: In case of ecall, we need to adjust mepc in the context */
if (K210_IRQ_ECALLM == irq || K210_IRQ_ECALLU == irq)
if (RISCV_IRQ_ECALLM == irq || RISCV_IRQ_ECALLU == irq)
{
*mepc += 4;
}
@ -99,18 +99,18 @@ void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
/* MEXT means no interrupt */
if (K210_IRQ_MEXT != irq)
if (RISCV_IRQ_MEXT != irq)
{
/* Deliver the IRQ */
irq_dispatch(irq, regs);
}
if (K210_IRQ_MEXT <= irq)
if (RISCV_IRQ_MEXT <= irq)
{
/* Then write PLIC_CLAIM to clear pending in PLIC */
putreg32(irq - K210_IRQ_MEXT, K210_PLIC_CLAIM);
putreg32(irq - RISCV_IRQ_MEXT, K210_PLIC_CLAIM);
}
#endif

4
arch/risc-v/src/k210/k210_timerisr.c
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@ -121,7 +121,7 @@ void up_timer_initialize(void)
#if 1
/* Attach timer interrupt handler */
irq_attach(K210_IRQ_MTIMER, k210_timerisr, NULL);
irq_attach(RISCV_IRQ_MTIMER, k210_timerisr, NULL);
/* Reload CLINT mtimecmp */
@ -129,6 +129,6 @@ void up_timer_initialize(void)
/* And enable the timer interrupt */
up_enable_irq(K210_IRQ_MTIMER);
up_enable_irq(RISCV_IRQ_MTIMER);
#endif
}