SAMA5 EHCI: Implemented (but did not test) interrupt endpoint logic
This commit is contained in:
Gregory Nutt
parent
1ab10a20bd
commit
e862d5d197
@ -5473,4 +5473,6 @@
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determines which memory regions get added to the heap. When
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CONFIG_MM_NREGIONS > 1, the logic was adding the ISRAM region to
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the heap twice! (2013-6-27).
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* nuttx/arch/arm/src/sama5/sam_ehci.c: Add (untested) support for
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interrupt endpoints (2013-8-28).
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@ -103,10 +103,7 @@
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# undef CONFIG_SAMA5_EHCI_REGDEBUG
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#endif
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/* Periodic transfers will be supported later */
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#undef CONFIG_USBHOST_INT_DISABLE
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#define CONFIG_USBHOST_INT_DISABLE 1
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/* Isochronous transfers are not currently supported */
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#undef CONFIG_USBHOST_ISOC_DISABLE
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#define CONFIG_USBHOST_ISOC_DISABLE 1
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@ -297,7 +294,6 @@ static void sam_qtd_free(struct sam_qtd_s *qtd);
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static int sam_qh_foreach(struct sam_qh_s *qh, uint32_t **bp,
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foreach_qh_t handler, void *arg);
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static int sam_qh_forall(foreach_qh_t handler, void *arg);
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static int sam_qtd_foreach(struct sam_qh_s *qh, foreach_qtd_t handler,
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void *arg);
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static int sam_qtd_discard(struct sam_qtd_s *qtd, uint32_t **bp, void *arg);
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@ -319,20 +315,16 @@ static void sam_qtd_print(struct sam_qtd_s *qtd);
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static void sam_qh_print(struct sam_qh_s *qh);
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static int sam_qtd_dump(struct sam_qtd_s *qtd, uint32_t **bp, void *arg);
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static int sam_qh_dump(struct sam_qh_s *qh, uint32_t **bp, void *arg);
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#if 0 /* not used */
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static int sam_qh_dumpall(void);
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#endif
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#else
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# define sam_qtd_print(qtd)
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# define sam_qh_print(qh)
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# define sam_qtd_dump(qtd, bp, arg) OK
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# define sam_qh_dump(qh, bp, arg) OK
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# define sam_qh_dumpall() OK
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#endif
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static int sam_ioc_setup(struct sam_rhport_s *rhport, struct sam_epinfo_s *epinfo);
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static int sam_ioc_wait(struct sam_epinfo_s *epinfo);
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static void sam_qh_enqueue(struct sam_qh_s *qh);
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static void sam_qh_enqueue(struct sam_qh_s *qhead, struct sam_qh_s *qh);
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static struct sam_qh_s *sam_qh_create(struct sam_rhport_s *rhport,
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struct sam_epinfo_s *epinfo);
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static int sam_qtd_addbpl(struct sam_qtd_s *qtd, const void *buffer, size_t buflen);
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@ -344,6 +336,10 @@ static struct sam_qtd_s *sam_qtd_statusphase(uint32_t tokenbits);
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static ssize_t sam_async_transfer(struct sam_rhport_s *rhport,
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struct sam_epinfo_s *epinfo, const struct usb_ctrlreq_s *req,
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uint8_t *buffer, size_t buflen);
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#ifndef CONFIG_USBHOST_INT_DISABLE
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static ssize_t sam_intr_transfer(struct sam_rhport_s *rhport,
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struct sam_epinfo_s *epinfo, uint8_t *buffer, size_t buflen);
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#endif
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/* Interrupt Handling **********************************************************/
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@ -408,11 +404,15 @@ static struct sam_qh_s g_asynchead __attribute__ ((aligned(32)));
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#ifndef CONFIG_USBHOST_INT_DISABLE
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/* The head of the periodic queue */
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static struct sam_qh_s g_perhead __attribute__ ((aligned(32)));
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static struct sam_qh_s g_intrhead __attribute__ ((aligned(32)));
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/* The frame list */
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#ifdef CONFIG_SAMA5_EHCI_PREALLOCATE
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static uint32_t g_framelist[FRAME_LIST_SIZE] __attribute__ ((aligned(4096)));
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#else
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static uint32_t *g_framelist;
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#endif
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#endif
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#ifdef CONFIG_SAMA5_EHCI_PREALLOCATE
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@ -951,34 +951,6 @@ static int sam_qh_foreach(struct sam_qh_s *qh, uint32_t **bp, foreach_qh_t handl
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return OK;
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}
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/*******************************************************************************
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* Name: sam_qh_forall
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*
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* Description:
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* Setup and call sam_qh_foreach to that every element of the asynchronous
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* queue is examined.
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*
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* Assumption: The caller holds the EHCI exclsem
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*
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*******************************************************************************/
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static int sam_qh_forall(foreach_qh_t handler, void *arg)
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{
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struct sam_qh_s *qh;
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uint32_t *bp;
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/* Set the back pointer to the forward qTD pointer of the asynchronous
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* queue head.
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*/
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bp = (uint32_t *)&g_asynchead.hw.hlp;
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qh = (struct sam_qh_s *)sam_virtramaddr(sam_swap32(*bp) & QH_HLP_MASK);
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/* Then traverse and operate on every QH and qTD in the list */
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return sam_qh_foreach(qh, &bp, handler, arg);
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}
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/*******************************************************************************
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* Name: sam_qtd_foreach
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*
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@ -1322,26 +1294,6 @@ static int sam_qh_dump(struct sam_qh_s *qh, uint32_t **bp, void *arg)
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}
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#endif
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/*******************************************************************************
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* Name: sam_qh_dumpall
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*
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* Description:
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* Set the request for the IOC event well BEFORE enabling the transfer (as
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* soon as we are absolutely committed to the to avoid transfer). We do this
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* to minimize race conditions. This logic would have to be expanded if we
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* want to have more than one packet in flight at a time!
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*
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*******************************************************************************/
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#ifdef CONFIG_SAMA5_EHCI_REGDEBUG
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#if 0 /* not used */
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static int sam_qh_dumpall(void)
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{
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return sam_qh_forall(sam_qh_dump, NULL);
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}
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#endif
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#endif
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/*******************************************************************************
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* Name: sam_ioc_setup
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*
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@ -1416,7 +1368,7 @@ static int sam_ioc_wait(struct sam_epinfo_s *epinfo)
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*
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*******************************************************************************/
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static void sam_qh_enqueue(struct sam_qh_s *qh)
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static void sam_qh_enqueue(struct sam_qh_s *qhead, struct sam_qh_s *qh)
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{
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uintptr_t physaddr;
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@ -1434,7 +1386,7 @@ static void sam_qh_enqueue(struct sam_qh_s *qh)
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* attached qTDs to RAM.
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*/
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qh->hw.hlp = g_asynchead.hw.hlp;
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qh->hw.hlp = qhead->hw.hlp;
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sam_qh_flush(qh);
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/* Then set the new QH as the first QH in the asychronous queue and flush the
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@ -1442,9 +1394,9 @@ static void sam_qh_enqueue(struct sam_qh_s *qh)
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*/
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physaddr = (uintptr_t)sam_physramaddr((uintptr_t)qh);
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g_asynchead.hw.hlp = sam_swap32(physaddr | QH_HLP_TYP_QH);
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cp15_clean_dcache((uintptr_t)&g_asynchead.hw,
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(uintptr_t)&g_asynchead.hw + sizeof(struct ehci_qh_s));
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qhead->hw.hlp = sam_swap32(physaddr | QH_HLP_TYP_QH);
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cp15_clean_dcache((uintptr_t)&qhead->hw,
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(uintptr_t)&qhead->hw + sizeof(struct ehci_qh_s));
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}
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/*******************************************************************************
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@ -1515,7 +1467,7 @@ static struct sam_qh_s *sam_qh_create(struct sam_rhport_s *rhport,
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*
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* FIELD DESCRIPTION VALUE/SOURCE
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* -------- ------------------------------- --------------------
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* SSMASK Interrupt Schedule Mask 0
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* SSMASK Interrupt Schedule Mask Depends on epinfo->xfrtype
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* SCMASK Split Completion Mask 0
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* HUBADDR Hub Address Always 0 for now
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* PORT Port number RH port index + 1
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@ -1525,9 +1477,29 @@ static struct sam_qh_s *sam_qh_create(struct sam_rhport_s *rhport,
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* and HUB device address to be included here.
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*/
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regval = ((uint32_t)0 << QH_EPCAPS_HUBADDR_SHIFT) |
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((uint32_t)(rhport->rhpndx + 1) << QH_EPCAPS_PORT_SHIFT) |
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((uint32_t)1 << QH_EPCAPS_MULT_SHIFT);
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regval = ((uint32_t)0 << QH_EPCAPS_HUBADDR_SHIFT) |
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((uint32_t)(rhport->rhpndx + 1) << QH_EPCAPS_PORT_SHIFT) |
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((uint32_t)1 << QH_EPCAPS_MULT_SHIFT);
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#ifndef CONFIG_USBHOST_INT_DISABLE
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if (epinfo->xfrtype == USB_EP_ATTR_XFER_INT)
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{
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/* Here, the S-Mask field in the queue head is set to 1, indicating
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* that the transaction for the endpoint should be executed on the bus
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* during micro-frame 0 of the frame.
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*
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* REVISIT: The polling interval should be controlled by the which
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* entry is the framelist holds the QH pointer for a given micro-frame
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* and the QH pointer should be replicated for different polling rates.
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* This implementation currently just sets all frame_list entry to
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* all the same interrupt queue. That should work but will not give
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* any control over polling rates.
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*/
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#warning REVISIT
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regval |= ((uint32_t)1 << QH_EPCAPS_SSMASK_SHIFT);
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}
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#endif
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qh->hw.epcaps = sam_swap32(regval);
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@ -1845,6 +1817,7 @@ static ssize_t sam_async_transfer(struct sam_rhport_s *rhport,
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uint32_t *flink;
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uint32_t *alt;
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uint32_t toggle;
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uint32_t regval;
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int ret;
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uvdbg("RHport%d EP%d: buffer=%p, buflen=%d, req=%p\n",
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@ -1931,7 +1904,7 @@ static ssize_t sam_async_transfer(struct sam_rhport_s *rhport,
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bool dirin;
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/* Extra TOKEN bits include the data toggle, the data PID, and if
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* there is no request, and indication to interrupt at the end of this
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* there is no request, an indication to interrupt at the end of this
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* transfer.
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*/
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@ -2058,9 +2031,20 @@ static ssize_t sam_async_transfer(struct sam_rhport_s *rhport,
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}
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}
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/* Disable the asynchronous schedule */
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regval = sam_getreg(&HCOR->usbcmd);
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regval &= ~EHCI_USBCMD_ASEN;
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sam_putreg(regval, &HCOR->usbcmd);
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/* Add the new QH to the head of the asynchronous queue list */
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sam_qh_enqueue(qh);
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sam_qh_enqueue(&g_asynchead, qh);
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/* Re-enable the asynchronous schedule */
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regval |= EHCI_USBCMD_ASEN;
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sam_putreg(regval, &HCOR->usbcmd);
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/* Release the EHCI semaphore while we wait. Other threads need the
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* opportunity to access the EHCI resources while we wait.
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@ -2105,12 +2089,193 @@ errout_with_iocwait:
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return (ssize_t)ret;
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}
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/*******************************************************************************
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* Name: sam_intr_transfer
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*
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* Description:
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* Process a IN or OUT request on any interrupt endpoint by inserting a qTD
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* into the periodic frame list.
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*
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* Paragraph 4.10.7 "Adding Interrupt Queue Heads to the Periodic Schedule"
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* "The link path(s) from the periodic frame list to a queue head establishes
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* in which frames a transaction can be executed for the queue head. Queue
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* heads are linked into the periodic schedule so they are polled at
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* the appropriate rate. System software sets a bit in a queue head's
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* S-Mask to indicate which micro-frame with-in a 1 millisecond period a
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* transaction should be executed for the queue head. Software must ensure
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* that all queue heads in the periodic schedule have S-Mask set to a non-
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* zero value. An S-mask with a zero value in the context of the periodic
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* schedule yields undefined results.
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*
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* "If the desired poll rate is greater than one frame, system software can
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* use a combination of queue head linking and S-Mask values to spread
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* interrupts of equal poll rates through the schedule so that the
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* periodic bandwidth is allocated and managed in the most efficient
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* manner possible."
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*
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* Paragraph 4.6 "Periodic Schedule"
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*
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* "The periodic schedule is used to manage all isochronous and interrupt
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* transfer streams. The base of the periodic schedule is the periodic
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* frame list. Software links schedule data structures to the periodic
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* frame list to produce a graph of scheduled data structures. The graph
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* represents an appropriate sequence of transactions on the USB. ...
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* isochronous transfers (using iTDs and siTDs) with a period of one are
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* linked directly to the periodic frame list. Interrupt transfers (are
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* managed with queue heads) and isochronous streams with periods other
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* than one are linked following the period-one iTD/siTDs. Interrupt
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* queue heads are linked into the frame list ordered by poll rate.
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* Longer poll rates are linked first (e.g. closest to the periodic
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* frame list), followed by shorter poll rates, with queue heads with a
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* poll rate of one, on the very end."
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*
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* Assumption: The caller holds the EHCI exclsem. The caller must be aware
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* that the EHCI exclsem will released while waiting for the transfer to
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* complete, but will be re-aquired when before returning. The state of
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* EHCI resources could be very different upon return.
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*
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* Returned value:
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* On success, this function returns the number of bytes actually transferred.
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* For control transfers, this size includes the size of the control request
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* plus the size of the data (which could be short); For bulk transfers, this
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* will be the number of data bytes transfers (which could be short).
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*
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*******************************************************************************/
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#ifndef CONFIG_USBHOST_INT_DISABLE
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static ssize_t sam_intr_transfer(struct sam_rhport_s *rhport,
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struct sam_epinfo_s *epinfo,
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uint8_t *buffer, size_t buflen)
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{
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struct sam_qh_s *qh;
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struct sam_qtd_s *qtd;
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uintptr_t physaddr;
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uint32_t tokenbits;
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uint32_t regval;
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int ret;
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uvdbg("RHport%d EP%d: buffer=%p, buflen=%d\n",
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rhport->rhpndx+1, epinfo->epno, buffer, buflen);
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DEBUGASSERT(rhport && epinfo && buffer && buflen > 0);
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/* Set the request for the IOC event well BEFORE enabling the transfer. */
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ret = sam_ioc_setup(rhport, epinfo);
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if (ret != OK)
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{
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udbg("ERROR: Device disconnected\n");
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return ret;
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}
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/* Create and initialize a Queue Head (QH) structure for this transfer */
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qh = sam_qh_create(rhport, epinfo);
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if (qh == NULL)
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{
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udbg("ERROR: sam_qh_create failed\n");
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ret = -ENOMEM;
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goto errout_with_iocwait;
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}
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/* Extra TOKEN bits include the data toggle, the data PID, and and indication to interrupt at the end of this
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* transfer.
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*/
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tokenbits = (uint32_t)epinfo->toggle << QTD_TOKEN_TOGGLE_SHIFT;
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/* Get the data token direction. */
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if (epinfo->dirin)
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{
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tokenbits |= (QTD_TOKEN_PID_IN | QTD_TOKEN_IOC);
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}
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else
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{
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tokenbits |= (QTD_TOKEN_PID_OUT | QTD_TOKEN_IOC);
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}
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/* Allocate a new Queue Element Transfer Descriptor (qTD) for the data
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* buffer.
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*/
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qtd = sam_qtd_dataphase(epinfo, buffer, buflen, tokenbits);
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if (qtd == NULL)
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{
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udbg("ERROR: sam_qtd_dataphase failed\n");
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goto errout_with_qh;
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}
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/* Link the new qTD to the QH. */
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physaddr = sam_physramaddr((uintptr_t)qtd);
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qh->hw.overlay.nqp = sam_swap32(physaddr);
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/* Disable the periodic schedule */
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regval = sam_getreg(&HCOR->usbcmd);
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regval &= ~EHCI_USBCMD_PSEN;
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sam_putreg(regval, &HCOR->usbcmd);
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/* Add the new QH to the head of the interrupt transfer list */
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sam_qh_enqueue(&g_intrhead, qh);
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/* Re-enable the periodic schedule */
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regval |= EHCI_USBCMD_PSEN;
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sam_putreg(regval, &HCOR->usbcmd);
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/* Release the EHCI semaphore while we wait. Other threads need the
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* opportunity to access the EHCI resources while we wait.
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*
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* REVISIT: Is this safe? NO. This is a bug and needs rethinking.
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* We need to lock all of the port-resources (not EHCI common) until
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* the transfer is complete. But we can't use the common ECHI exclsem
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* or we will deadlock while waiting (because the working thread that
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* wakes this thread up needs the exclsem).
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*/
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#warning REVISIT
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sam_givesem(&g_ehci.exclsem);
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/* Wait for the IOC completion event */
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ret = sam_ioc_wait(epinfo);
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/* Re-aquire the ECHI semaphore. The caller expects to be holding
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* this upon return.
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*/
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sam_takesem(&g_ehci.exclsem);
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/* Did sam_ioc_wait() report an error? */
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if (ret < 0)
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{
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udbg("ERROR: Transfer failed\n");
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goto errout_with_iocwait;
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}
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/* Transfer completed successfully. Return the number of bytes transferred */
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return epinfo->xfrd;
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/* Clean-up after an error */
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errout_with_qh:
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sam_qh_discard(qh);
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errout_with_iocwait:
|
||||
epinfo->iocwait = false;
|
||||
return (ssize_t)ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* EHCI Interrupt Handling
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Name: sam_qh_ioccheck
|
||||
* Name: sam_qtd_ioccheck
|
||||
*
|
||||
* Description:
|
||||
* This function is a sam_qtd_foreach() callback function. It services one
|
||||
@ -2217,7 +2382,7 @@ static int sam_qh_ioccheck(struct sam_qh_s *qh, uint32_t **bp, void *arg)
|
||||
ret = sam_qtd_foreach(qh, sam_qtd_ioccheck, (void *)qh->epinfo);
|
||||
if (ret < 0)
|
||||
{
|
||||
udbg("ERROR: sam_qh_forall failed: %d\n", ret);
|
||||
udbg("ERROR: sam_qtd_foreach failed: %d\n", ret);
|
||||
}
|
||||
|
||||
/* If there is no longer anything attached to the QH, then remove it from
|
||||
@ -2300,20 +2465,61 @@ static int sam_qh_ioccheck(struct sam_qh_s *qh, uint32_t **bp, void *arg)
|
||||
|
||||
static inline void sam_ioc_bottomhalf(void)
|
||||
{
|
||||
struct sam_qh_s *qh;
|
||||
uint32_t *bp;
|
||||
int ret;
|
||||
|
||||
/* Check the Asynchronous Queue */
|
||||
/* Make sure that the head of the asynchronous queue is invalidated */
|
||||
|
||||
cp15_invalidate_dcache((uintptr_t)&g_asynchead.hw,
|
||||
(uintptr_t)&g_asynchead.hw + sizeof(struct ehci_qh_s));
|
||||
|
||||
/* Traverse all elements in the asynchronous queue */
|
||||
/* Set the back pointer to the forward qTD pointer of the asynchronous
|
||||
* queue head.
|
||||
*/
|
||||
|
||||
ret = sam_qh_forall(sam_qh_ioccheck, NULL);
|
||||
if (ret < 0)
|
||||
bp = (uint32_t *)&g_asynchead.hw.hlp;
|
||||
qh = (struct sam_qh_s *)sam_virtramaddr(sam_swap32(*bp) & QH_HLP_MASK);
|
||||
if (qh)
|
||||
{
|
||||
udbg("ERROR: sam_qh_forall failed: %d\n", ret);
|
||||
/* Then traverse and operate on every QH and qTD in the asynchronous
|
||||
* queue
|
||||
*/
|
||||
|
||||
ret = sam_qh_foreach(qh, &bp, sam_qh_ioccheck, NULL);
|
||||
if (ret < 0)
|
||||
{
|
||||
udbg("ERROR: sam_qh_foreach failed: %d\n", ret);
|
||||
}
|
||||
}
|
||||
|
||||
#ifndef CONFIG_USBHOST_INT_DISABLE
|
||||
/* Check the Interrupt Queue */
|
||||
/* Make sure that the head of the interrupt queue is invalidated */
|
||||
|
||||
cp15_invalidate_dcache((uintptr_t)&g_intrhead.hw,
|
||||
(uintptr_t)&g_intrhead.hw + sizeof(struct ehci_qh_s));
|
||||
|
||||
/* Set the back pointer to the forward qTD pointer of the asynchronous
|
||||
* queue head.
|
||||
*/
|
||||
|
||||
bp = (uint32_t *)&g_intrhead.hw.hlp;
|
||||
qh = (struct sam_qh_s *)sam_virtramaddr(sam_swap32(*bp) & QH_HLP_MASK);
|
||||
if (qh)
|
||||
{
|
||||
/* Then traverse and operate on every QH and qTD in the asynchronous
|
||||
* queue.
|
||||
*/
|
||||
|
||||
ret = sam_qh_foreach(qh, &bp, sam_qh_ioccheck, NULL);
|
||||
if (ret < 0)
|
||||
{
|
||||
udbg("ERROR: sam_qh_foreach failed: %d\n", ret);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
@ -2959,7 +3165,6 @@ static int sam_enumerate(FAR struct usbhost_connection_s *conn, int rhpndx)
|
||||
* driver sets the PortOwner bit in the PORTSC register to a one to
|
||||
* release port ownership to a companion host controller."
|
||||
*/
|
||||
#warning REVISIT
|
||||
|
||||
regval = sam_getreg(&HCOR->portsc[rhpndx]);
|
||||
if ((regval & EHCI_PORTSC_PE) != 0)
|
||||
@ -3521,8 +3726,10 @@ static int sam_transfer(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep,
|
||||
|
||||
#ifndef CONFIG_USBHOST_INT_DISABLE
|
||||
case USB_EP_ATTR_XFER_INT:
|
||||
# warning "Interrupt endpoint support not emplemented"
|
||||
nbytes = sam_intr_transfer(rhport, epinfo, buffer, buflen);
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_USBHOST_ISOC_DISABLE
|
||||
case USB_EP_ATTR_XFER_ISOC:
|
||||
# warning "Isochronous endpoint support not emplemented"
|
||||
@ -3729,16 +3936,18 @@ FAR struct usbhost_connection_s *sam_ehci_initialize(int controller)
|
||||
DEBUGASSERT((sizeof(struct sam_qh_s) & 0x1f) == 0);
|
||||
DEBUGASSERT((sizeof(struct sam_qtd_s) & 0x1f) == 0);
|
||||
|
||||
#ifndef CONFIG_USBHOST_INT_DISABLE
|
||||
DEBUGASSERT(((uintptr_t)&g_perhead & 0x1f) == 0);
|
||||
DEBUGASSERT(((uintptr_t)g_framelist & 0xfff) == 0);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SAMA5_EHCI_PREALLOCATE
|
||||
DEBUGASSERT(((uintptr_t)&g_qhpool & 0x1f) == 0);
|
||||
DEBUGASSERT(((uintptr_t)&g_qtdpool & 0x1f) == 0);
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_USBHOST_INT_DISABLE
|
||||
DEBUGASSERT(((uintptr_t)&g_intrhead & 0x1f) == 0);
|
||||
#ifdef CONFIG_SAMA5_EHCI_PREALLOCATE
|
||||
DEBUGASSERT(((uintptr_t)g_framelist & 0xfff) == 0);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* SAMA5 Configuration *******************************************************/
|
||||
/* For High-speed operations, the user has to perform the following:
|
||||
*
|
||||
@ -3873,6 +4082,20 @@ FAR struct usbhost_connection_s *sam_ehci_initialize(int controller)
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SAMA5_EHCI_PREALLOCATE
|
||||
/* Allocate the periodic framelist */
|
||||
|
||||
g_framelist = (uint32_t *)
|
||||
kmemalign(4096, FRAME_LIST_SIZE * sizeof(uint32_t));
|
||||
if (!g_framelist)
|
||||
{
|
||||
udbg("ERROR: Failed to allocate the periodic frame list\n");
|
||||
kfree(g_qhpool);
|
||||
kfree(g_qtdpool);
|
||||
return NULL;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Initialize the list of free Transfer Descriptor (qTD) structures */
|
||||
|
||||
for (i = 0; i < CONFIG_SAMA5_EHCI_NQTDS; i++)
|
||||
@ -3979,18 +4202,22 @@ FAR struct usbhost_connection_s *sam_ehci_initialize(int controller)
|
||||
sam_putreg(sam_swap32(physaddr), &HCOR->asynclistaddr);
|
||||
|
||||
#ifndef CONFIG_USBHOST_INT_DISABLE
|
||||
/* Initialize the head of the periodic list */
|
||||
/* Initialize the head of the periodic list. Since Isochronous
|
||||
* endpoints are not not yet supported, each element of the
|
||||
* frame list is initialized to point to the Interrupt Queue
|
||||
* Head (g_intrhead).
|
||||
*/
|
||||
|
||||
memset(&g_perhead, 0, sizeof(struct sam_qh_s));
|
||||
g_perhead.hw.hlp = sam_swap32(QH_HLP_T);
|
||||
g_perhead.hw.overlay.nqp = sam_swap32(QH_NQP_T);
|
||||
g_perhead.hw.overlay.alt = sam_swap32(QH_NQP_T);
|
||||
g_perhead.hw.overlay.token = sam_swap32(QH_TOKEN_HALTED);
|
||||
g_perhead.hw.epcaps = sam_swap32(QH_EPCAPS_SSMASK(1));
|
||||
memset(&g_intrhead, 0, sizeof(struct sam_qh_s));
|
||||
g_intrhead.hw.hlp = sam_swap32(QH_HLP_T);
|
||||
g_intrhead.hw.overlay.nqp = sam_swap32(QH_NQP_T);
|
||||
g_intrhead.hw.overlay.alt = sam_swap32(QH_NQP_T);
|
||||
g_intrhead.hw.overlay.token = sam_swap32(QH_TOKEN_HALTED);
|
||||
g_intrhead.hw.epcaps = sam_swap32(QH_EPCAPS_SSMASK(1));
|
||||
|
||||
/* Attach the periodic QH to Period Frame List */
|
||||
|
||||
physaddr = sam_physramaddr((uintptr_t)&g_perhead);
|
||||
physaddr = sam_physramaddr((uintptr_t)&g_intrhead);
|
||||
for (i = 0; i < FRAME_LIST_SIZE; i++)
|
||||
{
|
||||
g_framelist[i] = sam_swap32(physaddr) | PFL_TYP_QH;
|
||||
@ -3998,15 +4225,18 @@ FAR struct usbhost_connection_s *sam_ehci_initialize(int controller)
|
||||
|
||||
/* Set the Periodic Frame List Base Address. */
|
||||
|
||||
cp15_clean_dcache((uintptr_t)&g_perhead.hw,
|
||||
(uintptr_t)&g_perhead.hw + sizeof(struct ehci_qh_s));
|
||||
cp15_clean_dcache((uintptr_t)&g_intrhead.hw,
|
||||
(uintptr_t)&g_intrhead.hw + sizeof(struct ehci_qh_s));
|
||||
cp15_clean_dcache((uintptr_t)g_framelist,
|
||||
(uintptr_t)g_framelist + FRAME_LIST_SIZE * sizeof(uint32_t));
|
||||
|
||||
physaddr = sam_physramaddr((uintptr_t)g_framelist);
|
||||
sam_putreg(sam_swap32(physaddr), &HCOR->periodiclistbase);
|
||||
#endif
|
||||
|
||||
/* Enable the asynchronous schedule and, possibly set the frame list size */
|
||||
/* Enable the asynchronous schedule and, possibly enable the periodic
|
||||
* schedule and set the frame list size.
|
||||
*/
|
||||
|
||||
regval = sam_getreg(&HCOR->usbcmd);
|
||||
regval &= ~(EHCI_USBCMD_HCRESET | EHCI_USBCMD_FLSIZE_MASK |
|
||||
@ -4015,6 +4245,7 @@ FAR struct usbhost_connection_s *sam_ehci_initialize(int controller)
|
||||
regval |= EHCI_USBCMD_ASEN;
|
||||
|
||||
#ifndef CONFIG_USBHOST_INT_DISABLE
|
||||
regval |= EHCI_USBCMD_PSEN;
|
||||
# if FRAME_LIST_SIZE == 1024
|
||||
regval |= EHCI_USBCMD_FLSIZE_1024;
|
||||
# elif FRAME_LIST_SIZE == 512
|
||||
|
||||
@ -1207,6 +1207,8 @@ Configurations
|
||||
: Defaults for values probably OK for both
|
||||
Device Drivers
|
||||
CONFIG_USBHOST=y : Enable USB host support
|
||||
CONFIG_USBHOST_INT_DISABLE=y : Interrupt endpoints not needed
|
||||
CONFIG_USBHOST_ISOC_DISABLE=y : Isochronous endpoints not needed
|
||||
|
||||
Device Drivers -> USB Host Driver Support
|
||||
CONFIG_USBHOST_ISOC_DISABLE=y : Isochronous endpoints not used
|
||||
@ -1215,8 +1217,8 @@ Configurations
|
||||
Library Routines
|
||||
CONFIG_SCHED_WORKQUEUE : Worker thread support is required
|
||||
|
||||
Application Configuration -> NSH Library
|
||||
CONFIG_NSH_ARCHINIT=y : NSH board-initialization
|
||||
Application Configuration -> NSH Library
|
||||
CONFIG_NSH_ARCHINIT=y : NSH board-initialization
|
||||
|
||||
STATUS:
|
||||
2013-7-19: This configuration (as do the others) run at 396MHz.
|
||||
@ -1283,13 +1285,13 @@ Configurations
|
||||
2013-8-20: Added description to add EHCI to the configuration. At
|
||||
present, however, EHCI is still a work in progress and not ready for
|
||||
prime time.
|
||||
2013-8-26: EHCI is still non-functional. After days of work, it is
|
||||
able to exchange a SETUP transfer or two, but it still does not make
|
||||
it through the full enumeration sequence.
|
||||
Nor does the hand-off of high speed devices to OHCI work. In this
|
||||
case, OHCI gets the port, but the port is reset, lost by OCHI and
|
||||
returned to EHCI. EHCI sees the full-speed port and hands it off
|
||||
to OHCI and this sequence continues forever.
|
||||
2013-8-26:
|
||||
The hand-off of full speed devices to OHCI does not work. In this
|
||||
case, OHCI gets the port, but the port is reset, lost by OHCI and
|
||||
returned to EHCI. EHCI sees the full-speed port and hands it off to
|
||||
OHCI and this sequence continues forever.
|
||||
2013-8-28: EHCI is partially functional. It is able to mount a high-
|
||||
speed USB FLASH drive using the Mass Storage Class (MSC) interface.
|
||||
|
||||
ostest:
|
||||
This configuration directory, performs a simple OS test using
|
||||
|
||||
Loading…
Reference in New Issue
Block a user