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SVC is the preferred mnemonic vs. SWI for cortex A

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This commit is contained in:
Gregory Nutt 2014-01-05 16:21:41 -06:00
parent 0673a9564c
commit e86f940374
3 changed files with 15 additions and 15 deletions
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6
arch/arm/src/armv7-a/arm_syscall.c
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@ -79,11 +79,11 @@
* Name: arm_syscall
*
* Description:
* SWI interrupts will vection here with insn=the SWI instruction and
* SVC interrupts will vector here with insn=the SVC instruction and
* xcp=the interrupt context
*
* The handler may get the SWI number be de-referencing the return
* address saved in the xcp and decoding the SWI instruction
* The handler may get the SVC number be de-referencing the return
* address saved in the xcp and decoding the SVC instruction
*
****************************************************************************/

16
arch/arm/src/armv7-a/arm_vectors.S
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@ -168,17 +168,17 @@ arm_vectorirq:
.align 5
/************************************************************************************
* Function: arm_vectorswi
* Function: arm_vectorsvc
*
* Description:
* SWI interrupt. We enter the SWI in SVC mode.
* SVC interrupt. We enter the SVC in SVC mode.
*
************************************************************************************/
.globl arm_vectorswi
.type arm_vectorswi, %function
.globl arm_vectorsvc
.type arm_vectorsvc, %function
arm_vectorswi:
arm_vectorsvc:
/* Create a context structure. First set aside a stack frame
* and store r0-r12 into the frame.
@ -191,14 +191,14 @@ arm_vectorswi:
* and CPSR in r1-r4 */
add r1, sp, #XCPTCONTEXT_SIZE
mov r2, r14 /* R14 is altered on return from SWI */
mov r2, r14 /* R14 is altered on return from SVC */
mov r3, r14 /* Save r14 as the PC as well */
mrs r4, spsr /* Get the saved CPSR */
add r0, sp, #(4*REG_SP) /* Offset to pc, cpsr storage */
stmia r0, {r1-r4}
/* Then call the SWI handler with interrupts disabled.
/* Then call the SVC handler with interrupts disabled.
* void arm_syscall(struct xcptcontext *xcp)
*/
@ -220,7 +220,7 @@ arm_vectorswi:
ldr r1, [r0, #(4*REG_CPSR)] /* Setup the SVC mode SPSR */
msr spsr, r1
ldmia r0, {r0-r15}^ /* Return */
.size arm_vectorswi, . - arm_vectorswi
.size arm_vectorsvc, . - arm_vectorsvc
.align 5

8
arch/arm/src/armv7-a/arm_vectortab.S
View File

@ -71,7 +71,7 @@
_vector_start:
ldr pc, .Lresethandler /* 0x00: Reset */
ldr pc, .Lundefinedhandler /* 0x04: Undefined instruction */
ldr pc, .Lswihandler /* 0x08: Software interrupt */
ldr pc, .Lsvchandler /* 0x08: Software interrupt */
ldr pc, .Lprefetchaborthandler /* 0x0c: Prefetch abort */
ldr pc, .Ldataaborthandler /* 0x10: Data abort */
ldr pc, .Laddrexcptnhandler /* 0x14: Address exception (reserved) */
@ -80,7 +80,7 @@ _vector_start:
.globl __start
.globl arm_vectorundefinsn
.globl arm_vectorswi
.globl arm_vectorsvc
.globl arm_vectorprefetch
.globl arm_vectordata
.globl arm_vectoraddrexcptn
@ -91,8 +91,8 @@ _vector_start:
.long __start
.Lundefinedhandler:
.long arm_vectorundefinsn
.Lswihandler:
.long arm_vectorswi
.Lsvchandler:
.long arm_vectorsvc
.Lprefetchaborthandler:
.long arm_vectorprefetch
.Ldataaborthandler: