From e89432b56317ef19b1f08daa11d82a7e34daef3b Mon Sep 17 00:00:00 2001 From: Fotis Panagiotopoulos Date: Thu, 27 Oct 2022 13:37:24 +0300 Subject: [PATCH] Added DHCSR definitions for ARMv7 & ARMv8. --- arch/arm/src/armv7-m/nvic.h | 17 +++++++++++++++++ arch/arm/src/armv8-m/nvic.h | 23 +++++++++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/arch/arm/src/armv7-m/nvic.h b/arch/arm/src/armv7-m/nvic.h index 4ed1b4d394..a1a77bec22 100644 --- a/arch/arm/src/armv7-m/nvic.h +++ b/arch/arm/src/armv7-m/nvic.h @@ -694,6 +694,23 @@ # define NVIC_CPACR_CP_PRIV(n) (1 << NVIC_CPACR_CP_SHIFT(n)) # define NVIC_CPACR_CP_FULL(n) (3 << NVIC_CPACR_CP_SHIFT(n)) +/* Debug Halting Control and Status Register (DHCSR) */ + +#define NVIC_DHCSR_C_DEBUGEN (1 << 0) /* Bit 0: Enables debug. */ +#define NVIC_DHCSR_C_HALT (1 << 1) /* Bit 1: Halts the core. */ +#define NVIC_DHCSR_C_STEP (1 << 2) /* Bit 2: Steps the core in halted debug. */ +#define NVIC_DHCSR_C_MASKINTS (1 << 3) /* Bit 3: Mask interrupts when stepping or running in halted debug. */ +#define NVIC_DHCSR_C_SNAPSTALL (1 << 5) /* Bit 5: If the core is stalled on a load/store operation the stall ceases and the instruction is forced to complete. */ +#define NVIC_DHCSR_S_REGRDY (1 << 16) /* Bit 16: Register Read/Write on the Debug Core Register Selector register is available. */ +#define NVIC_DHCSR_S_HALT (1 << 17) /* Bit 17: The core is in debug state when S_HALT is set. */ +#define NVIC_DHCSR_S_SLEEP (1 << 18) /* Bit 18: Indicates that the core is sleeping (WFI, WFE or SLEEP-ON-EXIT). */ +#define NVIC_DHCSR_S_LOCKUP (1 << 19) /* Bit 19: Reads as one if the core is running (not halted) and a lockup condition is present. */ +#define NVIC_DHCSR_S_RETIRE_ST (1 << 24) /* Bit 24: Indicates that an instruction has completed since last read. */ +#define NVIC_DHCSR_S_RESET_ST (1 << 25) /* Bit 25: Indicates that the core has been reset, or is now being reset, since the last time this bit was read. */ +#define NVIC_DHCSR_DBGKEY_SHIFT (16) /* Bits 16:31: Key to prevent inadvertent writes. */ +#define NVIC_DHCSR_DBGKEY_MASK (0xffff << NVIC_DHCSR_DBGKEY_SHIFT) +# define NVIC_DHCSR_DBGKEY_VALUE (0xa05f) + /* Debug Exception and Monitor Control Register (DEMCR) */ #define NVIC_DEMCR_VCCORERESET (1 << 0) /* Bit 0: Reset Vector Catch */ diff --git a/arch/arm/src/armv8-m/nvic.h b/arch/arm/src/armv8-m/nvic.h index f10362e03d..722706e5a9 100644 --- a/arch/arm/src/armv8-m/nvic.h +++ b/arch/arm/src/armv8-m/nvic.h @@ -796,6 +796,29 @@ # define NVIC_NSACR_CP_SECURE(n) (0 << NVIC_CPACR_CP_SHIFT(n)) # define NVIC_NSACR_CP_FULL(n) (1 << NVIC_CPACR_CP_SHIFT(n)) +/* Debug Halting Control and Status Register (DHCSR) */ + +#define NVIC_DHCSR_C_DEBUGEN (1 << 0) /* Bit 0: Enables debug. */ +#define NVIC_DHCSR_C_HALT (1 << 1) /* Bit 1: Halts the core. */ +#define NVIC_DHCSR_C_STEP (1 << 2) /* Bit 2: Steps the core in halted debug. */ +#define NVIC_DHCSR_C_MASKINTS (1 << 3) /* Bit 3: Mask interrupts when stepping or running in halted debug. */ +#define NVIC_DHCSR_C_SNAPSTALL (1 << 5) /* Bit 5: If the core is stalled on a load/store operation the stall ceases and the instruction is forced to complete. */ +#define NVIC_DHCSR_C_PMOV (1 << 6) /* Bit 6: Halt on PMU overflow control. */ +#define NVIC_DHCSR_S_REGRDY (1 << 16) /* Bit 16: Register Read/Write on the Debug Core Register Selector register is available. */ +#define NVIC_DHCSR_S_HALT (1 << 17) /* Bit 17: The core is in debug state when S_HALT is set. */ +#define NVIC_DHCSR_S_SLEEP (1 << 18) /* Bit 18: Indicates that the core is sleeping (WFI, WFE or SLEEP-ON-EXIT). */ +#define NVIC_DHCSR_S_LOCKUP (1 << 19) /* Bit 19: Reads as one if the core is running (not halted) and a lockup condition is present. */ +#define NVIC_DHCSR_S_SDE (1 << 20) /* Bit 20: Secure debug enable. */ +#define NVIC_DHCSR_S_NSUIDE (1 << 21) /* Bit 21: Non-secure unprivileged halting debug enabled. */ +#define NVIC_DHCSR_S_SUIDE (1 << 22) /* Bit 22: Secure unprivileged halting debug enabled. */ +#define NVIC_DHCSR_S_FPD (1 << 23) /* Bit 23: Floating-point registers debuggable. */ +#define NVIC_DHCSR_S_RETIRE_ST (1 << 24) /* Bit 24: Indicates that an instruction has completed since last read. */ +#define NVIC_DHCSR_S_RESET_ST (1 << 25) /* Bit 25: Indicates that the core has been reset, or is now being reset, since the last time this bit was read. */ +#define NVIC_DHCSR_S_RESTART_ST (1 << 26) /* Bit 26: Restart sticky status. */ +#define NVIC_DHCSR_DBGKEY_SHIFT (16) /* Bits 16:31: Key to prevent inadvertent writes. */ +#define NVIC_DHCSR_DBGKEY_MASK (0xffff << NVIC_DHCSR_DBGKEY_SHIFT) +# define NVIC_DHCSR_DBGKEY_VALUE (0xa05f) + /* Debug Exception and Monitor Control Register (DEMCR) */ #define NVIC_DEMCR_VCCORERESET (1 << 0) /* Bit 0: Reset Vector Catch */