esp32: enable APP_CPU cache earlier
NuttX uses PSRAM, possibly using the APP_CPU cache MMU, way before starting the APP_CPU in up_cpu_start(). Flushing the cache when launching the APP_CPU can cause data corruptions on PSRAM. Eg. mm_heap structures if the PSRAM is added to a heap.
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@ -57,8 +57,6 @@ static volatile spinlock_t g_appcpu_interlock;
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* ROM function prototypes
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****************************************************************************/
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extern void cache_flush(int cpu);
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extern void cache_read_enable(int cpu);
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extern void ets_set_appcpu_boot_addr(uint32_t start);
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/****************************************************************************
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@ -245,11 +243,6 @@ int up_cpu_start(int cpu)
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spin_initialize(&g_appcpu_interlock, SP_LOCKED);
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/* Flush and enable I-cache for APP CPU */
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cache_flush(cpu);
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cache_read_enable(cpu);
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/* Unstall the APP CPU */
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regval = getreg32(RTC_CNTL_SW_CPU_STALL_REG);
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@ -68,6 +68,13 @@
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# error "FLASH speed can only be equal to or higher than SRAM speed while SRAM is enabled!"
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#endif
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/****************************************************************************
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* ROM Function Prototypes
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****************************************************************************/
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extern void cache_flush(int cpu);
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extern void cache_read_enable(int cpu);
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/****************************************************************************
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* Private Data
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****************************************************************************/
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@ -238,6 +245,8 @@ void IRAM_ATTR esp_spiram_init_cache(void)
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/* Flush and enable icache for APP CPU */
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#ifdef CONFIG_SMP
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cache_flush(APP_CPU_NUM);
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cache_read_enable(APP_CPU_NUM);
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regval = getreg32(DPORT_APP_CACHE_CTRL1_REG);
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regval &= ~(1 << DPORT_APP_CACHE_MASK_DRAM1);
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putreg32(regval, DPORT_APP_CACHE_CTRL1_REG);
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