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esp32c3: Always reserve CPU INT 0 and fix cpu init order

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Co-author: Tiago Medicci <tiago.medicci@espressif.com>
Co-author: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
This commit is contained in:
Alan Carvalho de Assis 2023-02-01 17:38:12 -03:00 committed by Xiang Xiao
parent 8845e6bb38
commit e950e53df2
2 changed files with 16 additions and 22 deletions
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12
arch/risc-v/include/esp32c3/irq.h
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@ -46,8 +46,7 @@
/* RESERVED interrupts: 0 to 14 */
#define ESP32C3_PERIPH_MAC 0 /* Reserved, but needed by WiFi driver */
#define ESP32C3_PERIPH_MAC_NMI 1 /* Reserved, but needed by WiFi driver */
#define ESP32C3_PERIPH_WMAC 1 /* Reserved, but needed by WiFi driver */
#define ESP32C3_PERIPH_BT_BB 5 /* Reserved, but needed by BLE driver */
#define ESP32C3_PERIPH_RWBLE 8 /* Reserved, but needed by BLE driver */
@ -119,11 +118,7 @@
#define ESP32C3_NCPUINTS 32
#define ESP32C3_CPUINT_MAX (ESP32C3_NCPUINTS - 1)
#define ESP32C3_CPUINT_MAC 0
#define ESP32C3_CPUINT_MAC_NMI 1
#define ESP32C3_CPUINT_BT_BB 5
#define ESP32C3_CPUINT_RWBLE_IRQ 8
#define ESP32C3_CPUINT_ALWAYS_RSVD 0
#define ESP32C3_CPUINT_PERIPHSET 0xffffffff
@ -149,8 +144,7 @@
/* Peripheral IRQs */
#define ESP32C3_IRQ_MAC (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_MAC)
#define ESP32C3_IRQ_MAC_NMI (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_MAC_NMI)
#define ESP32C3_IRQ_WMAC (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_WMAC)
#define ESP32C3_IRQ_BT_BB (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_BT_BB)
#define ESP32C3_IRQ_RWBLE (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_RWBLE)

26
arch/risc-v/src/esp32c3/esp32c3_irq.c
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@ -82,10 +82,10 @@
#define ESP32C3_PRIO_INDEX(p) ((p) - ESP32C3_MIN_PRIORITY)
#ifdef CONFIG_ESP32C3_WIFI
# define ESP32C3_WIFI_RESERVE_INT ((1 << ESP32C3_CPUINT_MAC | \
1 << ESP32C3_CPUINT_MAC_NMI))
# define ESP32C3_WIFI_RESERVE_INT ((1 << ESP32C3_CPUINT_ALWAYS_RSVD | \
1 << ESP32C3_CPUINT_WMAC))
#else
# define ESP32C3_WIFI_RESERVE_INT 0
# define ESP32C3_WIFI_RESERVE_INT (1 << ESP32C3_CPUINT_ALWAYS_RSVD)
#endif
/****************************************************************************
@ -196,11 +196,15 @@ void up_irqinitialize(void)
g_irqmap[i] = IRQ_UNMAPPED;
}
/* Initialize CPU interrupts */
esp32c3_cpuint_initialize();
/* Hard code special cases. */
#ifdef CONFIG_ESP32C3_WIFI
g_irqmap[ESP32C3_IRQ_MAC_NMI] = ESP32C3_CPUINT_MAC_NMI;
g_cpu_intmap[ESP32C3_CPUINT_MAC_NMI] = CPUINT_ASSIGN(ESP32C3_IRQ_MAC_NMI);
g_irqmap[ESP32C3_IRQ_WMAC] = ESP32C3_CPUINT_WMAC;
g_cpu_intmap[ESP32C3_CPUINT_WMAC] = CPUINT_ASSIGN(ESP32C3_IRQ_WMAC);
#endif
#ifdef CONFIG_ESP32C3_BLE
@ -211,10 +215,6 @@ void up_irqinitialize(void)
g_cpu_intmap[ESP32C3_CPUINT_RWBLE] = CPUINT_ASSIGN(ESP32C3_IRQ_RWBLE);
#endif
/* Initialize CPU interrupts */
esp32c3_cpuint_initialize();
/* Attach the common interrupt handler */
riscv_exception_attach();
@ -248,7 +248,7 @@ void up_enable_irq(int irq)
irqinfo("irq=%d | cpuint=%d \n", irq, cpuint);
DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32C3_CPUINT_MAX);
DEBUGASSERT(cpuint >= 1 && cpuint <= ESP32C3_CPUINT_MAX);
irqstate = enter_critical_section();
setbits(1 << cpuint, INTERRUPT_CPU_INT_ENABLE_REG);
@ -269,7 +269,7 @@ void up_disable_irq(int irq)
irqinfo("irq=%d | cpuint=%d \n", irq, cpuint);
DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32C3_CPUINT_MAX);
DEBUGASSERT(cpuint >= 1 && cpuint <= ESP32C3_CPUINT_MAX);
if (cpuint == IRQ_UNMAPPED)
{
@ -358,7 +358,7 @@ int esp32c3_cpuint_initialize(void)
{
/* Disable all CPU interrupts on this CPU */
for (int i = 0; i < ESP32C3_NCPUINTS; i++)
for (int i = 1; i <= ESP32C3_CPUINT_MAX; i++)
{
putreg32(0, INTERRUPT_CPU_INT_PRI_0_REG + i * 4);
}
@ -473,7 +473,7 @@ int esp32c3_setup_irq(int periphid, int priority, int type)
irq = ESP32C3_PERIPH2IRQ(periphid);
DEBUGASSERT(periphid >= 0 && periphid < ESP32C3_NPERIPHERALS);
DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32C3_CPUINT_MAX);
DEBUGASSERT(cpuint >= 1 && cpuint <= ESP32C3_CPUINT_MAX);
DEBUGASSERT(g_cpu_intmap[cpuint] == CPUINT_UNASSIGNED);
g_cpu_intmap[cpuint] = CPUINT_ASSIGN(periphid + ESP32C3_IRQ_FIRSTPERIPH);