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Fix warnings and remove not used function

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This commit is contained in:
Alan C. Assis 2020-10-16 13:31:35 -03:00 committed by Abdelatif Guettouche
parent fdc44dc6fc
commit e956c3d1d3
4 changed files with 44 additions and 65 deletions
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19
arch/xtensa/src/esp32/esp32_psram.c
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@ -253,7 +253,7 @@ struct rtc_vddsdio_config_s
* Private Data
****************************************************************************/
static psram_cache_mode_t s_psram_mode = PSRAM_CACHE_MAX;
static int s_psram_mode = PSRAM_CACHE_MAX;
static psram_clk_mode_t s_clk_mode = PSRAM_CLK_MODE_DCLK;
static uint64_t s_psram_id = 0;
static bool s_2t_mode_enabled = false;
@ -275,8 +275,8 @@ static int IRAM_ATTR esp32_get_vddsdio_config(
struct rtc_vddsdio_config_s *config);
static void IRAM_ATTR
psram_cache_init(psram_cache_mode_t psram_cache_mode,
psram_vaddr_mode_t vaddrmode);
psram_cache_init(int psram_cache_mode,
int vaddrmode);
static void psram_clear_spi_fifo(psram_spi_num_t spi_num);
@ -305,6 +305,7 @@ static void psram_read_id(uint64_t *dev_id);
static int IRAM_ATTR
psram_enable_qio_mode(psram_spi_num_t spi_num);
#if defined(CONFIG_ESP32_SPIRAM_2T_MODE)
static void spi_user_psram_write(psram_spi_num_t spi_num, uint32_t address,
uint32_t *data_buffer, uint32_t data_len);
@ -315,6 +316,7 @@ static int IRAM_ATTR
psram_2t_mode_enable(psram_spi_num_t spi_num);
static int psram_2t_mode_check(psram_spi_num_t spi_num);
#endif
/****************************************************************************
* ROM function prototypes
@ -1052,7 +1054,7 @@ void psram_set_cs_timing(psram_spi_num_t spi_num, psram_clk_mode_t clk_mode)
/* spi param init for psram */
void IRAM_ATTR
psram_spi_init(psram_spi_num_t spi_num, psram_cache_mode_t mode)
psram_spi_init(psram_spi_num_t spi_num, int mode)
{
modifyreg32(SPI_SLAVE_REG(spi_num), SPI_TRANS_DONE << 5, 0);
@ -1086,7 +1088,7 @@ psram_spi_init(psram_spi_num_t spi_num, psram_cache_mode_t mode)
*/
static void IRAM_ATTR psram_gpio_config(psram_io_t *psram_io,
psram_cache_mode_t mode)
int mode)
{
int spi_cache_dummy = 0;
uint32_t rd_mode_reg = getreg32(SPI_CTRL_REG(0));
@ -1236,7 +1238,7 @@ static void IRAM_ATTR psram_gpio_config(psram_io_t *psram_io,
#endif
}
psram_size_t psram_get_size(void)
int psram_get_size(void)
{
if ((PSRAM_SIZE_ID(s_psram_id) == PSRAM_EID_SIZE_64MBITS) ||
PSRAM_IS_64MBIT_TRIAL(s_psram_id))
@ -1277,7 +1279,7 @@ bool psram_is_32mbit_ver0(void)
*/
int IRAM_ATTR
psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vaddrmode) /* psram init */
psram_enable(int mode, int vaddrmode) /* psram init */
{
struct rtc_vddsdio_config_s cfg;
@ -1546,8 +1548,7 @@ psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vaddrmode) /* psram i
/* register initialization for sram cache params and r/w commands */
static void IRAM_ATTR
psram_cache_init(psram_cache_mode_t psram_cache_mode,
psram_vaddr_mode_t vaddrmode)
psram_cache_init(int psram_cache_mode, int vaddrmode)
{
uint32_t regval;

51
arch/xtensa/src/esp32/esp32_psram.h
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@ -25,21 +25,15 @@
* Included Files
****************************************************************************/
typedef enum
{
PSRAM_CACHE_F80M_S40M = 0,
PSRAM_CACHE_F40M_S40M,
PSRAM_CACHE_F80M_S80M,
PSRAM_CACHE_MAX,
} psram_cache_mode_t;
#define PSRAM_CACHE_F80M_S40M 0
#define PSRAM_CACHE_F40M_S40M 1
#define PSRAM_CACHE_F80M_S80M 2
#define PSRAM_CACHE_MAX 3
typedef enum
{
PSRAM_SIZE_16MBITS = 0,
PSRAM_SIZE_32MBITS = 1,
PSRAM_SIZE_64MBITS = 2,
PSRAM_SIZE_MAX,
} psram_size_t;
#define PSRAM_SIZE_16MBITS 0
#define PSRAM_SIZE_32MBITS 1
#define PSRAM_SIZE_64MBITS 2
#define PSRAM_SIZE_MAX 3
/* See the TRM, chapter PID/MPU/MMU, header 'External RAM' for the
* definitions of these modes. Important is that NORMAL works with the app
@ -48,20 +42,18 @@ typedef enum
* issues but cannot be used when the app CPU cache is disabled.
*/
typedef enum
{
PSRAM_VADDR_MODE_NORMAL = 0, /* App and Pro CPU use their own flash cache
* for external RAM access
*/
#define PSRAM_VADDR_MODE_NORMAL 0 /* App and Pro CPU use their own flash
* cache for external RAM access
*/
PSRAM_VADDR_MODE_LOWHIGH, /* App and Pro CPU share external RAM caches:
* pro CPU has low 2M, app CPU has high 2M
*/
PSRAM_VADDR_MODE_EVENODD, /* App and Pro CPU share external RAM caches:
* pro CPU does even 32yte ranges, app does
* odd ones.
*/
} psram_vaddr_mode_t;
#define PSRAM_VADDR_MODE_LOWHIGH 1 /* App and Pro CPU share external RAM caches:
* pro CPU has low 2M, app CPU has high 2M
*/
#define PSRAM_VADDR_MODE_EVENODD 2 /* App and Pro CPU share external RAM caches:
* pro CPU does even 32yte ranges, app does
* odd ones.
*/
/* Description: Get PSRAM size
* return:
@ -69,7 +61,7 @@ typedef enum
* - PSRAM size
*/
psram_size_t psram_get_size(void);
int psram_get_size(void);
/* Description: PSRAM cache enable function
*
@ -85,7 +77,6 @@ psram_size_t psram_get_size(void);
* claimed.
*/
int psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t
vaddrmode);
int psram_enable(int mode, int vaddrmode);
#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_HIMEM_H */

20
arch/xtensa/src/esp32/esp32_spiram.c
View File

@ -93,18 +93,6 @@ size_t __attribute__((weak)) esp_himem_reserved_area_size(void)
return 0;
}
static int spiram_size_usable_for_malloc(void)
{
int s = esp_spiram_get_size();
if (s > 4 * 1024 * 1024)
{
s = 4 * 1024 * 1024; /* we can map at most 4MiB */
}
return s - esp_himem_reserved_area_size();
}
/****************************************************************************
* Public Functions
****************************************************************************/
@ -124,15 +112,17 @@ void IRAM_ATTR esp_spiram_init_cache(void)
#endif
}
esp_spiram_size_t esp_spiram_get_chip_size(void)
int esp_spiram_get_chip_size(void)
{
int psram_size;
if (!spiram_inited)
{
merr("SPI RAM not initialized");
return ESP_SPIRAM_SIZE_INVALID;
}
psram_size_t psram_size = psram_get_size();
psram_size = psram_get_size();
switch (psram_size)
{
case PSRAM_SIZE_16MBITS:
@ -249,7 +239,7 @@ int esp_spiram_reserve_dma_pool(size_t size)
size_t esp_spiram_get_size(void)
{
psram_size_t size = esp_spiram_get_chip_size();
int size = esp_spiram_get_chip_size();
if (size == PSRAM_SIZE_16MBITS)
{

19
arch/xtensa/src/esp32/esp32_spiram.h
View File

@ -30,13 +30,10 @@
#include <stdbool.h>
#include "xtensa_attr.h"
typedef enum
{
ESP_SPIRAM_SIZE_16MBITS = 0, /* SPI RAM size is 16 MBits */
ESP_SPIRAM_SIZE_32MBITS = 1, /* SPI RAM size is 32 MBits */
ESP_SPIRAM_SIZE_64MBITS = 2, /* SPI RAM size is 64 MBits */
ESP_SPIRAM_SIZE_INVALID, /* SPI RAM size is invalid */
} esp_spiram_size_t;
#define ESP_SPIRAM_SIZE_16MBITS 0 /* SPI RAM size is 16 MBits */
#define ESP_SPIRAM_SIZE_32MBITS 1 /* SPI RAM size is 32 MBits */
#define ESP_SPIRAM_SIZE_64MBITS 2 /* SPI RAM size is 64 MBits */
#define ESP_SPIRAM_SIZE_INVALID 3 /* SPI RAM size is invalid */
/* Description: get SPI RAM size
* return
@ -44,7 +41,7 @@ typedef enum
* - SPI RAM size
*/
esp_spiram_size_t esp_spiram_get_chip_size(void);
int esp_spiram_get_chip_size(void);
/* Description: Initialize spiram interface/hardware. Normally called from
* cpu_start.c.
@ -58,9 +55,9 @@ int esp_spiram_init(void);
/* Description: Configure Cache/MMU for access to external SPI RAM.
*
* Normally this function is called from cpu_start, if
* CONFIG_ESP32_SPIRAM_BOOT_INIT option is enabled. Applications which need to
* enable SPI RAM at run time can disable CONFIG_ESP32_SPIRAM_BOOT_INIT, and
* call this function later.
* CONFIG_ESP32_SPIRAM_BOOT_INIT option is enabled. Applications which need
* to enable SPI RAM at run time can disable CONFIG_ESP32_SPIRAM_BOOT_INIT,
* and call this function later.
*
* Attention this function must be called with flash cache disabled.
*/