Add STR71x serial driver
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1110 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
07dbb2ef5f
commit
e97446cd54
@ -47,9 +47,9 @@ ifneq ($(CONFIG_DISABLE_SIGNALS),y)
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CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c
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endif
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CHIP_ASRCS = str71x_lowputc.S
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CHIP_CSRCS = str71x_prccu.c str71x_decodeirq.c str71x_irq.c str71x_timerisr.c \
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str71x_serial.c
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CHIP_ASRCS =
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CHIP_CSRCS = str71x_prccu.c str71x_lowputc.c str71x_decodeirq.c str71x_irq.c \
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str71x_timerisr.c str71x_serial.c
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ifeq ($(CONFIG_USBDEV),y)
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CHIP_CSRCS += str71x_usbdev.c
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@ -57,10 +57,25 @@
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/* GPIO register addresses **********************************************************/
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#define STR71X_GPIO_PC0 (STR71X_GPIO_BASE + STR71X_GPIO_PC0_OFFSET)
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#define STR71X_GPIO_PC1 (STR71X_GPIO_BASE + STR71X_GPIO_PC1_OFFSET)
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#define STR71X_GPIO_PC2 (STR71X_GPIO_BASE + STR71X_GPIO_PC2_OFFSET)
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#define STR71X_GPIO_PD (STR71X_GPIO_BASE + STR71X_GPIO_PD_OFFSET)
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#define STR71X_GPIO_PC0(b) ((b) + STR71X_GPIO_PC0_OFFSET)
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#define STR71X_GPIO_PC1(b) ((b) + STR71X_GPIO_PC1_OFFSET)
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#define STR71X_GPIO_PC2(b) ((b) + STR71X_GPIO_PC2_OFFSET)
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#define STR71X_GPIO_PD(b) ((b) + STR71X_GPIO_PD_OFFSET)
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#define STR71X_GPIO0_PC0 (STR71X_GPIO0_BASE + STR71X_GPIO_PC0_OFFSET)
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#define STR71X_GPIO0_PC1 (STR71X_GPIO0_BASE + STR71X_GPIO_PC1_OFFSET)
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#define STR71X_GPIO0_PC2 (STR71X_GPIO0_BASE + STR71X_GPIO_PC2_OFFSET)
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#define STR71X_GPIO0_PD (STR71X_GPIO0_BASE + STR71X_GPIO_PD_OFFSET)
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#define STR71X_GPIO1_PC0 (STR71X_GPIO1_BASE + STR71X_GPIO_PC0_OFFSET)
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#define STR71X_GPIO1_PC1 (STR71X_GPIO1_BASE + STR71X_GPIO_PC1_OFFSET)
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#define STR71X_GPIO1_PC2 (STR71X_GPIO1_BASE + STR71X_GPIO_PC2_OFFSET)
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#define STR71X_GPIO1_PD (STR71X_GPIO1_BASE + STR71X_GPIO_PD_OFFSET)
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#define STR71X_GPIO2_PC0 (STR71X_GPIO2_BASE + STR71X_GPIO_PC0_OFFSET)
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#define STR71X_GPIO2_PC1 (STR71X_GPIO2_BASE + STR71X_GPIO_PC1_OFFSET)
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#define STR71X_GPIO2_PC2 (STR71X_GPIO2_BASE + STR71X_GPIO_PC2_OFFSET)
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#define STR71X_GPIO2_PD (STR71X_GPIO2_BASE + STR71X_GPIO_PD_OFFSET)
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/* Register bit settings ************************************************************/
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@ -553,7 +553,7 @@ __flashstart:
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bl str71x_prccuinit
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/* Configure the uart so that we can get debug output as soon
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* as possible. Modifies r0, r1, r2, and r14.
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* as possible.
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*/
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bl up_lowsetup
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334
arch/arm/src/str71x/str71x_lowputc.c
Normal file
334
arch/arm/src/str71x/str71x_lowputc.c
Normal file
@ -0,0 +1,334 @@
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/**************************************************************************
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* arch/arm/src/str71x/str71x_lowputc.c
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*
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* Copyright (C) 2008 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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**************************************************************************/
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/**************************************************************************
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* Included Files
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**************************************************************************/
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#include <nuttx/config.h>
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#include "up_internal.h"
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#include "up_arch.h"
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#include "chp.h"
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/**************************************************************************
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* Private Definitions
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**************************************************************************/
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/* Configuration **********************************************************/
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/* Is there a UART enabled? */
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#if defined(CONFIG_STR71X_UART0) || defined(CONFIG_STR71X_UART1) || \
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defined(CONFIG_STR71X_UART2) || defined(CONFIG_STR71X_UART3))
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# define HAVE_UART 1
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/* Is there a serial console? */
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# if defined(CONFIG_UART0_SERIAL_CONSOLE) || defined(CONFIG_UART1_SERIAL_CONSOLE) ||\
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defined(CONFIG_UART2_SERIAL_CONSOLE) || defined(CONFIG_UART3_SERIAL_CONSOLE)
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# define HAVE_CONSOLE
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# else
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# undef HAVE_CONSOLE
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# endif
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#else
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# undef HAVE_UART
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# undef HAVE_CONSOLE
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#endif
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/* GPIO0 UART configuration bits */
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#if CONFIG_STR71X_UART0
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# define STR71X_UART0_GPIO0_MASK (0x0300) /* P0.8->U0.TX, B0.9->U0.RX */
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# define STR71X_UART0_GPIO0_PC0BITS (0x0300)
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# define STR71X_UART0_GPIO0_PC1BITS (0x0200)
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# define STR71X_UART0_GPIO0_PC2BITS (0x0200)
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#else
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# define STR71X_UART0_GPIO0_MASK (0)
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# define STR71X_UART0_GPIO0_PC0BITS (0)
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# define STR71X_UART0_GPIO0_PC1BITS (0)
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# define STR71X_UART0_GPIO0_PC2BITS (0)
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#endif
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#if CONFIG_STR71X_UART0
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# define STR71X_UART1_GPIO0_MASK (0x0c00) /* P0,10->U1.RX, P0.11->U1.TX */
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# define STR71X_UART1_GPIO0_PC0BITS (0x0c00)
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# define STR71X_UART1_GPIO0_PC1BITS (0x0800)
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# define STR71X_UART1_GPIO0_PC2BITS (0x0800)
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#else
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# define STR71X_UART1_GPIO0_MASK (0)
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# define STR71X_UART1_GPIO0_PC0BITS (0)
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# define STR71X_UART1_GPIO0_PC1BITS (0)
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# define STR71X_UART1_GPIO0_PC2BITS (0)
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#endif
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#if CONFIG_STR71X_UART0
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# define STR71X_UART2_GPIO0_MASK (0x6000) /* P0.13->U2.RX, P0.14>U2.TX */
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# define STR71X_UART2_GPIO0_PC0BITS (0x6000)
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# define STR71X_UART2_GPIO0_PC1BITS (0x4000)
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# define STR71X_UART2_GPIO0_PC2BITS (0x4000)
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#else
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# define STR71X_UART2_GPIO0_MASK (0)
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# define STR71X_UART2_GPIO0_PC0BITS (0)
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# define STR71X_UART2_GPIO0_PC1BITS (0)
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# define STR71X_UART2_GPIO0_PC2BITS (0)
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#endif
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#if CONFIG_STR71X_UART0
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# define STR71X_UART3_GPIO0_MASK (0x0003) /* P0.0->U3.TX, P0.1->U3.RX */
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# define STR71X_UART3_GPIO0_PC0BITS (0x0003)
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# define STR71X_UART3_GPIO0_PC1BITS (0x0001)
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# define STR71X_UART3_GPIO0_PC2BITS (0x0001)
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#else
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# define STR71X_UART3_GPIO0_MASK (0)
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# define STR71X_UART3_GPIO0_PC0BITS (0)
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# define STR71X_UART3_GPIO0_PC1BITS (0)
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# define STR71X_UART3_GPIO0_PC2BITS (0)
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#endif
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#define STR71X_UART_GPIO0_MASK (STR71X_UART0_GPIO0_MASK |STR71X_UART1_GPIO0_MASK|\
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STR71X_UART2_GPIO0_MASK |STR71X_UART3_GPIO0_MASK)
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#define STR71X_UART_GPIO0_PC0BITS (STR71X_UART0_GPIO0_PC0BITS|STR71X_UART1_GPIO0_PC0BITS|\
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STR71X_UART2_GPIO0_PC0BITS|STR71X_UART3_GPIO0_PC0BITS)
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#define STR71X_UART_GPIO0_PC1BITS (STR71X_UART0_GPIO0_PC0BITS|STR71X_UART1_GPIO0_PC0BITS|\
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STR71X_UART2_GPIO0_PC0BITS|STR71X_UART3_GPIO0_PC0BITS)
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#define STR71X_UART_GPIO0_PC2BITS (STR71X_UART0_GPIO0_PC0BITS|STR71X_UART1_GPIO0_PC0BITS|\
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STR71X_UART2_GPIO0_PC0BITS|STR71X_UART3_GPIO0_PC0BITS)
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/* Select UART parameters for the selected console */
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#if defined(CONFIG_UART0_SERIAL_CONSOLE)
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# define STR71X_UART_BASE STR71X_UART0_BASE
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# define STR71X_UART_BAUD CONFIG_UART0_BAUD
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# define STR71X_UART_BITS CONFIG_UART0_BITS
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# define STR71X_UART_PARITY CONFIG_UART0_PARITY
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# define STR71X_UART_2STOP CONFIG_UART0_2STOP
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#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
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# define STR71X_UART_BASE STR71X_UART1_BASE
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# define STR71X_UART_BAUD CONFIG_UART1_BAUD
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# define STR71X_UART_BITS CONFIG_UART1_BITS
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# define STR71X_UART_PARITY CONFIG_UART1_PARITY
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# define STR71X_UART_2STOP CONFIG_UART1_2STOP
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#elif defined(CONFIG_UART2_SERIAL_CONSOLE)
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# define STR71X_UART_BASE STR71X_UART2_BASE
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# define STR71X_UART_BAUD CONFIG_UART2_BAUD
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# define STR71X_UART_BITS CONFIG_UART2_BITS
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# define STR71X_UART_PARITY CONFIG_UART2_PARITY
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# define STR71X_UART_2STOP CONFIG_UART2_2STOP
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#elif defined(CONFIG_UART3_SERIAL_CONSOLE)
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# define STR71X_UART_BASE STR71X_UART3_BASE
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# define STR71X_UART_BAUD CONFIG_UART3_BAUD
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# define STR71X_UART_BITS CONFIG_UART3_BITS
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# define STR71X_UART_PARITY CONFIG_UART3_PARITY
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# define STR71X_UART_2STOP CONFIG_UART3_2STOP
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#else
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# error "No CONFIG_UARTn_SERIAL_CONSOLE Setting"
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#endif
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/* Get mode setting */
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#if STR71X_UART_BITS == 7
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# if STR71X_UART_PARITY == 0
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# error "7-bits, no parity mode not supported"
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# else
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# define STR71X_UARTCR_MODE STR71X_UARTCR_MODE7BITP
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# endif
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#elif STR71X_UART_BITS == 8
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# if STR71X_UART_PARITY == 0
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# define STR71X_UARTCR_MODE STR71X_UARTCR_MODE8BIT
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# else
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# define STR71X_UARTCR_MODE STR71X_UARTCR_MODE8BITP
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# endif
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#elif STR71X_UART_BITS == 9
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# if STR71X_UART_PARITY == 0
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# define STR71X_UARTCR_MODE STR71X_UARTCR_MODE9BIT
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# else
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# error "9-bits with parity not supported"
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# endif
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#else
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# error "Number of bits not supported"
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#endif
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#if STR71X_UART_PARITY == 0 || STR71X_UART_PARITY == 2
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# define STR71X_UARTCR_PARITY (0)
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#elif STR71X_UART_PARITY == 1
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# define STR71X_UARTCR_PARITY STR71X_UARTCR_PARITYODD
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#else
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# error "Invalid parity selection"
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#endif
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#if STR71X_UART_2STOP != 0
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# define STR71X_UARTCR_STOP STR71X_UARTCR_STOPBIT20
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#else
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# define STR71X_UARTCR_STOP STR71X_UARTCR_STOPBIT05
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#endif
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#define STR71X_UARTCR_VALUE (STR71X_UARTCR_MODE|STR71X_UARTCR_PARITY|STR71X_UARTCR_STOP|\
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STR71X_UARTCR_RUN|STR71X_UARTCR_RXENABLE|STR71X_UARTCR_FIFOENABLE)
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/* Calculate the value of PCLK1 from settings in board.h.
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*
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* Example:
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* STR71X_RCCU_MAIN_OSC = 4MHz (not divided by 2)
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* CLK2 = 4MHz
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* PLL1OUT = 16 * CLK2 / 2 = 32MHz
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* CLK3 = 32MHz
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* RCLK = 32MHz
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* PCLK1 = 32MHz / 1 = 32MHz
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*/
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#ifdef STR71X_PLL1IN_DIV2 /* Input may be divided by 2 */
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# define CLK2 (STR71X_RCCU_MAIN_OSC/2) /* CLK2 is input to PLL1 */
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#else
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# define CLK2 STR71X_RCCU_MAIN_OSC /* CLK2 is input to PLL1 */
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#endif
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/* PLL1OUT derives from CLK2 */
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#define PLL1OUT (STR71X_PLL1OUT_MUL * CLK2 / STR71X_PLL1OUT_DIV)
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#define CLK3 PLL1OUT /* CLK3 hard coded to be PLL1OUT */
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#define RCLK CLK3 /* RCLK hard coded to be CLK3 */
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#define PCLK1 (RCLK / STR71X_APB1_DIV) /* PCLK1 derives from RCLK */
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/* Calculate BAUD rate from PCLK1:
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*
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* Example:
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* PCLK1 = 32MHz
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* STR71X_UART_BAUD = 38,400
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* UART_BAUDRATE_DIVISOR = 614,400
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* UART_BAUDRATE = 52.583 (exact) or 52 truncated (1.1% error)
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*/
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#define UART_BAUDDIVISOR (16 * STR71X_UART_BAUD)
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#define UART_BAUDRATE ((PCLK1 + (UART_BAUDDIVISOR/2) / UART_BAUDDIVISOR)
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/**************************************************************************
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* Private Types
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**************************************************************************/
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/**************************************************************************
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* Private Function Prototypes
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**************************************************************************/
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/**************************************************************************
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* Global Variables
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**************************************************************************/
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/**************************************************************************
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* Private Variables
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**************************************************************************/
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/**************************************************************************
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* Private Functions
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**************************************************************************/
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/**************************************************************************
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* Public Functions
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**************************************************************************/
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/**************************************************************************
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* Name: up_lowputc
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*
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* Description:
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* Output one byte on the serial console
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*
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**************************************************************************/
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void up_lowputc(char ch)
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{
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#if HAVE_CONSOLE
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uint16 reg16;
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/* Wait until the TX FIFO is not full */
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while (getreg16(STR71X_UART_SR(STR71X_UART_BASE)) & STR71X_UARTSR_TF != 0);
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/* Then send the character */
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putreg16((uint16)ch, STR71X_UART_TXBUFR(STR71X_UART_BASE));
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#endif
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}
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/**************************************************************************
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* Name: up_lowsetup
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*
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* Description:
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* This performs basic initialization of the UART used for the serial
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* console. Its purpose is to get the console output availabe as soon
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* as possible.
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*
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**************************************************************************/
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void up_lowsetup(void)
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{
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#if HAVE_CONSOLE
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uint16 reg16;
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/* Enable the selected console device */
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/* Set the UART baud rate */
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putreg16(UART_BAUDRATE, STR71X_UART_BR(STR71X_UART_BASE));
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/* Configure the UART control registers */
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putreg16(STR71X_UARTCR_VALUE, STR71X_UART_CR(STR71X_UART_BASE));
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/* Clear FIFOs */
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putreg16(0, STR71X_UART2_TXRSTR_(STR71X_UART_BASE));
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putreg16(0, SSTR71X_UART2_RXRSTR(STR71X_UART_BASE));
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#endif
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/* Configure GPIO0 pins to enable all UARTs in the configuration
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* (the serial driver later depends on this configuration)
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*/
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#if HAVE_UART
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reg16 = getreg16(STR71X_GPIO_PC0_OFFSET);
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reg16 &= STR71X_GPIO0_MASK;
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reg16 |= STR71X_GPIO0_PC0BITS;
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putreg16(reg16, STR71X_GPIO_PC0_OFFSET);
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reg16 = getreg16(STR71X_GPIO_PC1_OFFSET);
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reg16 &= STR71X_GPIO0_MASK;
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reg16 |= STR71X_GPIO0_PC1BITS;
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putreg16(reg16, STR71X_GPIO_PC1_OFFSET);
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reg16 = getreg16(STR71X_GPIO_PC2_OFFSET);
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reg16 &= STR71X_GPIO0_MASK;
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reg16 |= STR71X_GPIO0_PC2BITS;
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putreg16(reg16, STR71X_GPIO_PC2_OFFSET);
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#endif
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}
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@ -98,66 +98,3 @@
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************************************************************************************/
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#endif // __ARCH_ARM_SRC_STR71X_STR71X_MAP_H
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/*------------------------ Analog to Digital Converter -----------------------*/
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/*------------------------ APB -----------------------------------------------*/
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/*------------------------ Buffered Serial Peripheral Interface --------------*/
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/*------------------------ Controller Area Network ---------------------------*/
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/*------------------------ Enhanced Interrupt Controller ---------------------*/
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/*------------------------ External Memory Interface -------------------------*/
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/*------------------------ General Purpose IO ports --------------------------*/
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/*------------------------ I2C interface -------------------------------------*/
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/*------------------------ Power Reset Clock Control unit --------------------*/
|
||||
|
||||
|
||||
/*------------------------ Real Time Clock -----------------------------------*/
|
||||
|
||||
/*------------------------ TIM -----------------------------------------------*/
|
||||
|
||||
/*------------------------ Universal Asynchronous Receiver Transmitter -------*/
|
||||
|
||||
|
||||
/*------------------------ WATCHDOG ------------------------------------------*/
|
||||
/*------------------------ External Interrupt Controller ---------------------*/
|
||||
|
||||
|
||||
/* IRQ vectors */
|
||||
typedef struct
|
||||
{
|
||||
volatile uint32 T0TIMI_IRQHandler;
|
||||
volatile uint32 RCCU_IRQHandler;
|
||||
volatile uint32 RTC_IRQHandler;
|
||||
volatile uint32 WDG_IRQHandler;
|
||||
volatile uint32 XTI_IRQHandler;
|
||||
volatile uint32 USBHP_IRQHandler;
|
||||
volatile uint32 I2C0ITERR_IRQHandler;
|
||||
volatile uint32 I2C1ITERR_IRQHandler;
|
||||
volatile uint32 UART0_IRQHandler;
|
||||
volatile uint32 UART1_IRQHandler;
|
||||
volatile uint32 UART2_IRQHandler;
|
||||
volatile uint32 UART3_IRQHandler;
|
||||
volatile uint32 BSPI0_IRQHandler;
|
||||
volatile uint32 BSPI1_IRQHandler;
|
||||
volatile uint32 I2C0_IRQHandler;
|
||||
volatile uint32 I2C1_IRQHandler;
|
||||
volatile uint32 CAN_IRQHandler;
|
||||
volatile uint32 ADC12_IRQHandler;
|
||||
volatile uint32 T1TIMI_IRQHandler;
|
||||
volatile uint32 T2TIMI_IRQHandler;
|
||||
volatile uint32 T3TIMI_IRQHandler;
|
||||
uint32 EMPTY1[3];
|
||||
volatile uint32 HDLC_IRQHandler;
|
||||
volatile uint32 USBLP_IRQHandler;
|
||||
uint32 EMPTY2[2];
|
||||
volatile uint32 T0TOI_IRQHandler;
|
||||
volatile uint32 T0OC1_IRQHandler;
|
||||
volatile uint32 T0OC2_IRQHandler;
|
||||
} IRQVectors_TypeDef;
|
||||
|
||||
1003
arch/arm/src/str71x/str71x_serial.c
Normal file
1003
arch/arm/src/str71x/str71x_serial.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -126,13 +126,13 @@
|
||||
#define STR71X_UARTCR_MODE8BIT (0x0001) /* 8-bit */
|
||||
#define STR71X_UARTCR_MODE7BITP (0x0003) /* 7-bit with parity bit */
|
||||
#define STR71X_UARTCR_MODE9BIT (0x0004) /* 9-bit */
|
||||
#define STR71X_UARTCR_MODE8BIT (0x0005) /* 8-bit with wakeup bit */
|
||||
#define STR71X_UARTCR_MODE8BIT (0x0007) /* 8-bit with parity bit */
|
||||
#define STR71X_UARTCR_MODE8BITWU (0x0005) /* 8-bit with wakeup bit */
|
||||
#define STR71X_UARTCR_MODE8BITP (0x0007) /* 8-bit with parity bit */
|
||||
#define STR71X_UARTCR_STOPBITSMASK (0x0018) /* Bits 3-4: Stop bits */
|
||||
#define STR71X_UARTCR_STOPBIT0 (0x0000) /* 0.5 stop bits */
|
||||
#define STR71X_UARTCR_STOPBIT1 (0x0008) /* 1 stop bit */
|
||||
#define STR71X_UARTCR_STOPBIT0 (0x0010) /* 1.5 stop bits */
|
||||
#define STR71X_UARTCR_STOPBIT0 (0x0018) /* 2 stop bits */
|
||||
#define STR71X_UARTCR_STOPBIT05 (0x0000) /* 0.5 stop bits */
|
||||
#define STR71X_UARTCR_STOPBIT10 (0x0008) /* 1.0 stop bit */
|
||||
#define STR71X_UARTCR_STOPBIT15 (0x0010) /* 1.5 stop bits */
|
||||
#define STR71X_UARTCR_STOPBIT20 (0x0018) /* 2.0 stop bits */
|
||||
#define STR71X_UARTCR_PARITYODD (0x0020) /* Bit 5:
|
||||
#define STR71X_UARTCR_LOOPBACK (0x0040) /* Bit 6:
|
||||
#define STR71X_UARTCR_RUN (0x0080) /* Bit 7:
|
||||
@ -151,6 +151,7 @@
|
||||
#define STR71X_UARTIER_TIMEOUTNE (0x0040) /* Bit 6: Time out not empty*/
|
||||
#define STR71X_UARTIER_TIMEOUTIDLE (0x0080) /* Bit 7: Timeout out idle */
|
||||
#define STR71X_UARTIER_RHF (0x0100) /* Bit 8: Rx half full */
|
||||
#define STR71X_UIRTIER_ALL (0x01ff) /* All interrupt bits */
|
||||
|
||||
/* UART status register (SR) */
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user