arch/armv7-a: Remove the special SMP SGI process
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com> Change-Id: Iaf7fe77a3ab7cbf145d907dafb0b7ca54cc4a012
This commit is contained in:
Xiang Xiao
Masayuki Ishikawa
parent
13651cde99
commit
e97ffb1f79
@ -39,38 +39,29 @@
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#include "group/group.h"
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#include "gic.h"
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/* A bit set of pending, non-maskable SGI interrupts, on bit set for each
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* supported CPU.
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*/
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#ifdef CONFIG_ARMV7A_HAVE_GICv2
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#ifdef CONFIG_SMP
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static uint16_t g_sgi_pending[CONFIG_SMP_NCPUS];
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#else
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static uint16_t g_sgi_pending[1];
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#endif
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#endif
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: _arm_doirq
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* Name: arm_doirq
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*
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* Description:
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* Receives the one decoded interrupt and dispatches control to the
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* attached interrupt handler.
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* Receives the decoded GIC interrupt information and dispatches control
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* to the attached interrupt handler.
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*
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****************************************************************************/
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#ifndef CONFIG_SUPPRESS_INTERRUPTS
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static inline uint32_t *_arm_doirq(int irq, uint32_t *regs)
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uint32_t *arm_doirq(int irq, uint32_t *regs)
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{
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board_autoled_on(LED_INIRQ);
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#ifdef CONFIG_SUPPRESS_INTERRUPTS
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PANIC();
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#else
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/* Nested interrupts are not supported */
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DEBUGASSERT(CURRENT_REGS == NULL);
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/* Current regs non-zero indicates that we are processing an interrupt;
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* CURRENT_REGS is also used to manage interrupt level context switches.
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*/
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@ -115,131 +106,8 @@ static inline uint32_t *_arm_doirq(int irq, uint32_t *regs)
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regs = (uint32_t *)CURRENT_REGS;
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CURRENT_REGS = NULL;
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return regs;
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}
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#endif
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: arm_doirq
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*
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* Description:
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* Receives the decoded GIC interrupt information and dispatches control
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* to the attached interrupt handler. There are two versions:
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*
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* 1) For the simple case where all interrupts are maskable. In that
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* simple case, arm_doirq() is simply a wrapper for the inlined
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* _arm_do_irq() that does the real work.
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*
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* 2) With the GICv2, there are 16 non-maskable software generated
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* interrupts (SGIs) that also come through arm_doirq(). In that case,
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* we must avoid nesting interrupt handling and serial the processing.
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*
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****************************************************************************/
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#ifndef CONFIG_ARMV7A_HAVE_GICv2
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uint32_t *arm_doirq(int irq, uint32_t *regs)
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{
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board_autoled_on(LED_INIRQ);
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#ifdef CONFIG_SUPPRESS_INTERRUPTS
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PANIC();
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#else
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/* Nested interrupts are not supported */
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DEBUGASSERT(CURRENT_REGS == NULL);
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/* Dispatch the interrupt to its attached handler */
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regs = _arm_doirq(irq, regs);
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#endif
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board_autoled_off(LED_INIRQ);
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return regs;
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}
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#endif
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#ifdef CONFIG_ARMV7A_HAVE_GICv2
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uint32_t *arm_doirq(int irq, uint32_t *regs)
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{
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#ifndef CONFIG_SUPPRESS_INTERRUPTS
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uint32_t bit;
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int cpu;
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int i;
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#endif
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board_autoled_on(LED_INIRQ);
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#ifdef CONFIG_SUPPRESS_INTERRUPTS
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PANIC();
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#else
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/* Get the CPU processing the interrupt */
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#ifdef CONFIG_SMP
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cpu = up_cpu_index();
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#else
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cpu = 0;
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#endif
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/* Non-zero CURRENT_REGS indicates that we are already processing an
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* interrupt. This could be a normal event for the case of the GICv2;
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* Software generated interrupts are non-maskable.
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*
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* REVISIT: There is no support for nested SGIs! That will cause an
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* assertion below. There is also no protection for concurrent access
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* to g_sgi_pending for that case.
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*/
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if (CURRENT_REGS != NULL)
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{
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int ndx = irq - GIC_IRQ_SGI0;
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bit = (1 << (ndx));
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/* Only an SGI should cause this event. We also cannot support
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* multiple pending SGI interrupts.
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*/
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DEBUGASSERT((unsigned int)irq <= GIC_IRQ_SGI15 &&
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(g_sgi_pending[cpu] & bit) == 0);
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/* Mare the SGI as pending and return immediately */
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sinfo("SGI%d pending\n", ndx);
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g_sgi_pending[cpu] |= bit;
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return regs;
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}
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/* Dispatch the interrupt to its attached handler */
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regs = _arm_doirq(irq, regs);
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/* Then loop dispatching any pending SGI interrupts that occcurred during
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* processing of the interrupts.
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*/
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for (i = 0; i < 16 && g_sgi_pending[cpu] != 0; i++)
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{
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/* Check if this SGI is pending */
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bit = (1 << i);
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if ((g_sgi_pending[cpu] & bit) != 0)
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{
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/* Clear the pending bit */
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g_sgi_pending[cpu] &= ~bit;
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/* And dispatch the SGI */
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sinfo("Dispatching pending SGI%d\n", i + GIC_IRQ_SGI0);
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regs = _arm_doirq(i + GIC_IRQ_SGI0, regs);
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}
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}
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#endif
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board_autoled_off(LED_INIRQ);
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return regs;
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}
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#endif
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@ -175,30 +175,6 @@ Status
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But this does not completely eliminate instabilities which seem to be
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related to memory corruption -- mm_mallinfo() asserts.
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CORTEX-A GIC SGI INTERRUPT MASKING (From the top-level TODO list)
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-----------------------------------------------------------------
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In the ARMv7-A GICv2 architecture, the inter-processor interrupts (SGIs) are
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non maskable and will occur even if interrupts are disabled. This adds a
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lot of complexity to the ARMV7-A critical section design.
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Masayuki Ishikawa has suggested the use of the GICv2 ICCMPR register to
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control SGI interrupts. This register (much like the ARMv7-M BASEPRI
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register) can be used to mask interrupts by interrupt priority. Since SGIs
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may be assigned priorities the ICCMPR should be able to block execution of
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SGIs as well.
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Such an implementation would be very similar to the BASEPRI (vs PRIMASK)
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implementation for the ARMv7-M: (1) The up_irq_save() and up_irq_restore()
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registers would have to set/restore the ICCMPR register, (2) register setup
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logic in arch/arm/src/armv7-a for task start-up and signal dispatch would
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have to set the ICCMPR correctly, and (3) the 'xcp' structure would have to
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be extended to hold the ICCMPR register; logic would have to added be
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save/restore the ICCMPR register in the 'xcp' structure on each interrupt
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and context switch.
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This would also be an essential part of a high priority, nested interrupt
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implementation (unrelated feature).
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Platform Features
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=================
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