LPC43xx: Add RS485 configuration settings to Kconfig; For RS485, add an option to select DTR as the DIR pin
This commit is contained in:
Gregory Nutt
parent
9b96057dc0
commit
e9bf66989e
@ -67,7 +67,7 @@ config ARCH_CHIP_LPC4357FET256
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config ARCH_CHIP_LPC4370FET100
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bool "LPC4370FET100"
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endchoice
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endchoice # LPC43XX Chip Selection
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config ARCH_FAMILY_LPC4310
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bool
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@ -143,7 +143,7 @@ config LPC43_BOOT_CS2FLASH
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config LPC43_BOOT_CS3FLASH
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bool "Running in external FLASH CS3"
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endchoice
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endchoice # LPC43XX Boot Configuration
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menu "LPC43xx Peripheral Support"
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@ -179,6 +179,138 @@ config LPC43_ETHERNET
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bool "Ethernet"
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default n
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config LPC43_EVNTMNTR
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bool "Event Monitor"
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default n
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config LPC43_GPDMA
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bool "GPDMA"
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default n
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config LPC43_I2C0
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bool "I2C0"
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default n
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config LPC43_I2C1
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bool "I2C1"
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default n
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config LPC43_I2S0
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bool "I2S0"
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default n
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config LPC43_I2S1
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bool "I2S1"
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default n
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config LPC43_LCD
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bool "LCD"
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default n
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config LPC43_MCPWM
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bool "Motor Control PWM (MCPWM)"
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default n
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config LPC43_QEI
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bool "Quadrature Controller Interface (QEI)"
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default n
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config LPC43_RIT
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bool "Repetitive Interrupt Timer (RIT)"
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default n
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config LPC43_RIT_RES
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int "Interrupt schedule resolution (nS)"
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default 250
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depends on LPC43_RIT
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config LPC43_RTC
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bool "Real Time Clock (RTC)"
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default n
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config LPC43_SCT
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bool "State Configurable Timer (SCT)"
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default n
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config LPC43_SDMMC
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bool "SD/MMC"
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default n
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config LPC43_SPI
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bool "SPI"
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default n
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config LPC43_SPIFI
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bool "SPI Flash Interface (SPIFI)"
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default n
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config LPC43_SSP0
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bool "SSP0"
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default n
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config LPC43_SSP1
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bool "SSP1"
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default n
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config LPC43_TMR0
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bool "ADC1"
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default n
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config LPC43_TMR1
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bool "Timer 1"
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default n
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config LPC43_TMR2
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bool "Timer 2"
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default n
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config LPC43_TMR3
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bool "Timer 3"
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default n
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config LPC43_USART0
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bool "USART0"
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default n
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select ARCH_HAVE_USART0
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select ARCH_HAVE_SERIAL_TERMIOS
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config LPC43_UART1
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bool "UART1"
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default n
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select ARCH_HAVE_UART1
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select ARCH_HAVE_SERIAL_TERMIOS
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config LPC43_USART2
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bool "USART2"
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default n
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select ARCH_HAVE_USART2
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select ARCH_HAVE_SERIAL_TERMIOS
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config LPC43_USART3
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bool "USART3"
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default n
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select ARCH_HAVE_USART3
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select ARCH_HAVE_SERIAL_TERMIOS
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config LPC43_USBOTG
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bool "USB EHCI"
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default n
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select USBHOST_HAVE_ASYNCH
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config LPC43_USB0
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bool "USB0"
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default n
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config LPC43_USB1
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bool "USB1"
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default n
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config LPC43_WWDT
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bool "Windowing Watchdog Timer (WWDT)"
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default n
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endmenu # LPC43xx Peripheral Support
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if LPC43_ETHERNET
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menu "Ethernet MAC configuration"
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@ -313,7 +445,6 @@ config LPC43_RMII
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bool
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default y if !LPC43_MII
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config LPC43_ETHERNET_REGDEBUG
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bool "Register-Level Debug"
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default n
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@ -321,131 +452,121 @@ config LPC43_ETHERNET_REGDEBUG
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---help---
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Enable very low-level register access debug. Depends on DEBUG.
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endmenu
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endif
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endmenu # Ethernet MAC configuration
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endif # LPC43_ETHERNET
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config LPC43_EVNTMNTR
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bool "Event Monitor"
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default n
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menu "RS-485 Configuration"
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if LPC43_USART0
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config LPC43_GPDMA
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bool "GPDMA"
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config USART0_RS485MODE
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bool "RS-485 on USART0"
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default n
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---help---
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Enable RS-485 interface on USART0.
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config LPC43_I2C0
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bool "I2C0"
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config USART0_RS485_DTRDIR
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bool "USART0 DTR for DIR"
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default n
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---help---
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Use the USART DTR pin for the DIR pin
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endif # LPC43_USART0
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if LPC43_UART1
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config UART1_RS485MODE
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bool "RS-485 on UART1"
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default n
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---help---
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Enable RS-485 interface on USRT1.
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config UART1_RS485_DTRDIR
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bool "UART1 DTR for DIR"
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default n
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---help---
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Use the UART DTR pin for the DIR pin
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endif # LPC43_USART0
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if LPC43_USART2
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config USART2_RS485MODE
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bool "RS-485 on USART2"
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default n
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---help---
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Enable RS-485 interface on USART2.
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config USART2_RS485_DTRDIR
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bool "USART2 DTR for DIR"
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default n
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---help---
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Use the USART DTR pin for the DIR pin
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endif # LPC43_USART2
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if LPC43_USART3
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config USART3_RS485MODE
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bool "RS-485 on USART3"
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default n
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---help---
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Enable RS-485 interface on USART3.
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config USART3_RS485_DTRDIR
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bool "USART3 DTR for DIR"
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default n
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---help---
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Use the USART DTR pin for the DIR pin
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endif # LPC43_USART3
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endmenu # RS-485 Configuration
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if LPC43_I2C0
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menu "I2C Configution"
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config LPC43_I2C0_SUPERFAST
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bool "I2C0 super fast mode"
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default n
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depends on LPC43_I2C0
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config LPC43_I2C1
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bool "I2C1"
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default n
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endmenu # I2C Configution
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endif # LPC43_I2C0
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config LPC43_I2S0
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bool "I2S0"
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default n
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if LPC43_USBOTG && USBHOST
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menu "USB host controller driver (HCD) options"
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config LPC43_I2S1
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bool "I2S1"
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default n
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config LPC43_EHCI_NQHS
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int "Number of Queue Head (QH) structures"
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default 4
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---help---
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Configurable number of Queue Head (QH) structures. The default is
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one per Root hub port plus one for EP0 (4).
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config LPC43_LCD
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bool "LCD"
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default n
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config LPC43_EHCI_NQTDS
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int "Number of Queue Element Transfer Descriptor (qTDs)"
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default 6
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---help---
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Configurable number of Queue Element Transfer Descriptor (qTDs).
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The default is one per root hub plus three from EP0 (6).
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config LPC43_MCPWM
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bool "Motor Control PWM (MCPWM)"
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default n
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config LPC43_EHCI_BUFSIZE
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int "Size of one request/descriptor buffer"
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default 128
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---help---
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The size of one request/descriptor buffer in bytes. The TD buffe
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size must be an even number of 32-bit words and must be large enough
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to hangle the largest transfer via a SETUP request.
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config LPC43_QEI
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bool "Quadrature Controller Interface (QEI)"
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default n
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config LPC43_EHCI_PREALLOCATE
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bool "Preallocate descriptor pool"
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default y
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---help---
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Select this option to pre-allocate EHCI queue and descriptor
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structure pools in .bss. Otherwise, these pools will be
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dynamically allocated using kmm_memalign().
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config LPC43_RIT
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bool "Repetitive Interrupt Timer (RIT)"
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default n
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config LPC43_RIT_RES
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int "Interrupt schedule resolution (nS)"
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default 250
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depends on LPC43_RIT
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config LPC43_RTC
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bool "Real Time Clock (RTC)"
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default n
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config LPC43_SCT
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bool "State Configurable Timer (SCT)"
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default n
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config LPC43_SDMMC
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bool "SD/MMC"
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default n
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config LPC43_SPI
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bool "SPI"
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default n
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config LPC43_SPIFI
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bool "SPI Flash Interface (SPIFI)"
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default n
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config LPC43_SSP0
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bool "SSP0"
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default n
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config LPC43_SSP1
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bool "SSP1"
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default n
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config LPC43_TMR0
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bool "ADC1"
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default n
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config LPC43_TMR1
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bool "Timer 1"
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default n
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config LPC43_TMR2
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bool "Timer 2"
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default n
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config LPC43_TMR3
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bool "Timer 3"
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default n
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config LPC43_USART0
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bool "USART0"
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default n
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select ARCH_HAVE_USART0
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select ARCH_HAVE_SERIAL_TERMIOS
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config LPC43_UART1
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bool "UART1"
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default n
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select ARCH_HAVE_UART1
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select ARCH_HAVE_SERIAL_TERMIOS
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config LPC43_USART2
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bool "USART2"
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default n
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select ARCH_HAVE_USART2
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select ARCH_HAVE_SERIAL_TERMIOS
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config LPC43_USART3
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bool "USART3"
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default n
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select ARCH_HAVE_USART3
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select ARCH_HAVE_SERIAL_TERMIOS
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config LPC43_USBOTG
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bool "USB EHCI"
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default n
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select USBHOST_HAVE_ASYNCH
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endmenu # USB host controller driver (HCD) options
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endif # LPC43_USBOTG && USBHOST
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if LPC43_USBOTG && USBHOST
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@ -484,31 +605,24 @@ config LPC43_EHCI_PREALLOCATE
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endmenu # USB host controller driver (HCD) options
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endif # LPC43_USBOTG && USBHOST
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config LPC43_USB0
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bool "USB0"
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default n
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if LPC43_USB0 || LPC43_USB1
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menu "USB device controller driver (DCD) options"
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config LPC43_USB0DEV_NOVBUS
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bool "No USB0 VBUS sensing"
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default n
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depends on LPC43_USB0 && USBDEV
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config LPC43_USB1
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bool "USB1"
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config LPC43_USB1_ULPI
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bool "USB1 with ULPI"
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default n
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depends on LPC43_USB1
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config LPC43_USB1DEV_NOVBUS
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bool "No USB1 VBUS sensing"
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default n
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depends on LPC43_USB1 && USBDEV
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config LPC43_USB1_ULPI
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bool "USB1 with ULPI"
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default n
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depends on LPC43_USB1
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config LPC43_WWDT
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bool "Windowing Watchdog Timer (WWDT)"
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default n
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endmenu
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endmenu # USB device controller driver (DCD) options
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endif # LPC43_USB0 || LPC43_USB1
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@ -73,20 +73,25 @@
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#ifndef CONFIG_LPC43_USART0
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# undef CONFIG_USART0_SERIAL_CONSOLE
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# undef CONFIG_USART0_RS485MODE
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# undef CONFIG_USART0_RS485_DTRDIR
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#endif
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#ifndef CONFIG_LPC43_UART1
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# undef CONFIG_UART1_SERIAL_CONSOLE
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# undef CONFIG_UART1_RS485MODE
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# undef CONFIG_UART1_RS485_DTRDIR
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#endif
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#ifndef CONFIG_LPC43_USART2
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# undef CONFIG_USART2_SERIAL_CONSOLE
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# undef CONFIG_USART2_RS485MODE
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# undef CONFIG_USART2_RS485_DTRDIR
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#endif
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#ifndef CONFIG_LPC43_USART3
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# undef CONFIG_USART3_SERIAL_CONSOLE
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# undef CONFIG_USART3_RS485MODE
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# undef CONFIG_USART3_RS485_DTRDIR
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#endif
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/* Is there a serial console? There should be at most one defined. It could be on
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@ -1,7 +1,7 @@
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/****************************************************************************
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* arch/arm/src/lpc43xx/lpc43_serial.c
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*
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* Copyright (C) 2012-2013 Gregory Nutt. All rights reserved.
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* Copyright (C) 2012-2013, 2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -91,6 +91,9 @@ struct up_dev_s
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uint8_t parity; /* 0=none, 1=odd, 2=even */
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uint8_t bits; /* Number of bits (7 or 8) */
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bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */
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#ifdef HAVE_RS485
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bool dtrdir; /* DTR pin is the direction bit */
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#endif
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};
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/****************************************************************************
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@ -166,6 +169,9 @@ static struct up_dev_s g_uart0priv =
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.parity = CONFIG_USART0_PARITY,
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.bits = CONFIG_USART0_BITS,
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.stopbits2 = CONFIG_USART0_2STOP,
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#if defined(CONFIG_USART0_RS485MODE) && defined(CONFIG_USART0_RS485_DTRDIR)
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.dtrdir = true;
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#endif
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};
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static uart_dev_t g_uart0port =
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@ -198,6 +204,9 @@ static struct up_dev_s g_uart1priv =
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.parity = CONFIG_UART1_PARITY,
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.bits = CONFIG_UART1_BITS,
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.stopbits2 = CONFIG_UART1_2STOP,
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#if defined(CONFIG_UART1_RS485MODE) && defined(CONFIG_UART1_RS485_DTRDIR)
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.dtrdir = true;
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#endif
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};
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static uart_dev_t g_uart1port =
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@ -230,6 +239,9 @@ static struct up_dev_s g_uart2priv =
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.parity = CONFIG_USART2_PARITY,
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.bits = CONFIG_USART2_BITS,
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.stopbits2 = CONFIG_USART2_2STOP,
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#if defined(CONFIG_USART2_RS485MODE) && defined(CONFIG_USART2_RS485_DTRDIR)
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.dtrdir = true;
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#endif
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};
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static uart_dev_t g_uart2port =
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@ -262,6 +274,9 @@ static struct up_dev_s g_uart3priv =
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.parity = CONFIG_USART3_PARITY,
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.bits = CONFIG_USART3_BITS,
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.stopbits2 = CONFIG_USART3_2STOP,
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#if defined(CONFIG_USART3_RS485MODE) && defined(CONFIG_USART3_RS485_DTRDIR)
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.dtrdir = true;
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#endif
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};
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static uart_dev_t g_uart3port =
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@ -939,7 +954,8 @@ static inline int up_set_rs485_mode(struct up_dev_s *priv,
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* RXDIS 0 = Receiver is not disabled
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* AADEN 0 = Auto Address Detect (ADD) is disabled
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* DCTRL 1 = Auto Direction Control is enabled
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* OINV ? = Value control by user mode settings
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* OINV ? = Value controlle by user mode settings
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* SEL ? = Value controlled by user mode settings
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*/
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regval = UART_RS485CTRL_DCTRL;
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@ -957,6 +973,17 @@ static inline int up_set_rs485_mode(struct up_dev_s *priv,
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regval |= UART_RS485CTRL_OINV;
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}
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|
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#ifdef BOARD_LPC43_UART1_DTRDIR
|
||||
if (priv->dtrdir)
|
||||
{
|
||||
/* If we ar using DTR for direction then ensure the H/W is
|
||||
* configured correctly.
|
||||
*/
|
||||
|
||||
regval |= UART_RS485CTRL_SEL;
|
||||
}
|
||||
#endif
|
||||
|
||||
up_serialout(priv, LPC43_UART_RS485CTRL_OFFSET, regval);
|
||||
|
||||
/* We only have control of the delay after send. Time provided
|
||||
|
||||
Loading…
Reference in New Issue
Block a user